From 2e34c2ac16ee6574743c73caa3d796e307f028a6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Jun 2016 12:52:30 +0200 Subject: clk: tegra: Make sor_safe the parent of dpaux and dpaux1 It turns out that sor_safe, rather than pll_p, is the parent of the dpaux and dpaux1 clocks. Acked-by: Jon Hunter Tested-by: Jon Hunter Acked-by: Rhyland Klein Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-tegra210.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk/tegra') diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index aab32af77aa2..fe295b4102ca 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 2); clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; - clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, 1, 17, 181); clks[TEGRA210_CLK_DPAUX] = clk; - clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base, + clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, 1, 17, 207); clks[TEGRA210_CLK_DPAUX1] = clk; -- cgit v1.2.3