From b0f0daa8fe9e74b85f6360288d38224ad1c2f2f4 Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Thu, 2 Mar 2017 22:55:27 +0200 Subject: clk: sunxi-ng: sun5i: Fix mux width for csi clock Mux for CSI clock is 3 bits, not 2. Signed-off-by: Priit Laes Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/sunxi-ng/ccu-sun5i.c') diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c index 06edaa523479..5c476f966a72 100644 --- a/drivers/clk/sunxi-ng/ccu-sun5i.c +++ b/drivers/clk/sunxi-ng/ccu-sun5i.c @@ -469,7 +469,7 @@ static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1", static const u8 csi_table[] = { 0, 1, 2, 5, 6 }; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table, - 0x134, 0, 5, 24, 2, BIT(31), 0); + 0x134, 0, 5, 24, 3, BIT(31), 0); static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve", 0x13c, BIT(31), CLK_SET_RATE_PARENT); -- cgit v1.2.3