From defadcc956cacfb36ecf9902bd56dc5a14fdec49 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 12 Sep 2018 15:16:41 +0200 Subject: clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume cycle, otherwise TM2(e) boards hangs before entering the suspend mode. Signed-off-by: Marek Szyprowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5433.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk/samsung') diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 13384f4911c7..751e2c4fb65b 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -180,6 +180,8 @@ static const unsigned long top_clk_regs[] __initconst = { static const struct samsung_clk_reg_dump top_suspend_regs[] = { /* force all aclk clocks enabled */ { ENABLE_ACLK_TOP, 0x67ecffed }, + /* force all sclk_uart clocks enabled */ + { ENABLE_SCLK_TOP_PERIC, 0x38 }, /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ { ISP_PLL_CON0, 0x85cc0502 }, /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ -- cgit v1.2.3