From 4f89f7b59a6ea17e81cff212c18a0b580ff5ff27 Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Mon, 3 Dec 2018 09:13:43 -0700 Subject: clk: qcom: Fix MSM8998 resets The offsets for the defined BCR reset registers does not match the hardware documentation. Update the values to match the hardware documentation. Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver) Signed-off-by: Jeffrey Hugo Reviewed-by: Bjorn Andersson Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 9f0ae403d5f5..c3bb9fffd040 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2742,25 +2742,25 @@ static struct gdsc *gcc_msm8998_gdscs[] = { }; static const struct qcom_reset_map gcc_msm8998_resets[] = { - [GCC_BLSP1_QUP1_BCR] = { 0x102400 }, - [GCC_BLSP1_QUP2_BCR] = { 0x110592 }, - [GCC_BLSP1_QUP3_BCR] = { 0x118784 }, - [GCC_BLSP1_QUP4_BCR] = { 0x126976 }, - [GCC_BLSP1_QUP5_BCR] = { 0x135168 }, - [GCC_BLSP1_QUP6_BCR] = { 0x143360 }, - [GCC_BLSP2_QUP1_BCR] = { 0x155648 }, - [GCC_BLSP2_QUP2_BCR] = { 0x163840 }, - [GCC_BLSP2_QUP3_BCR] = { 0x172032 }, - [GCC_BLSP2_QUP4_BCR] = { 0x180224 }, - [GCC_BLSP2_QUP5_BCR] = { 0x188416 }, - [GCC_BLSP2_QUP6_BCR] = { 0x196608 }, - [GCC_PCIE_0_BCR] = { 0x438272 }, - [GCC_PDM_BCR] = { 0x208896 }, - [GCC_SDCC2_BCR] = { 0x81920 }, - [GCC_SDCC4_BCR] = { 0x90112 }, - [GCC_TSIF_BCR] = { 0x221184 }, - [GCC_UFS_BCR] = { 0x479232 }, - [GCC_USB_30_BCR] = { 0x61440 }, + [GCC_BLSP1_QUP1_BCR] = { 0x19000 }, + [GCC_BLSP1_QUP2_BCR] = { 0x1b000 }, + [GCC_BLSP1_QUP3_BCR] = { 0x1d000 }, + [GCC_BLSP1_QUP4_BCR] = { 0x1f000 }, + [GCC_BLSP1_QUP5_BCR] = { 0x21000 }, + [GCC_BLSP1_QUP6_BCR] = { 0x23000 }, + [GCC_BLSP2_QUP1_BCR] = { 0x26000 }, + [GCC_BLSP2_QUP2_BCR] = { 0x28000 }, + [GCC_BLSP2_QUP3_BCR] = { 0x2a000 }, + [GCC_BLSP2_QUP4_BCR] = { 0x2c000 }, + [GCC_BLSP2_QUP5_BCR] = { 0x2e000 }, + [GCC_BLSP2_QUP6_BCR] = { 0x30000 }, + [GCC_PCIE_0_BCR] = { 0x6b000 }, + [GCC_PDM_BCR] = { 0x33000 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_TSIF_BCR] = { 0x36000 }, + [GCC_UFS_BCR] = { 0x75000 }, + [GCC_USB_30_BCR] = { 0xf000 }, }; static const struct regmap_config gcc_msm8998_regmap_config = { -- cgit v1.2.3 From 11832328c5640d2dd25e8f909b3142252379737f Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 5 Dec 2018 15:48:45 -0800 Subject: clk: qcom: Add xo dummy clk on msm8998 We have this dummy factor clk in place to workaround a missing rpm clk driver that can manage the XO clk state. Add it in to match what we do on msm8996. Cc: Jeffrey Hugo Cc: Marc Gonzalez Tested-by: Jeffrey Hugo Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index c3bb9fffd040..d72b908137e2 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -117,6 +117,17 @@ static const char * const gcc_parent_names_5[] = { "core_bi_pll_test_se", }; +static struct clk_fixed_factor xo = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "xo", + .parent_names = (const char *[]){ "xo_board" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + static struct pll_vco fabia_vco[] = { { 250000000, 2000000000, 0 }, { 125000000, 1000000000, 1 }, @@ -2798,6 +2809,10 @@ static int gcc_msm8998_probe(struct platform_device *pdev) if (ret) return ret; + ret = devm_clk_hw_register(&pdev->dev, &xo.hw); + if (ret) + return ret; + return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); } -- cgit v1.2.3 From c0cb7c7e716471136b43760778c95eacaa54449a Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Tue, 4 Dec 2018 08:13:22 -0700 Subject: clk: qcom: Enumerate remaining msm8998 resets The current list of defined resets is incomplete compared to what the hardware implements. Enumerate the remaining resets according to the hardware documentation. Signed-off-by: Jeffrey Hugo Acked-by: Bjorn Andersson Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 87 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index d72b908137e2..fef7cf3ffada 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2772,6 +2772,93 @@ static const struct qcom_reset_map gcc_msm8998_resets[] = { [GCC_TSIF_BCR] = { 0x36000 }, [GCC_UFS_BCR] = { 0x75000 }, [GCC_USB_30_BCR] = { 0xf000 }, + [GCC_SYSTEM_NOC_BCR] = { 0x4000 }, + [GCC_CONFIG_NOC_BCR] = { 0x5000 }, + [GCC_AHB2PHY_EAST_BCR] = { 0x7000 }, + [GCC_IMEM_BCR] = { 0x8000 }, + [GCC_PIMEM_BCR] = { 0xa000 }, + [GCC_MMSS_BCR] = { 0xb000 }, + [GCC_QDSS_BCR] = { 0xc000 }, + [GCC_WCSS_BCR] = { 0x11000 }, + [GCC_BLSP1_BCR] = { 0x17000 }, + [GCC_BLSP1_UART1_BCR] = { 0x1a000 }, + [GCC_BLSP1_UART2_BCR] = { 0x1c000 }, + [GCC_BLSP1_UART3_BCR] = { 0x1e000 }, + [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 }, + [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 }, + [GCC_BLSP2_BCR] = { 0x25000 }, + [GCC_BLSP2_UART1_BCR] = { 0x27000 }, + [GCC_BLSP2_UART2_BCR] = { 0x29000 }, + [GCC_BLSP2_UART3_BCR] = { 0x2b000 }, + [GCC_SRAM_SENSOR_BCR] = { 0x2d000 }, + [GCC_PRNG_BCR] = { 0x34000 }, + [GCC_TSIF_0_RESET] = { 0x36024 }, + [GCC_TSIF_1_RESET] = { 0x36028 }, + [GCC_TCSR_BCR] = { 0x37000 }, + [GCC_BOOT_ROM_BCR] = { 0x38000 }, + [GCC_MSG_RAM_BCR] = { 0x39000 }, + [GCC_TLMM_BCR] = { 0x3a000 }, + [GCC_MPM_BCR] = { 0x3b000 }, + [GCC_SEC_CTRL_BCR] = { 0x3d000 }, + [GCC_SPMI_BCR] = { 0x3f000 }, + [GCC_SPDM_BCR] = { 0x40000 }, + [GCC_CE1_BCR] = { 0x41000 }, + [GCC_BIMC_BCR] = { 0x44000 }, + [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 }, + [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 }, + [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 }, + [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 }, + [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 }, + [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 }, + [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c }, + [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 }, + [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 }, + [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 }, + [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 }, + [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 }, + [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 }, + [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 }, + [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 }, + [GCC_APB2JTAG_BCR] = { 0x4c000 }, + [GCC_RBCPR_CX_BCR] = { 0x4e000 }, + [GCC_RBCPR_MX_BCR] = { 0x4f000 }, + [GCC_USB3_PHY_BCR] = { 0x50020 }, + [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, + [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, + [GCC_SSC_BCR] = { 0x63000 }, + [GCC_SSC_RESET] = { 0x63020 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, + [GCC_PCIE_PHY_BCR] = { 0x6f000 }, + [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c }, + [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 }, + [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 }, + [GCC_GPU_BCR] = { 0x71000 }, + [GCC_SPSS_BCR] = { 0x72000 }, + [GCC_OBT_ODT_BCR] = { 0x73000 }, + [GCC_VS_BCR] = { 0x7a000 }, + [GCC_MSS_VS_RESET] = { 0x7a100 }, + [GCC_GPU_VS_RESET] = { 0x7a104 }, + [GCC_APC0_VS_RESET] = { 0x7a108 }, + [GCC_APC1_VS_RESET] = { 0x7a10c }, + [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 }, + [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 }, + [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 }, + [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 }, + [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 }, + [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 }, + [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 }, + [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 }, + [GCC_AGGRE1_NOC_BCR] = { 0x82000 }, + [GCC_AGGRE2_NOC_BCR] = { 0x83000 }, + [GCC_DCC_BCR] = { 0x84000 }, + [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 }, + [GCC_IPA_BCR] = { 0x89000 }, + [GCC_GLM_BCR] = { 0x8b000 }, + [GCC_SKL_BCR] = { 0x8c000 }, + [GCC_MSMPU_BCR] = { 0x8d000 }, }; static const struct regmap_config gcc_msm8998_regmap_config = { -- cgit v1.2.3 From b0d2e8a0cde9dc6cd0154b15f4a58462878e87e8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 3 Dec 2018 10:33:28 -0800 Subject: clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_at Disabling gcc_hmss_dvm_bus_clk and gcc_lpass_at_clk causes the board to lock up, and by that preventing the kernel to boot without clk_ignore_unused. gcc_hmss_dvm_bus_clk is marked always-on downstream, but not referenced, and gcc_lpass_at_clk isn't mentioned. So let's remove them until they are needed by some client. Signed-off-by: Bjorn Andersson Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 28 ---------------------------- 1 file changed, 28 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index fef7cf3ffada..664bdaf4127e 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -1975,19 +1975,6 @@ static struct clk_branch gcc_hmss_at_clk = { }, }; -static struct clk_branch gcc_hmss_dvm_bus_clk = { - .halt_reg = 0x4808c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4808c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_hmss_dvm_bus_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_hmss_rbcpr_clk = { .halt_reg = 0x48008, .halt_check = BRANCH_HALT, @@ -2018,19 +2005,6 @@ static struct clk_branch gcc_hmss_trig_clk = { }, }; -static struct clk_branch gcc_lpass_at_clk = { - .halt_reg = 0x47020, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x47020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_lpass_at_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_lpass_trig_clk = { .halt_reg = 0x4701c, .halt_check = BRANCH_HALT, @@ -2664,10 +2638,8 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr, - [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr, [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr, - [GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr, [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr, [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr, -- cgit v1.2.3 From 2abf856202fd3e4883e4c518acaa9a023b0dbe54 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 3 Dec 2018 10:33:29 -0800 Subject: clk: qcom: gcc-msm8998: Disable halt check of UFS clocks Drop the halt check of the UFS symbol clocks, in accordance with other platforms. This makes clk_disable_unused() happy and makes it possible to turn the clocks on again without an error. Signed-off-by: Bjorn Andersson Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 664bdaf4127e..c1819ef6abab 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2386,7 +2386,7 @@ static struct clk_branch gcc_ufs_phy_aux_clk = { static struct clk_branch gcc_ufs_rx_symbol_0_clk = { .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x75014, .enable_mask = BIT(0), @@ -2399,7 +2399,7 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { static struct clk_branch gcc_ufs_rx_symbol_1_clk = { .halt_reg = 0x7605c, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x7605c, .enable_mask = BIT(0), @@ -2412,7 +2412,7 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { static struct clk_branch gcc_ufs_tx_symbol_0_clk = { .halt_reg = 0x75010, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x75010, .enable_mask = BIT(0), -- cgit v1.2.3 From 30bc0b9881f3a3bbe4e20c2176c53c34fcc287a5 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 3 Dec 2018 10:33:30 -0800 Subject: clk: qcom: gcc-msm8998: Add clkref clocks Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all sourced off CXO_IN, so parent them off "xo" until a proper link to the rpmcc can be described in DT. Signed-off-by: Bjorn Andersson Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 75 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index c1819ef6abab..5f989eee43e4 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2526,6 +2526,76 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { }, }; +static struct clk_branch gcc_hdmi_clkref_clk = { + .halt_reg = 0x88000, + .clkr = { + .enable_reg = 0x88000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hdmi_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_clkref_clk = { + .halt_reg = 0x88004, + .clkr = { + .enable_reg = 0x88004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_clkref_clk = { + .halt_reg = 0x88008, + .clkr = { + .enable_reg = 0x88008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_clkref_clk = { + .halt_reg = 0x8800c, + .clkr = { + .enable_reg = 0x8800c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx1_usb2_clkref_clk = { + .halt_reg = 0x88014, + .clkr = { + .enable_reg = 0x88014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx1_usb2_clkref_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, .gds_hw_ctrl = 0x0, @@ -2716,6 +2786,11 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, + [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, + [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, + [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, + [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, + [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, }; static struct gdsc *gcc_msm8998_gdscs[] = { -- cgit v1.2.3 From a1697aba2721bebd5af2a041b9c251ce9bf7631e Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Tue, 11 Dec 2018 13:00:04 -0700 Subject: clk: qcom: Add missing msm8998 resets commit c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") missed two USB2 resets. Add them. Fixes: c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") Signed-off-by: Jeffrey Hugo Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 5f989eee43e4..f3c2ab4bf42a 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2827,6 +2827,8 @@ static const struct qcom_reset_map gcc_msm8998_resets[] = { [GCC_MMSS_BCR] = { 0xb000 }, [GCC_QDSS_BCR] = { 0xc000 }, [GCC_WCSS_BCR] = { 0x11000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, [GCC_BLSP1_BCR] = { 0x17000 }, [GCC_BLSP1_UART1_BCR] = { 0x1a000 }, [GCC_BLSP1_UART2_BCR] = { 0x1c000 }, -- cgit v1.2.3 From 12eced09cd301aa7b1868a67c50a651c2aacd363 Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Thu, 13 Dec 2018 15:43:40 -0700 Subject: clk: qcom: Leave mmss noc on for 8998 Similar to other qcom targets, gcc_mmss_noc_cfg_ahb_clk should not be disabled. Any mmss access depends on this clock, and its been observed that enabling mmssnoc_axi_rpm_clk with rpmcc results in an implicit access to mmss and will crash the system if gcc_mmss_noc_cfg_ahb_clk is disabled. Signed-off-by: Jeffrey Hugo Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index f3c2ab4bf42a..b0c4b3874120 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2027,6 +2027,12 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_noc_cfg_ahb_clk", .ops = &clk_branch2_ops, + /* + * Any access to mmss depends on this clock. + * Gating this clock has been shown to crash the system + * when mmssnoc_axi_rpm_clk is inited in rpmcc. + */ + .flags = CLK_IS_CRITICAL, }, }, }; -- cgit v1.2.3 From 0f1c6ca83fb483a5ea85fe239588a90bb29d519d Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Thu, 13 Dec 2018 10:09:09 -0700 Subject: clk: qcom: Drop unused 8998 clock gcc_lpass_trig_clk is not used downstream, therefore there is no reason to expect it to be needed for clients. Let's remove it because messing with the clock has been observed to cause Linux hangs when the qdss_clk is initialized by rpmcc. Signed-off-by: Jeffrey Hugo Reviewed-by: Marc Gonzalez Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'drivers/clk/qcom') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index b0c4b3874120..1b779396e04f 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2005,19 +2005,6 @@ static struct clk_branch gcc_hmss_trig_clk = { }, }; -static struct clk_branch gcc_lpass_trig_clk = { - .halt_reg = 0x4701c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4701c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_lpass_trig_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { .halt_reg = 0x9004, .halt_check = BRANCH_HALT, @@ -2716,7 +2703,6 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr, [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr, - [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr, [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr, [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr, -- cgit v1.2.3