From 32cae024f7186e60cbdeb5b594eb920036f38225 Mon Sep 17 00:00:00 2001 From: Abhishek Sahu Date: Wed, 13 Dec 2017 19:55:34 +0530 Subject: clk: qcom: ipq8074: fix missing GPLL0 divider width GPLL0 uses 4 bits post divider which should be specified in clock driver structure. Signed-off-by: Abhishek Sahu Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/qcom/gcc-ipq8074.c') diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index ed2d00f55378..99906f6a8264 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -84,6 +84,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", .parent_names = (const char *[]){ -- cgit v1.2.3