From 55213e1acec9218580c90d36034aa0370a51daab Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 30 Nov 2015 17:31:41 -0800 Subject: clk: qcom: Add gfx3d ping-pong PLL frequency switching The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2, MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624 MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To make switching frequencies faster, we ping-pong between MMPLL2 and MMPLL8 when we're switching between frequencies that aren't the maximum. Implement custom rcg clk ops for this type of frequency switching. Signed-off-by: Stephen Boyd --- drivers/clk/qcom/clk-rcg.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/qcom/clk-rcg.h') diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 4b1e94bdf29e..b904c335cda4 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -178,5 +178,6 @@ extern const struct clk_ops clk_edp_pixel_ops; extern const struct clk_ops clk_byte_ops; extern const struct clk_ops clk_byte2_ops; extern const struct clk_ops clk_pixel_ops; +extern const struct clk_ops clk_gfx3d_ops; #endif -- cgit v1.2.3