From 56fbeefe366e5920802f60f26b6b59b365c0569b Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Wed, 11 Mar 2020 16:41:15 +0300 Subject: CLK: HSDK: CGU: add support for 148.5MHz clock Add support for 148.5MHz clock for HDMI PLL Signed-off-by: Eugeniy Paltsev Link: https://lkml.kernel.org/r/20200311134115.13257-4-Eugeniy.Paltsev@synopsys.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-hsdk-pll.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/clk-hsdk-pll.c') diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c index 0ea7af57a5b1..b4f8852201cb 100644 --- a/drivers/clk/clk-hsdk-pll.c +++ b/drivers/clk/clk-hsdk-pll.c @@ -81,6 +81,7 @@ static const struct hsdk_pll_cfg asdt_pll_cfg[] = { static const struct hsdk_pll_cfg hdmi_pll_cfg[] = { { 27000000, 0, 0, 0, 0, 1 }, + { 148500000, 0, 21, 3, 0, 0 }, { 297000000, 0, 21, 2, 0, 0 }, { 540000000, 0, 19, 1, 0, 0 }, { 594000000, 0, 21, 1, 0, 0 }, -- cgit v1.2.3