From bcc5fd49a0fda5abc22057f65b318788ccb5d2ad Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 15 Sep 2014 18:15:53 +0200 Subject: clk: at91: add a driver for the h32mx clock Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix interconnect (h32mx) has a clock that can be setup at the half of the h64mx clock (which is mck). The h32mx clock can not exceed 90 MHz. Signed-off-by: Alexandre Belloni Acked-by: Boris Brezillon Signed-off-by: Nicolas Ferre --- drivers/clk/at91/Makefile | 1 + drivers/clk/at91/clk-h32mx.c | 123 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/at91/pmc.c | 6 +++ drivers/clk/at91/pmc.h | 5 ++ 4 files changed, 135 insertions(+) create mode 100644 drivers/clk/at91/clk-h32mx.c (limited to 'drivers/clk/at91') diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 4998aee59267..89a48a7bd5df 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -9,3 +9,4 @@ obj-y += clk-system.o clk-peripheral.o clk-programmable.o obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o +obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c new file mode 100644 index 000000000000..152dcb3f7b5f --- /dev/null +++ b/drivers/clk/at91/clk-h32mx.c @@ -0,0 +1,123 @@ +/* + * clk-h32mx.c + * + * Copyright (C) 2014 Atmel + * + * Alexandre Belloni + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pmc.h" + +#define H32MX_MAX_FREQ 90000000 + +struct clk_sama5d4_h32mx { + struct clk_hw hw; + struct at91_pmc *pmc; +}; + +#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw) + +static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw); + + if (pmc_read(h32mxclk->pmc, AT91_PMC_MCKR) & AT91_PMC_H32MXDIV) + return parent_rate / 2; + + if (parent_rate > H32MX_MAX_FREQ) + pr_warn("H32MX clock is too fast\n"); + return parent_rate; +} + +static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned long div; + + if (rate > *parent_rate) + return *parent_rate; + div = *parent_rate / 2; + if (rate < div) + return div; + + if (rate - div < *parent_rate - rate) + return div; + + return *parent_rate; +} + +static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw); + struct at91_pmc *pmc = h32mxclk->pmc; + u32 tmp; + + if (parent_rate != rate && (parent_rate / 2) != rate) + return -EINVAL; + + pmc_lock(pmc); + tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_H32MXDIV; + if ((parent_rate / 2) == rate) + tmp |= AT91_PMC_H32MXDIV; + pmc_write(pmc, AT91_PMC_MCKR, tmp); + pmc_unlock(pmc); + + return 0; +} + +static const struct clk_ops h32mx_ops = { + .recalc_rate = clk_sama5d4_h32mx_recalc_rate, + .round_rate = clk_sama5d4_h32mx_round_rate, + .set_rate = clk_sama5d4_h32mx_set_rate, +}; + +void __init of_sama5d4_clk_h32mx_setup(struct device_node *np, + struct at91_pmc *pmc) +{ + struct clk_sama5d4_h32mx *h32mxclk; + struct clk_init_data init; + const char *parent_name; + struct clk *clk; + + h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL); + if (!h32mxclk) + return; + + parent_name = of_clk_get_parent_name(np, 0); + + init.name = np->name; + init.ops = &h32mx_ops; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + init.flags = CLK_SET_RATE_GATE; + + h32mxclk->hw.init = &init; + h32mxclk->pmc = pmc; + + clk = clk_register(NULL, &h32mxclk->hw); + if (!clk) + return; + + of_clk_add_provider(np, of_clk_src_simple_get, clk); +} diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index 524196bb35a5..386999b4f8eb 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -336,6 +336,12 @@ static const struct of_device_id pmc_clk_ids[] __initconst = { .compatible = "atmel,at91sam9x5-clk-smd", .data = of_at91sam9x5_clk_smd_setup, }, +#endif +#if defined(CONFIG_HAVE_AT91_H32MX) + { + .compatible = "atmel,sama5d4-clk-h32mx", + .data = of_sama5d4_clk_h32mx_setup, + }, #endif { /*sentinel*/ } }; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 6c7625976113..52d2041fa3f6 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -120,4 +120,9 @@ extern void __init of_at91sam9x5_clk_smd_setup(struct device_node *np, struct at91_pmc *pmc); #endif +#if defined(CONFIG_HAVE_AT91_SMD) +extern void __init of_sama5d4_clk_h32mx_setup(struct device_node *np, + struct at91_pmc *pmc); +#endif + #endif /* __PMC_H_ */ -- cgit v1.2.3