From 555eae97358082be3a46572464829c27b96ed8f1 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Tue, 9 Apr 2013 16:46:26 +0800 Subject: clk: add PowerPC corenet clock driver support This adds the clock driver for Freescale PowerPC corenet series SoCs using common clock infrastructure. Signed-off-by: Tang Yuantian Signed-off-by: Li Yang Signed-off-by: Mike Turquette --- drivers/clk/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/Makefile') diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 137d3e730f86..3a26115bb0f9 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o +obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o -- cgit v1.2.3 From 7d1818fa6683daee6f6bf6f420ac850e5fe4e544 Mon Sep 17 00:00:00 2001 From: Daniel Tang Date: Fri, 31 May 2013 19:27:33 +1000 Subject: clk: Add TI-Nspire clock drivers This patch adds a basic clock driver for the TI-Nspire calculator series. Changes from v1: * Removed filename in header comment * Removed unnecessary #undef EXTRACT statement Signed-off-by: Daniel Tang Signed-off-by: Mike Turquette [mturquette@linaro.org: fixed $SUBJECT and changelog max width] --- drivers/clk/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/Makefile') diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 3a26115bb0f9..f51b52b6651a 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-composite.o obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o +obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o obj-$(CONFIG_ARCH_MXS) += mxs/ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ -- cgit v1.2.3 From 646572c77db7c42beb3d091915c8f97359100c47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Thu, 13 Jun 2013 16:59:40 +0200 Subject: clk: add support for Rockchip gate clocks This adds basic support for gate-clocks on Rockchip SoCs. There are 16 gates in each register and use the HIWORD_MASK mechanism for changing gate settings. The gate registers form a continuos block which makes the dt node structure a matter of taste, as either all 160 gates can be put into one gate clock spanning all registers or they can be divided into the 10 individual gates containing 16 clocks each. The code supports both approaches. Signed-off-by: Heiko Stuebner Signed-off-by: Mike Turquette --- drivers/clk/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/Makefile') diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f51b52b6651a..2e2e957ccfb7 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -25,6 +25,7 @@ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o -- cgit v1.2.3