From cefe6aac29ff608a244f8cc9ba6bcfe12ee9c1f3 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 24 Oct 2019 23:38:26 +0200 Subject: ACPI / PMIC: Add Cherry Trail Crystal Cove PMIC OpRegion driver We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal Cove Plus" PMIC and talks about Cherry Trail, so presuambly that one could be used to get register info for the regulators if we need to implement regulator support in the future. For now the sole purpose of this driver is to make intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a CHT Crystal Cove PMIC. Specifically this fixes the following MIPI PMIC sequence related errors on e.g. an Asus T100HA: [ 178.211801] intel_soc_pmic_exec_mipi_pmic_seq_element: No PMIC registered [ 178.211897] [drm:intel_dsi_dcs_init_backlight_funcs [i915]] *ERROR* mipi_exec_pmic failed, error: -6 Signed-off-by: Hans de Goede Reviewed-by: Andy Shevchenko Signed-off-by: Rafael J. Wysocki --- drivers/acpi/pmic/intel_pmic_chtcrc.c | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 drivers/acpi/pmic/intel_pmic_chtcrc.c (limited to 'drivers/acpi/pmic') diff --git a/drivers/acpi/pmic/intel_pmic_chtcrc.c b/drivers/acpi/pmic/intel_pmic_chtcrc.c new file mode 100644 index 000000000000..ebf8d3187df1 --- /dev/null +++ b/drivers/acpi/pmic/intel_pmic_chtcrc.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Cherry Trail Crystal Cove PMIC operation region driver + * + * Copyright (C) 2019 Hans de Goede + */ + +#include +#include +#include +#include +#include +#include "intel_pmic.h" + +/* + * We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel + * code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal + * Cove Plus" PMIC and talks about Cherry Trail, so presuambly that one + * could be used to get register info for the regulators if we need to + * implement regulator support in the future. + * + * For now the sole purpose of this driver is to make + * intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a + * CHT Crystal Cove PMIC. + */ +static struct intel_pmic_opregion_data intel_chtcrc_pmic_opregion_data = { + .pmic_i2c_address = 0x6e, +}; + +static int intel_chtcrc_pmic_opregion_probe(struct platform_device *pdev) +{ + struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent); + return intel_pmic_install_opregion_handler(&pdev->dev, + ACPI_HANDLE(pdev->dev.parent), pmic->regmap, + &intel_chtcrc_pmic_opregion_data); +} + +static struct platform_driver intel_chtcrc_pmic_opregion_driver = { + .probe = intel_chtcrc_pmic_opregion_probe, + .driver = { + .name = "cht_crystal_cove_pmic", + }, +}; +builtin_platform_driver(intel_chtcrc_pmic_opregion_driver); -- cgit v1.2.3