From 1068ed4547adf6123504d9623ebd1ffcdd616101 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Mon, 8 Jun 2020 16:19:49 +0200 Subject: x86/msr: Lift AMD family 0x15 power-specific MSRs ... into the global msr-index.h header because they're used in multiple compilation units. Sort the MSR list a bit. Update the msr-index.h copy in tools. No functional changes. Signed-off-by: Borislav Petkov Acked-by: Guenter Roeck Link: https://lkml.kernel.org/r/20200608164847.14232-1-bp@alien8.de --- arch/x86/events/amd/power.c | 4 ---- arch/x86/include/asm/msr-index.h | 5 ++++- 2 files changed, 4 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/events/amd/power.c b/arch/x86/events/amd/power.c index 43b09e9c93a2..16a2369c586e 100644 --- a/arch/x86/events/amd/power.c +++ b/arch/x86/events/amd/power.c @@ -13,10 +13,6 @@ #include #include "../perf_event.h" -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b -#define MSR_F15H_PTSC 0xc0010280 - /* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */ #define AMD_POWER_EVENT_MASK 0xFFULL diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index e8370e64a155..eb9537254920 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -418,15 +418,18 @@ #define MSR_AMD64_PATCH_LEVEL 0x0000008b #define MSR_AMD64_TSC_RATIO 0xc0000104 #define MSR_AMD64_NB_CFG 0xc001001f -#define MSR_AMD64_CPUID_FN_1 0xc0011004 #define MSR_AMD64_PATCH_LOADER 0xc0010020 #define MSR_AMD_PERF_CTL 0xc0010062 #define MSR_AMD_PERF_STATUS 0xc0010063 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 +#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a +#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 +#define MSR_F15H_PTSC 0xc0010280 #define MSR_AMD_PPIN_CTL 0xc00102f0 #define MSR_AMD_PPIN 0xc00102f1 +#define MSR_AMD64_CPUID_FN_1 0xc0011004 #define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_DC_CFG 0xc0011022 #define MSR_AMD64_BU_CFG2 0xc001102a -- cgit v1.2.3 From fbd5969d1ff2598143d6a6fbc9491a9e40ab9b82 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Thu, 4 Jun 2020 12:38:39 +0200 Subject: x86/cpufeatures: Mark two free bits in word 3 ... so that they get reused when needed. No functional changes. Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20200604104150.2056-1-bp@alien8.de --- arch/x86/include/asm/cpufeatures.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 02dabc9e77b0..c693ebf32a15 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -96,6 +96,7 @@ #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ +/* free ( 3*32+17) */ #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ @@ -107,6 +108,7 @@ #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ +/* free ( 3*32+29) */ #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ -- cgit v1.2.3 From 28b60197b573cd0b2d8f0ded56a5441c6147af14 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Thu, 4 Jun 2020 12:50:44 +0200 Subject: x86/asm: Unify __ASSEMBLY__ blocks Merge the two ifndef __ASSEMBLY__ blocks. No functional changes. Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20200604133204.7636-1-bp@alien8.de --- arch/x86/include/asm/asm.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h index 0f63585edf5f..5c15f95b1ba7 100644 --- a/arch/x86/include/asm/asm.h +++ b/arch/x86/include/asm/asm.h @@ -144,7 +144,7 @@ _ASM_PTR (entry); \ .popsection -#else +#else /* ! __ASSEMBLY__ */ # define _EXPAND_EXTABLE_HANDLE(x) #x # define _ASM_EXTABLE_HANDLE(from, to, handler) \ " .pushsection \"__ex_table\",\"a\"\n" \ @@ -164,9 +164,7 @@ _ASM_EXTABLE_HANDLE(from, to, ex_handler_fault) /* For C file, we already have NOKPROBE_SYMBOL macro */ -#endif -#ifndef __ASSEMBLY__ /* * This output constraint should be used for any inline asm which has a "call" * instruction. Otherwise the asm may be inserted before the frame pointer @@ -175,6 +173,6 @@ */ register unsigned long current_stack_pointer asm(_ASM_SP); #define ASM_CALL_CONSTRAINT "+r" (current_stack_pointer) -#endif +#endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_ASM_H */ -- cgit v1.2.3 From d5249bc7a1a8869da90ba668b331b0b3f8996924 Mon Sep 17 00:00:00 2001 From: Benjamin Thiel Date: Sat, 6 Jun 2020 14:26:29 +0200 Subject: x86/mm: Fix -Wmissing-prototypes warnings for arch/x86/mm/init.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix -Wmissing-prototypes warnings: arch/x86/mm/init.c:81:6: warning: no previous prototype for ‘x86_has_pat_wp’ [-Wmissing-prototypes] bool x86_has_pat_wp(void) arch/x86/mm/init.c:86:22: warning: no previous prototype for ‘pgprot2cachemode’ [-Wmissing-prototypes] enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) by including the respective header containing prototypes. Also fix: arch/x86/mm/init.c:893:13: warning: no previous prototype for ‘mem_encrypt_free_decrypted_mem’ [-Wmissing-prototypes] void __weak mem_encrypt_free_decrypted_mem(void) { } by making it static inline for the !CONFIG_AMD_MEM_ENCRYPT case. This warning happens when CONFIG_AMD_MEM_ENCRYPT is not enabled (defconfig for example): ./arch/x86/include/asm/mem_encrypt.h:80:27: warning: inline function ‘mem_encrypt_free_decrypted_mem’ declared weak [-Wattributes] static inline void __weak mem_encrypt_free_decrypted_mem(void) { } ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ It's ok to convert to static inline because the function is used only in x86. Is not shared with other architectures so drop the __weak too. [ bp: Massage and adjust __weak comments while at it. ] Signed-off-by: Benjamin Thiel Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20200606122629.2720-1-b.thiel@posteo.de --- arch/x86/include/asm/mem_encrypt.h | 5 ++++- arch/x86/mm/init.c | 3 +-- arch/x86/mm/mem_encrypt.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h index 848ce43b9040..5049f6c22683 100644 --- a/arch/x86/include/asm/mem_encrypt.h +++ b/arch/x86/include/asm/mem_encrypt.h @@ -43,9 +43,10 @@ void __init sme_enable(struct boot_params *bp); int __init early_set_memory_decrypted(unsigned long vaddr, unsigned long size); int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size); +void __init mem_encrypt_free_decrypted_mem(void); + /* Architecture __weak replacement functions */ void __init mem_encrypt_init(void); -void __init mem_encrypt_free_decrypted_mem(void); bool sme_active(void); bool sev_active(void); @@ -77,6 +78,8 @@ early_set_memory_decrypted(unsigned long vaddr, unsigned long size) { return 0; static inline int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size) { return 0; } +static inline void mem_encrypt_free_decrypted_mem(void) { } + #define __bss_decrypted #endif /* CONFIG_AMD_MEM_ENCRYPT */ diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 001dd7dc829f..c7a47603537f 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -25,6 +25,7 @@ #include #include #include +#include /* * We need to define the tracepoints somewhere, and tlb.c @@ -912,8 +913,6 @@ void free_kernel_image_pages(const char *what, void *begin, void *end) set_memory_np_noalias(begin_ul, len_pages); } -void __weak mem_encrypt_free_decrypted_mem(void) { } - void __ref free_initmem(void) { e820__reallocate_tables(); diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 4a781cf99e92..9f1177edc2e7 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -376,7 +376,6 @@ bool force_dma_unencrypted(struct device *dev) return false; } -/* Architecture __weak replacement functions */ void __init mem_encrypt_free_decrypted_mem(void) { unsigned long vaddr, vaddr_end, npages; @@ -401,6 +400,7 @@ void __init mem_encrypt_free_decrypted_mem(void) free_init_pages("unused decrypted", vaddr, vaddr_end); } +/* Architecture __weak replacement functions */ void __init mem_encrypt_init(void) { if (!sme_me_mask) -- cgit v1.2.3 From 56ce93700eb630a8d894f5a578f166888ae8cba6 Mon Sep 17 00:00:00 2001 From: Benjamin Thiel Date: Sat, 6 Jun 2020 14:37:43 +0200 Subject: x86/mm/32: Fix -Wmissing prototypes warnings for init.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix: arch/x86/mm/init.c:503:21: warning: no previous prototype for ‘init_memory_mapping’ [-Wmissing-prototypes] unsigned long __ref init_memory_mapping(unsigned long start, arch/x86/mm/init.c:745:13: warning: no previous prototype for ‘poking_init’ [-Wmissing-prototypes] void __init poking_init(void) Lift init_memory_mapping() and poking_init() out of the ifdef CONFIG_X86_64 to make the functions visible on 32-bit too. Signed-off-by: Benjamin Thiel Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20200606123743.3277-1-b.thiel@posteo.de --- arch/x86/include/asm/pgtable.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index 76aa21e8128d..b836138ce852 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -999,15 +999,12 @@ extern int direct_gbpages; void init_mem_mapping(void); void early_alloc_pgt_buf(void); extern void memblock_find_dma_reserve(void); - - -#ifdef CONFIG_X86_64 -extern pgd_t trampoline_pgd_entry; - void __init poking_init(void); - unsigned long init_memory_mapping(unsigned long start, unsigned long end, pgprot_t prot); + +#ifdef CONFIG_X86_64 +extern pgd_t trampoline_pgd_entry; #endif /* local pte updates need not use xchg for locking */ -- cgit v1.2.3 From 286d966b21587b6303081b902f5c5e30b691baf5 Mon Sep 17 00:00:00 2001 From: Jason Andryuk Date: Fri, 19 Jun 2020 16:51:02 -0400 Subject: x86/idt: Make idt_descr static Commit 3e77abda65b1 ("x86/idt: Consolidate idt functionality") states that idt_descr could be made static, but it did not actually make the change. Make it static now. Fixes: 3e77abda65b1 ("x86/idt: Consolidate idt functionality") Signed-off-by: Jason Andryuk Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20200619205103.30873-1-jandryuk@gmail.com --- arch/x86/kernel/idt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index 0db21206f2f3..7ecf9babf0cb 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -160,7 +160,7 @@ static const __initconst struct idt_data apic_idts[] = { /* Must be page-aligned because the real IDT is used in the cpu entry area */ static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss; -struct desc_ptr idt_descr __ro_after_init = { +static struct desc_ptr idt_descr __ro_after_init = { .size = IDT_TABLE_SIZE - 1, .address = (unsigned long) idt_table, }; -- cgit v1.2.3 From 99e40204e014e06644072c39001a269d9689e0d1 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Sun, 21 Jun 2020 12:41:53 +0200 Subject: x86/msr: Move the F15h MSRs where they belong 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs") moved the three F15h power MSRs to the architectural list but that was wrong as they belong in the family 0x15 list. That also caused: In file included from trace/beauty/tracepoints/x86_msr.c:10: perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: initialized field overwritten [-Werror=override-init] 292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC", | ^~~~~~~~~~~ perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near initialization for 'x86_AMD_V_KVM_MSRs[640]') due to MSR_F15H_PTSC ending up being defined twice. Move them where they belong and drop the duplicate. Also, drop the respective tools/ changes of the msr-index.h copy the above commit added because perf tool developers prefer to go through those changes themselves in order to figure out whether changes to the kernel headers would need additional handling in perf. Fixes: 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs") Reported-by: Stephen Rothwell Signed-off-by: Borislav Petkov Acked-by: Arnaldo Carvalho de Melo Link: https://lkml.kernel.org/r/20200621163323.14e8533f@canb.auug.org.au --- arch/x86/include/asm/msr-index.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index eb9537254920..63ed8fe35738 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -422,11 +422,8 @@ #define MSR_AMD_PERF_CTL 0xc0010062 #define MSR_AMD_PERF_STATUS 0xc0010063 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 -#define MSR_F15H_PTSC 0xc0010280 #define MSR_AMD_PPIN_CTL 0xc00102f0 #define MSR_AMD_PPIN 0xc00102f1 #define MSR_AMD64_CPUID_FN_1 0xc0011004 @@ -469,6 +466,8 @@ #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 /* Fam 15h MSRs */ +#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a +#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b #define MSR_F15H_PERF_CTL 0xc0010200 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) -- cgit v1.2.3 From 0a787b28b7a375ad9d5c77bc3922ae1a8305239e Mon Sep 17 00:00:00 2001 From: Arvind Sankar Date: Thu, 23 Jul 2020 19:15:42 -0400 Subject: x86/mm: Drop unused MAX_PHYSADDR_BITS The macro is not used anywhere, and has an incorrect value (going by the comment) on x86_64 since commit c898faf91b3e ("x86: 46 bit physical address support on 64 bits") To avoid confusion, just remove the definition. Signed-off-by: Arvind Sankar Signed-off-by: Thomas Gleixner Link: https://lkml.kernel.org/r/20200723231544.17274-2-nivedita@alum.mit.edu --- arch/x86/include/asm/sparsemem.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/sparsemem.h b/arch/x86/include/asm/sparsemem.h index 199218719a86..6bfc878f6771 100644 --- a/arch/x86/include/asm/sparsemem.h +++ b/arch/x86/include/asm/sparsemem.h @@ -10,24 +10,20 @@ * field of the struct page * * SECTION_SIZE_BITS 2^n: size of each section - * MAX_PHYSADDR_BITS 2^n: max size of physical address space - * MAX_PHYSMEM_BITS 2^n: how much memory we can have in that space + * MAX_PHYSMEM_BITS 2^n: max size of physical address space * */ #ifdef CONFIG_X86_32 # ifdef CONFIG_X86_PAE # define SECTION_SIZE_BITS 29 -# define MAX_PHYSADDR_BITS 36 # define MAX_PHYSMEM_BITS 36 # else # define SECTION_SIZE_BITS 26 -# define MAX_PHYSADDR_BITS 32 # define MAX_PHYSMEM_BITS 32 # endif #else /* CONFIG_X86_32 */ # define SECTION_SIZE_BITS 27 /* matt - 128 is convenient right now */ -# define MAX_PHYSADDR_BITS (pgtable_l5_enabled() ? 52 : 44) # define MAX_PHYSMEM_BITS (pgtable_l5_enabled() ? 52 : 46) #endif -- cgit v1.2.3 From 8cd591aeb1d650f79a49d8704c35a78bf18f5de9 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Fri, 24 Jul 2020 13:44:16 +0200 Subject: x86/ioapic: Remove unused "IOAPIC_AUTO" define Last use was removed more than 5 years ago, in: 5ad274d41c1b: ("x86/irq: Remove unused old IOAPIC irqdomain interfaces") Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20200724114418.629021-2-mingo@kernel.org --- arch/x86/include/asm/io_apic.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h index fd20a2334885..a1a26f6d3aa4 100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -99,7 +99,6 @@ struct IR_IO_APIC_route_entry { struct irq_alloc_info; struct ioapic_domain_cfg; -#define IOAPIC_AUTO -1 #define IOAPIC_EDGE 0 #define IOAPIC_LEVEL 1 -- cgit v1.2.3 From 161449bad5053d66f2310744ba8498158ab12c89 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Fri, 24 Jul 2020 13:44:17 +0200 Subject: x86/tsc: Remove unused "US_SCALE" and "NS_SCALE" leftover macros Last use of them was removed 13 years ago, when the code was converted to use CYC2NS_SCALE_FACTOR: 53d517cdbaac: ("x86: scale cyc_2_nsec according to CPU frequency") The current TSC code uses the 'struct cyc2ns_data' scaling abstraction, the old fixed scaling approach is long gone. This cleanup also removes the 'arbitralrily' typo from the comment, so win-win. ;-) Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20200724114418.629021-3-mingo@kernel.org --- arch/x86/include/asm/tsc.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 8a0c25c6bf09..b7b2624fba86 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -7,9 +7,6 @@ #include -#define NS_SCALE 10 /* 2^10, carefully chosen */ -#define US_SCALE 32 /* 2^32, arbitralrily chosen */ - /* * Standard way to access the cycle counter. */ -- cgit v1.2.3 From 4b8e0328e56e177663645a96ea4c5c0401ecd78f Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Fri, 24 Jul 2020 13:44:18 +0200 Subject: x86/mm: Remove the unused mk_kernel_pgd() #define AFAICS the last uses of directly 'making' kernel PGDs was removed 7 years ago: 8b78c21d72d9: ("x86, 64bit, mm: hibernate use generic mapping_init") Where the explicit PGD walking loop was replaced with kernel_ident_mapping_init() calls. This was then (unnecessarily) carried over through the 5-level paging conversion. Also clean up the 'level' comments a bit, to convey the original, meanwhile somewhat bit-rotten notion, that these are empty comment blocks with no methods to handle any of the levels except the PTE level. Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20200724114418.629021-4-mingo@kernel.org --- arch/x86/include/asm/pgtable_64.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index 1b68d24dc6a0..d2af8c48ba50 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h @@ -175,16 +175,13 @@ extern void sync_global_pgds(unsigned long start, unsigned long end); * and a page entry and page directory to the page they refer to. */ -/* - * Level 4 access. - */ -#define mk_kernel_pgd(address) __pgd((address) | _KERNPG_TABLE) +/* PGD - Level 4 access */ -/* PUD - Level3 access */ +/* PUD - Level 3 access */ -/* PMD - Level 2 access */ +/* PMD - Level 2 access */ -/* PTE - Level 1 access. */ +/* PTE - Level 1 access */ /* * Encode and de-code a swap entry -- cgit v1.2.3 From ddeddd0811ffeb43937aca2d5479f323234f17cd Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 25 Jul 2020 17:41:22 -0700 Subject: x86: bootparam.h: Delete duplicated word Delete the repeated word "for". Signed-off-by: Randy Dunlap Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20200726004124.20618-2-rdunlap@infradead.org --- arch/x86/include/uapi/asm/bootparam.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h index 8669c6bdbb84..600a141c8805 100644 --- a/arch/x86/include/uapi/asm/bootparam.h +++ b/arch/x86/include/uapi/asm/bootparam.h @@ -255,7 +255,7 @@ struct boot_params { * currently supportd through this PV boot path. * @X86_SUBARCH_INTEL_MID: Used for Intel MID (Mobile Internet Device) platform * systems which do not have the PCI legacy interfaces. - * @X86_SUBARCH_CE4100: Used for Intel CE media processor (CE4100) SoC for + * @X86_SUBARCH_CE4100: Used for Intel CE media processor (CE4100) SoC * for settop boxes and media devices, the use of a subarch for CE4100 * is more of a hack... */ -- cgit v1.2.3 From 8b9fd48eb73ec854c2877735e96c91127cc78a1d Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 25 Jul 2020 17:41:23 -0700 Subject: x86: cmpxchg_32.h: Delete duplicated word Delete the repeated word "you". Signed-off-by: Randy Dunlap Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20200726004124.20618-3-rdunlap@infradead.org --- arch/x86/include/asm/cmpxchg_32.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h index 1a2eafca7038..0a7fe0321613 100644 --- a/arch/x86/include/asm/cmpxchg_32.h +++ b/arch/x86/include/asm/cmpxchg_32.h @@ -3,7 +3,7 @@ #define _ASM_X86_CMPXCHG_32_H /* - * Note: if you use set64_bit(), __cmpxchg64(), or their variants, you + * Note: if you use set64_bit(), __cmpxchg64(), or their variants, * you need to test for the feature in boot_cpu_data. */ -- cgit v1.2.3 From de0038bfaf53af0e8bc4961b7aacdcb79f43bf08 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 25 Jul 2020 17:41:24 -0700 Subject: x86: uv: uv_hub.h: Delete duplicated word Delete the repeated word "the". [ mingo: While at it, also capitalize CPU properly. ] Signed-off-by: Randy Dunlap Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20200726004124.20618-4-rdunlap@infradead.org --- arch/x86/include/asm/uv/uv_hub.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h index 60ca0afdeaf9..5738c36be674 100644 --- a/arch/x86/include/asm/uv/uv_hub.h +++ b/arch/x86/include/asm/uv/uv_hub.h @@ -682,7 +682,7 @@ static inline int uv_node_to_blade_id(int nid) return nid; } -/* Convert a cpu number to the the UV blade number */ +/* Convert a CPU number to the UV blade number */ static inline int uv_cpu_to_blade_id(int cpu) { return uv_node_to_blade_id(cpu_to_node(cpu)); -- cgit v1.2.3 From 90fc73928fec2f62bbee1476781754c7392a7b61 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 21 Jul 2020 11:02:17 +0100 Subject: x86/ioperm: Initialize pointer bitmap with NULL rather than 0 The pointer bitmap is being initialized with a plain integer 0, fix this by initializing it with a NULL instead. Cleans up sparse warning: arch/x86/xen/enlighten_pv.c:876:27: warning: Using plain integer as NULL pointer Signed-off-by: Colin Ian King Signed-off-by: Ingo Molnar Reviewed-by: Juergen Gross Link: https://lore.kernel.org/r/20200721100217.407975-1-colin.king@canonical.com --- arch/x86/xen/enlighten_pv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index c46b9f2e732f..2aab43a13a8c 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -873,7 +873,7 @@ static void xen_load_sp0(unsigned long sp0) static void xen_invalidate_io_bitmap(void) { struct physdev_set_iobitmap iobitmap = { - .bitmap = 0, + .bitmap = NULL, .nr_ports = 0, }; -- cgit v1.2.3