From 97f9f9763a7a431e04f0ffd4e62d0d288a59f908 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 15 Jun 2018 13:08:34 +0200 Subject: MIPS: Octeon: refactor swiotlb code Share a common set of swiotlb operations, and to instead branch out in __phys_to_dma/__dma_to_phys for the PCI vs non-PCI case. Also use const structures for the PCI methods so that attackers can't use them as exploit vectors. Signed-off-by: Christoph Hellwig Patchwork: https://patchwork.linux-mips.org/patch/19532/ Signed-off-by: Paul Burton Cc: Florian Fainelli Cc: David Daney Cc: Kevin Cernekee Cc: Jiaxun Yang Cc: Tom Bogendoerfer Cc: Huacai Chen Cc: iommu@lists.linux-foundation.org Cc: linux-mips@linux-mips.org --- arch/mips/pci/pci-octeon.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 3e92a06fa772..a20697df3539 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -166,8 +166,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev) pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); } - dev->dev.dma_ops = octeon_pci_dma_map_ops; - return 0; } -- cgit v1.2.3 From a330a9c59b45e53dee7985237340f6480a1ea08f Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 15 Jun 2018 13:08:40 +0200 Subject: MIPS: Octeon: move swiotlb declarations out of dma-coherence.h No need to pull them into a global header. Signed-off-by: Christoph Hellwig Patchwork: https://patchwork.linux-mips.org/patch/19538/ Signed-off-by: Paul Burton Cc: Florian Fainelli Cc: David Daney Cc: Kevin Cernekee Cc: Jiaxun Yang Cc: Tom Bogendoerfer Cc: Huacai Chen Cc: iommu@lists.linux-foundation.org Cc: linux-mips@linux-mips.org --- arch/mips/pci/pci-octeon.c | 2 -- arch/mips/pci/pcie-octeon.c | 2 -- 2 files changed, 4 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index a20697df3539..5017d5843c5a 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -21,8 +21,6 @@ #include #include -#include - #define USE_OCTEON_INTERNAL_ARBITER /* diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index 87ba86bd8696..9cc5905860ef 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -94,8 +94,6 @@ union cvmx_pcie_address { static int cvmx_pcie_rc_initialize(int pcie_port); -#include - /** * Return the Core virtual base address for PCIe IO access. IOs are * read/written as an offset from this address. -- cgit v1.2.3 From 54aed4dd35269ef15eb1569517f34fb3961d4d34 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 15 Jun 2018 13:08:44 +0200 Subject: MIPS: IP27: use dma_direct_ops IP27 is coherent and has a reasonably direct mapping, just with a little per-bus offset added into the dma address. Signed-off-by: Christoph Hellwig Patchwork: https://patchwork.linux-mips.org/patch/19542/ Signed-off-by: Paul Burton Cc: Florian Fainelli Cc: David Daney Cc: Kevin Cernekee Cc: Jiaxun Yang Cc: Tom Bogendoerfer Cc: Huacai Chen Cc: iommu@lists.linux-foundation.org Cc: linux-mips@linux-mips.org --- arch/mips/pci/pci-ip27.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 0f09eafa5e3a..65b48d41a229 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -182,6 +183,19 @@ int pcibios_plat_dev_init(struct pci_dev *dev) return 0; } +dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus); + + return bc->baddr + paddr; +} + +phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr) +{ + return dma_addr & ~(0xffUL << 56); +} + /* * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses * to find the slot number in sense of the bridge device register. -- cgit v1.2.3 From d1f2564a5639bb54493eaa313aef612aee47ba7c Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 15 Jun 2018 13:08:49 +0200 Subject: MIPS: ath25: use generic dma noncoherent ops Provide phys_to_dma/dma_to_phys helpers only if PCI support is enabled, everything else is generic. Signed-off-by: Christoph Hellwig Patchwork: https://patchwork.linux-mips.org/patch/19547/ Signed-off-by: Paul Burton Cc: Florian Fainelli Cc: David Daney Cc: Kevin Cernekee Cc: Jiaxun Yang Cc: Tom Bogendoerfer Cc: Huacai Chen Cc: iommu@lists.linux-foundation.org Cc: linux-mips@linux-mips.org --- arch/mips/pci/pci-ar2315.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/pci-ar2315.c b/arch/mips/pci/pci-ar2315.c index b4fa6413c4e5..c539d0d2b0cf 100644 --- a/arch/mips/pci/pci-ar2315.c +++ b/arch/mips/pci/pci-ar2315.c @@ -149,6 +149,13 @@ #define AR2315_PCI_HOST_SLOT 3 #define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS) +/* + * We need some arbitrary non-zero value to be programmed to the BAR1 register + * of PCI host controller to enable DMA. The same value should be used as the + * offset to calculate the physical address of DMA buffer for PCI devices. + */ +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000 + /* ??? access BAR */ #define AR2315_PCI_HOST_MBAR0 0x10000000 /* RAM access BAR */ @@ -167,6 +174,23 @@ struct ar2315_pci_ctrl { struct resource io_res; }; +static inline dma_addr_t ar2315_dev_offset(struct device *dev) +{ + if (dev && dev_is_pci(dev)) + return AR2315_PCI_HOST_SDRAM_BASEADDR; + return 0; +} + +dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr) +{ + return paddr + ar2315_dev_offset(dev); +} + +phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr) +{ + return dma_addr - ar2315_dev_offset(dev); +} + static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus) { struct pci_controller *hose = bus->sysdata; -- cgit v1.2.3 From 8fd2d6ea66272f849943269c7ea771ce85fd8fb1 Mon Sep 17 00:00:00 2001 From: Joshua Kinard Date: Tue, 17 Oct 2017 14:26:12 -0400 Subject: MIPS: Use !pci_is_root_bus(bus) in ops-bridge.c This is a manual cherrypick of commit c7ddc3d137b7 from Alastair Bridgewater's IP35 tree that replaces two cases of "if (bus->number > 0)" with a more correct "if (!pci_is_root_bus(bus))" in arch/mips/pci/ops-bridge.c. Cc: linux-mips@linux-mips.org Cc: Alastair Bridgewater Suggested-by: Alastair Bridgewater Signed-off-by: Joshua Kinard Patchwork: https://patchwork.linux-mips.org/patch/17501/ Signed-off-by: Paul Burton Cc: Linux/MIPS --- arch/mips/pci/ops-bridge.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c index 57e1463fcd02..a1d2c4ae0d1b 100644 --- a/arch/mips/pci/ops-bridge.c +++ b/arch/mips/pci/ops-bridge.c @@ -167,7 +167,7 @@ oh_my_gawd: static int pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) { - if (bus->number > 0) + if (!pci_is_root_bus(bus)) return pci_conf1_read_config(bus, devfn, where, size, value); return pci_conf0_read_config(bus, devfn, where, size, value); @@ -310,7 +310,7 @@ oh_my_gawd: static int pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { - if (bus->number > 0) + if (!pci_is_root_bus(bus)) return pci_conf1_write_config(bus, devfn, where, size, value); return pci_conf0_write_config(bus, devfn, where, size, value); -- cgit v1.2.3 From ff404a936a958a45e3969730e065ea2886acc5e8 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Thu, 1 Jan 2015 16:32:06 +0100 Subject: arch: mips: pci: pci-ip27.c: Remove unused function Remove the function pci_enable_swapping() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Patchwork: https://patchwork.linux-mips.org/patch/8867/ Signed-off-by: Paul Burton Cc: John Crispin Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org --- arch/mips/pci/pci-ip27.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 65b48d41a229..c94a66070a60 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -214,17 +214,6 @@ static inline void pci_disable_swapping(struct pci_dev *dev) bridge->b_widget.w_tflush; /* Flush */ } -static inline void pci_enable_swapping(struct pci_dev *dev) -{ - struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); - bridge_t *bridge = bc->base; - int slot = PCI_SLOT(dev->devfn); - - /* Turn on byte swapping */ - bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; - bridge->b_widget.w_tflush; /* Flush */ -} - static void pci_fixup_ioc3(struct pci_dev *d) { pci_disable_swapping(d); -- cgit v1.2.3 From 769f4372b2887b7c758f67f4fae82bd5b8555b59 Mon Sep 17 00:00:00 2001 From: "Steven J. Hill" Date: Tue, 3 Jul 2018 16:44:21 -0500 Subject: MIPS: Octeon: Unify QLM data types in CIU header. Data types 'cvmx_ciu_qlm0' and 'cvmx_ciu_qlm1' are identical in their usage and structure. Combine them and update the PCIe code. Signed-off-by: Steven J. Hill Signed-off-by: Paul Burton Patchwork: https://patchwork.linux-mips.org/patch/19708/ Cc: linux-mips@linux-mips.org Cc: Chandrakala Chavva --- arch/mips/pci/pcie-octeon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index 9cc5905860ef..d919a0d813a1 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -1237,14 +1237,14 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port) /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) { if (pcie_port) { - union cvmx_ciu_qlm1 ciu_qlm; + union cvmx_ciu_qlm ciu_qlm; ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1); ciu_qlm.s.txbypass = 1; ciu_qlm.s.txdeemph = 5; ciu_qlm.s.txmargin = 0x17; cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64); } else { - union cvmx_ciu_qlm0 ciu_qlm; + union cvmx_ciu_qlm ciu_qlm; ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0); ciu_qlm.s.txbypass = 1; ciu_qlm.s.txdeemph = 5; -- cgit v1.2.3 From 0316b05311e777f8044c72a88b966ebae7c7a39f Mon Sep 17 00:00:00 2001 From: Mathias Kresin Date: Fri, 20 Jul 2018 13:58:25 +0200 Subject: MIPS: ath79: get PCIe controller out of reset The ar724x pci driver expects the PCIe controller to be brought out of reset by the bootloader. At least the AVM Fritz 300E bootloader doesn't take care of releasing the different PCIe controller related resets which causes an endless hang as soon as either the PCIE Reset register (0x180f0018) or the PCI Application Control register (0x180f0000) is read from. Do the full "PCIE Root Complex Initialization Sequence" if the PCIe host controller is still in reset during probing. The QCA u-boot sleeps 10ms after the PCIE Application Control bit is set to ready. It has been shown that 10ms might not be enough time if PCIe should be used right after setting the bit. During my tests it took up to 20ms till the link was up. Giving the link up to 100ms should work for all cases. Signed-off-by: Mathias Kresin Signed-off-by: John Crispin Signed-off-by: Paul Burton Patchwork: https://patchwork.linux-mips.org/patch/19916/ Cc: James Hogan Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/mips/pci') diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c index 1e23c8d587bd..64b58cc48a91 100644 --- a/arch/mips/pci/pci-ar724x.c +++ b/arch/mips/pci/pci-ar724x.c @@ -12,14 +12,18 @@ #include #include #include +#include #include #include #include +#define AR724X_PCI_REG_APP 0x00 #define AR724X_PCI_REG_RESET 0x18 #define AR724X_PCI_REG_INT_STATUS 0x4c #define AR724X_PCI_REG_INT_MASK 0x50 +#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) + #define AR724X_PCI_RESET_LINK_UP BIT(0) #define AR724X_PCI_INT_DEV0 BIT(14) @@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc, apc); } +static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc) +{ + u32 ppl, app; + int wait = 0; + + /* deassert PCIe host controller and PCIe PHY reset */ + ath79_device_reset_clear(AR724X_RESET_PCIE); + ath79_device_reset_clear(AR724X_RESET_PCIE_PHY); + + /* remove the reset of the PCIE PLL */ + ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); + ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; + ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); + + /* deassert bypass for the PCIE PLL */ + ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); + ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; + ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); + + /* set PCIE Application Control to ready */ + app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); + app |= AR724X_PCI_APP_LTSSM_ENABLE; + __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP); + + /* wait up to 100ms for PHY link up */ + do { + mdelay(10); + wait++; + } while (wait < 10 && !ar724x_pci_check_link(apc)); +} + static int ar724x_pci_probe(struct platform_device *pdev) { struct ar724x_pci_controller *apc; @@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platform_device *pdev) apc->pci_controller.io_resource = &apc->io_res; apc->pci_controller.mem_resource = &apc->mem_res; + /* + * Do the full PCIE Root Complex Initialization Sequence if the PCIe + * host controller is in reset. + */ + if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE) + ar724x_pci_hw_init(apc); + apc->link_up = ar724x_pci_check_link(apc); if (!apc->link_up) dev_warn(&pdev->dev, "PCIe link is down\n"); -- cgit v1.2.3