From 4ba66a9760722ccbb691b8f7116cad2f791cca7b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 7 Mar 2018 22:23:24 +0100 Subject: arch: remove blackfin port The Analog Devices Blackfin port was added in 2007 and was rather active for a while, but all work on it has come to a standstill over time, as Analog have changed their product line-up. Aaron Wu confirmed that the architecture port is no longer relevant, and multiple people suggested removing blackfin independently because of some of its oddities like a non-working SMP port, and the amount of duplication between the chip variants, which cause extra work when doing cross-architecture changes. Link: https://docs.blackfin.uclinux.org/ Acked-by: Aaron Wu Acked-by: Bryan Wu Cc: Steven Miao Cc: Mike Frysinger Signed-off-by: Arnd Bergmann --- arch/blackfin/mach-common/Makefile | 17 - arch/blackfin/mach-common/arch_checks.c | 66 -- arch/blackfin/mach-common/cache-c.c | 85 -- arch/blackfin/mach-common/cache.S | 124 --- arch/blackfin/mach-common/clock.h | 28 - arch/blackfin/mach-common/clocks-init.c | 121 -- arch/blackfin/mach-common/dpmc.c | 164 --- arch/blackfin/mach-common/dpmc_modes.S | 320 ------ arch/blackfin/mach-common/entry.S | 1711 ----------------------------- arch/blackfin/mach-common/head.S | 229 ---- arch/blackfin/mach-common/interrupt.S | 326 ------ arch/blackfin/mach-common/ints-priority.c | 1366 ----------------------- arch/blackfin/mach-common/pm.c | 301 ----- arch/blackfin/mach-common/scb-init.c | 52 - arch/blackfin/mach-common/smp.c | 432 -------- 15 files changed, 5342 deletions(-) delete mode 100644 arch/blackfin/mach-common/Makefile delete mode 100644 arch/blackfin/mach-common/arch_checks.c delete mode 100644 arch/blackfin/mach-common/cache-c.c delete mode 100644 arch/blackfin/mach-common/cache.S delete mode 100644 arch/blackfin/mach-common/clock.h delete mode 100644 arch/blackfin/mach-common/clocks-init.c delete mode 100644 arch/blackfin/mach-common/dpmc.c delete mode 100644 arch/blackfin/mach-common/dpmc_modes.S delete mode 100644 arch/blackfin/mach-common/entry.S delete mode 100644 arch/blackfin/mach-common/head.S delete mode 100644 arch/blackfin/mach-common/interrupt.S delete mode 100644 arch/blackfin/mach-common/ints-priority.c delete mode 100644 arch/blackfin/mach-common/pm.c delete mode 100644 arch/blackfin/mach-common/scb-init.c delete mode 100644 arch/blackfin/mach-common/smp.c (limited to 'arch/blackfin/mach-common') diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile deleted file mode 100644 index fcef1c8e117f..000000000000 --- a/arch/blackfin/mach-common/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/mach-common/Makefile -# - -obj-y := \ - cache.o cache-c.o entry.o head.o \ - interrupt.o arch_checks.o ints-priority.o - -obj-$(CONFIG_PM) += pm.o -ifneq ($(CONFIG_BF60x),y) -obj-$(CONFIG_PM) += dpmc_modes.o -endif -obj-$(CONFIG_SCB_PRIORITY) += scb-init.o -obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o -obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c deleted file mode 100644 index d8643fdd0fcf..000000000000 --- a/arch/blackfin/mach-common/arch_checks.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Do some checking to make sure things are OK - * - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -#ifdef CONFIG_BFIN_KERNEL_CLOCK - -# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ) -# error "VCO selected is more than maximum value. Please change the VCO multipler" -# endif - -# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ) -# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" -# endif - -# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ) -# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" -# endif - -# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ) -# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK" -# endif - -# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) -# error "Please select sclk less than cclk" -# endif - -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ - -#if CONFIG_BOOT_LOAD < FIXED_CODE_END -# error "The kernel load address must be after the fixed code section" -#endif - -#if (CONFIG_BOOT_LOAD & 0x3) -# error "The kernel load address must be 4 byte aligned" -#endif - -/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */ -#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000 -# error "The kernel load address is too high; keep it below 10meg for safety" -#endif - -#if ANOMALY_05000263 && defined(CONFIG_MPU) -# error the MPU will not function safely while Anomaly 05000263 applies -#endif - -#if ANOMALY_05000448 -# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. -#endif - -/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ -#if ANOMALY_05000220 && \ - (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)) -# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory" -#endif - -#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1) -# error You need IFLUSH in L1 inst while Anomaly 05000491 applies -#endif diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c deleted file mode 100644 index f4adedc92895..000000000000 --- a/arch/blackfin/mach-common/cache-c.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Blackfin cache control code (simpler control-style functions) - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -/* Invalidate the Entire Data cache by - * clearing DMC[1:0] bits - */ -void blackfin_invalidate_entire_dcache(void) -{ - u32 dmem = bfin_read_DMEM_CONTROL(); - bfin_write_DMEM_CONTROL(dmem & ~0xc); - SSYNC(); - bfin_write_DMEM_CONTROL(dmem); - SSYNC(); -} - -/* Invalidate the Entire Instruction cache by - * clearing IMC bit - */ -void blackfin_invalidate_entire_icache(void) -{ - u32 imem = bfin_read_IMEM_CONTROL(); - bfin_write_IMEM_CONTROL(imem & ~0x4); - SSYNC(); - bfin_write_IMEM_CONTROL(imem); - SSYNC(); -} - -#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE) - -static void -bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr, - unsigned long cplb_data, unsigned long mem_control, - unsigned long mem_mask) -{ - int i; -#ifdef CONFIG_L1_PARITY_CHECK - u32 ctrl; - - if (cplb_addr == DCPLB_ADDR0) { - ctrl = bfin_read32(mem_control) | (1 << RDCHK); - CSYNC(); - bfin_write32(mem_control, ctrl); - SSYNC(); - } -#endif - - for (i = 0; i < MAX_CPLBS; i++) { - bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr); - bfin_write32(cplb_data + i * 4, cplb_tbl[i].data); - } - - _enable_cplb(mem_control, mem_mask); -} - -#ifdef CONFIG_BFIN_ICACHE -void bfin_icache_init(struct cplb_entry *icplb_tbl) -{ - bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL, - (IMC | ENICPLB)); -} -#endif - -#ifdef CONFIG_BFIN_DCACHE -void bfin_dcache_init(struct cplb_entry *dcplb_tbl) -{ - /* - * Anomaly notes: - * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL - * register, so that the port preferences for DAG0 and DAG1 are set - * to port B - */ - bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL, - (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0))); -} -#endif - -#endif diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S deleted file mode 100644 index 9f4dd35bfd74..000000000000 --- a/arch/blackfin/mach-common/cache.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Blackfin cache control code - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include - -/* 05000443 - IFLUSH cannot be last instruction in hardware loop */ -#if ANOMALY_05000443 -# define BROK_FLUSH_INST "IFLUSH" -#else -# define BROK_FLUSH_INST "no anomaly! yeah!" -#endif - -/* Since all L1 caches work the same way, we use the same method for flushing - * them. Only the actual flush instruction differs. We write this in asm as - * GCC can be hard to coax into writing nice hardware loops. - * - * Also, we assume the following register setup: - * R0 = start address - * R1 = end address - */ -.macro do_flush flushins:req label - - R2 = -L1_CACHE_BYTES; - - /* start = (start & -L1_CACHE_BYTES) */ - R0 = R0 & R2; - - /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ - R1 += -1; - R1 = R1 & R2; - R1 += L1_CACHE_BYTES; - - /* count = (end - start) >> L1_CACHE_SHIFT */ - R2 = R1 - R0; - R2 >>= L1_CACHE_SHIFT; - P1 = R2; - -.ifnb \label -\label : -.endif - P0 = R0; - - LSETUP (1f, 2f) LC1 = P1; -1: -.ifeqs "\flushins", BROK_FLUSH_INST - \flushins [P0++]; - nop; - nop; -2: nop; -.else -2: \flushins [P0++]; -.endif - - RTS; -.endm - -#ifdef CONFIG_ICACHE_FLUSH_L1 -.section .l1.text -#else -.text -#endif - -/* Invalidate all instruction cache lines assocoiated with this memory area */ -#ifdef CONFIG_SMP -# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1 -#endif -ENTRY(_blackfin_icache_flush_range) - do_flush IFLUSH -ENDPROC(_blackfin_icache_flush_range) - -#ifdef CONFIG_SMP -.text -# undef _blackfin_icache_flush_range -ENTRY(_blackfin_icache_flush_range) - p0.L = LO(DSPID); - p0.H = HI(DSPID); - r3 = [p0]; - r3 = r3.b (z); - p2 = r3; - p0.L = _blackfin_iflush_l1_entry; - p0.H = _blackfin_iflush_l1_entry; - p0 = p0 + (p2 << 2); - p1 = [p0]; - jump (p1); -ENDPROC(_blackfin_icache_flush_range) -#endif - -#ifdef CONFIG_DCACHE_FLUSH_L1 -.section .l1.text -#else -.text -#endif - -/* Throw away all D-cached data in specified region without any obligation to - * write them back. Since the Blackfin ISA does not have an "invalidate" - * instruction, we use flush/invalidate. Perhaps as a speed optimization we - * could bang on the DTEST MMRs ... - */ -ENTRY(_blackfin_dcache_invalidate_range) - do_flush FLUSHINV -ENDPROC(_blackfin_dcache_invalidate_range) - -/* Flush all data cache lines assocoiated with this memory area */ -ENTRY(_blackfin_dcache_flush_range) - do_flush FLUSH, .Ldfr -ENDPROC(_blackfin_dcache_flush_range) - -/* Our headers convert the page structure to an address, so just need to flush - * its contents like normal. We know the start address is page aligned (which - * greater than our cache alignment), as is the end address. So just jump into - * the middle of the dcache flush function. - */ -ENTRY(_blackfin_dflush_page) - P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); - jump .Ldfr; -ENDPROC(_blackfin_dflush_page) diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h deleted file mode 100644 index fed851a51aaf..000000000000 --- a/arch/blackfin/mach-common/clock.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __MACH_COMMON_CLKDEV_H -#define __MACH_COMMON_CLKDEV_H - -#include - -struct clk_ops { - unsigned long (*get_rate)(struct clk *clk); - unsigned long (*round_rate)(struct clk *clk, unsigned long rate); - int (*set_rate)(struct clk *clk, unsigned long rate); - int (*enable)(struct clk *clk); - int (*disable)(struct clk *clk); -}; - -struct clk { - const char *name; - unsigned long rate; - spinlock_t lock; - u32 flags; - const struct clk_ops *ops; - const struct params *params; - void __iomem *reg; - u32 mask; - u32 shift; -}; - -#endif - diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c deleted file mode 100644 index d436bd907fc8..000000000000 --- a/arch/blackfin/mach-common/clocks-init.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_BF60x - -#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF) -#define CGU_DIV_VAL \ - ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \ - (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \ - (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \ - (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \ - (CONFIG_DCLK_DIV << DSEL_OFFSET)) - -#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000) -#if ((CONFIG_BFIN_DCLK != 125) && \ - (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \ - (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \ - (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250)) -#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" -#endif - -#else -#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ -#define PLL_CTL_VAL \ - (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ - (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) -#endif - -__attribute__((l1_text)) -static void do_sync(void) -{ - __builtin_bfin_ssync(); -} - -__attribute__((l1_text)) -void init_clocks(void) -{ - /* Kill any active DMAs as they may trigger external memory accesses - * in the middle of reprogramming things, and that'll screw us up. - * For example, any automatic DMAs left by U-Boot for splash screens. - */ -#ifdef CONFIG_BF60x - init_cgu(CGU_DIV_VAL, CGU_CTL_VAL); - init_dmc(CONFIG_BFIN_DCLK); -#else - size_t i; - for (i = 0; i < MAX_DMA_CHANNELS; ++i) { - struct dma_register *dma = dma_io_base_addr[i]; - dma->cfg = 0; - } - - do_sync(); - -#ifdef SIC_IWR0 - bfin_write_SIC_IWR0(IWR_ENABLE(0)); -# ifdef SIC_IWR1 - /* BF52x system reset does not properly reset SIC_IWR1 which - * will screw up the bootrom as it relies on MDMA0/1 waking it - * up from IDLE instructions. See this report for more info: - * http://blackfin.uclinux.org/gf/tracker/4323 - */ - if (ANOMALY_05000435) - bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); - else - bfin_write_SIC_IWR1(IWR_DISABLE_ALL); -# endif -# ifdef SIC_IWR2 - bfin_write_SIC_IWR2(IWR_DISABLE_ALL); -# endif -#else - bfin_write_SIC_IWR(IWR_ENABLE(0)); -#endif - do_sync(); -#ifdef EBIU_SDGCTL - bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); - do_sync(); -#endif - -#ifdef CLKBUFOE - bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE); - do_sync(); - __asm__ __volatile__("IDLE;"); -#endif - bfin_write_PLL_LOCKCNT(0x300); - do_sync(); - /* We always write PLL_CTL thus avoiding Anomaly 05000242 */ - bfin_write16(PLL_CTL, PLL_CTL_VAL); - __asm__ __volatile__("IDLE;"); - bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); -#ifdef EBIU_SDGCTL - bfin_write_EBIU_SDRRC(mem_SDRRC); - bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL); -#else - bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); - do_sync(); - bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1); - bfin_write_EBIU_DDRCTL0(mem_DDRCTL0); - bfin_write_EBIU_DDRCTL1(mem_DDRCTL1); - bfin_write_EBIU_DDRCTL2(mem_DDRCTL2); -#ifdef CONFIG_MEM_EBIU_DDRQUE - bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); -#endif -#endif -#endif - do_sync(); - bfin_read16(0); - -} diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c deleted file mode 100644 index 724a8c5f5578..000000000000 --- a/arch/blackfin/mach-common/dpmc.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define DRIVER_NAME "bfin dpmc" - -struct bfin_dpmc_platform_data *pdata; - -/** - * bfin_set_vlev - Update VLEV field in VR_CTL Reg. - * Avoid BYPASS sequence - */ -static void bfin_set_vlev(unsigned int vlev) -{ - unsigned pll_lcnt; - - pll_lcnt = bfin_read_PLL_LOCKCNT(); - - bfin_write_PLL_LOCKCNT(1); - bfin_write_VR_CTL((bfin_read_VR_CTL() & ~VLEV) | vlev); - bfin_write_PLL_LOCKCNT(pll_lcnt); -} - -/** - * bfin_get_vlev - Get CPU specific VLEV from platform device data - */ -static unsigned int bfin_get_vlev(unsigned int freq) -{ - int i; - - if (!pdata) - goto err_out; - - freq >>= 16; - - for (i = 0; i < pdata->tabsize; i++) - if (freq <= (pdata->tuple_tab[i] & 0xFFFF)) - return pdata->tuple_tab[i] >> 16; - -err_out: - printk(KERN_WARNING "DPMC: No suitable CCLK VDDINT voltage pair found\n"); - return VLEV_120; -} - -#ifdef CONFIG_CPU_FREQ -# ifdef CONFIG_SMP -static void bfin_idle_this_cpu(void *info) -{ - unsigned long flags = 0; - unsigned long iwr0, iwr1, iwr2; - unsigned int cpu = smp_processor_id(); - - local_irq_save_hw(flags); - bfin_iwr_set_sup0(&iwr0, &iwr1, &iwr2); - - platform_clear_ipi(cpu, IRQ_SUPPLE_0); - SSYNC(); - asm("IDLE;"); - bfin_iwr_restore(iwr0, iwr1, iwr2); - - local_irq_restore_hw(flags); -} - -static void bfin_idle_cpu(void) -{ - smp_call_function(bfin_idle_this_cpu, NULL, 0); -} - -static void bfin_wakeup_cpu(void) -{ - unsigned int cpu; - unsigned int this_cpu = smp_processor_id(); - cpumask_t mask; - - cpumask_copy(&mask, cpu_online_mask); - cpumask_clear_cpu(this_cpu, &mask); - for_each_cpu(cpu, &mask) - platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); -} - -# else -static void bfin_idle_cpu(void) {} -static void bfin_wakeup_cpu(void) {} -# endif - -static int -vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data) -{ - struct cpufreq_freqs *freq = data; - - if (freq->cpu != CPUFREQ_CPU) - return 0; - - if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) { - bfin_idle_cpu(); - bfin_set_vlev(bfin_get_vlev(freq->new)); - udelay(pdata->vr_settling_time); /* Wait until Volatge settled */ - bfin_wakeup_cpu(); - } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) { - bfin_idle_cpu(); - bfin_set_vlev(bfin_get_vlev(freq->new)); - bfin_wakeup_cpu(); - } - - return 0; -} - -static struct notifier_block vreg_cpufreq_notifier_block = { - .notifier_call = vreg_cpufreq_notifier -}; -#endif /* CONFIG_CPU_FREQ */ - -/** - * bfin_dpmc_probe - - * - */ -static int bfin_dpmc_probe(struct platform_device *pdev) -{ - if (pdev->dev.platform_data) - pdata = pdev->dev.platform_data; - else - return -EINVAL; - - return cpufreq_register_notifier(&vreg_cpufreq_notifier_block, - CPUFREQ_TRANSITION_NOTIFIER); -} - -/** - * bfin_dpmc_remove - - */ -static int bfin_dpmc_remove(struct platform_device *pdev) -{ - pdata = NULL; - return cpufreq_unregister_notifier(&vreg_cpufreq_notifier_block, - CPUFREQ_TRANSITION_NOTIFIER); -} - -struct platform_driver bfin_dpmc_device_driver = { - .probe = bfin_dpmc_probe, - .remove = bfin_dpmc_remove, - .driver = { - .name = DRIVER_NAME, - } -}; -module_platform_driver(bfin_dpmc_device_driver); - -MODULE_AUTHOR("Michael Hennerich "); -MODULE_DESCRIPTION("cpu power management driver for Blackfin"); -MODULE_LICENSE("GPL"); diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S deleted file mode 100644 index de99f3aac2c5..000000000000 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include - -.section .l1.text -ENTRY(_sleep_mode) - [--SP] = (R7:4, P5:3); - [--SP] = RETS; - - call _set_sic_iwr; - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R1 = W[P0](z); - BITSET (R1, 3); - W[P0] = R1.L; - - CLI R2; - SSYNC; - IDLE; - STI R2; - - call _test_pll_locked; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R7 = w[p0](z); - BITCLR (R7, 3); - BITCLR (R7, 5); - w[p0] = R7.L; - IDLE; - - bfin_init_pm_bench_cycles; - - call _test_pll_locked; - - RETS = [SP++]; - (R7:4, P5:3) = [SP++]; - RTS; -ENDPROC(_sleep_mode) - -/* - * This func never returns as it puts the part into hibernate, and - * is only called from do_hibernate, so we don't bother saving or - * restoring any of the normal C runtime state. When we wake up, - * the entry point will be in do_hibernate and not here. - * - * We accept just one argument -- the value to write to VR_CTL. - */ - -ENTRY(_hibernate_mode) - /* Save/setup the regs we need early for minor pipeline optimization */ - R4 = R0; - - P3.H = hi(VR_CTL); - P3.L = lo(VR_CTL); - /* Disable all wakeup sources */ - R0 = IWR_DISABLE_ALL; - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - call _set_sic_iwr; - call _set_dram_srfs; - SSYNC; - - /* Finally, we climb into our cave to hibernate */ - W[P3] = R4.L; - - bfin_init_pm_bench_cycles; - - CLI R2; - IDLE; -.Lforever: - jump .Lforever; -ENDPROC(_hibernate_mode) - -ENTRY(_sleep_deeper) - [--SP] = (R7:4, P5:3); - [--SP] = RETS; - - CLI R4; - - P3 = R0; - P4 = R1; - P5 = R2; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; - call _set_dram_srfs; /* Set SDRAM Self Refresh */ - - P0.H = hi(PLL_DIV); - P0.L = lo(PLL_DIV); - R6 = W[P0](z); - R0.L = 0xF; - W[P0] = R0.l; /* Set Max VCO to SCLK divider */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R5 = W[P0](z); - R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9; - W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */ - - SSYNC; - IDLE; - - call _test_pll_locked; - - P0.H = hi(VR_CTL); - P0.L = lo(VR_CTL); - R7 = W[P0](z); - R1 = 0x6; - R1 <<= 16; - R2 = 0x0404(Z); - R1 = R1|R2; - - R2 = DEPOSIT(R7, R1); - W[P0] = R2; /* Set Min Core Voltage */ - - SSYNC; - IDLE; - - call _test_pll_locked; - - R0 = P3; - R1 = P4; - R3 = P5; - call _set_sic_iwr; /* Set Awake from IDLE */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R0 = W[P0](z); - BITSET (R0, 3); - W[P0] = R0.L; /* Turn CCLK OFF */ - SSYNC; - IDLE; - - call _test_pll_locked; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; /* Set Awake from IDLE PLL */ - - P0.H = hi(VR_CTL); - P0.L = lo(VR_CTL); - W[P0]= R7; - - SSYNC; - IDLE; - - bfin_init_pm_bench_cycles; - - call _test_pll_locked; - - P0.H = hi(PLL_DIV); - P0.L = lo(PLL_DIV); - W[P0]= R6; /* Restore CCLK and SCLK divider */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - w[p0] = R5; /* Restore VCO multiplier */ - IDLE; - call _test_pll_locked; - - call _unset_dram_srfs; /* SDRAM Self Refresh Off */ - - STI R4; - - RETS = [SP++]; - (R7:4, P5:3) = [SP++]; - RTS; -ENDPROC(_sleep_deeper) - -ENTRY(_set_dram_srfs) - /* set the dram to self refresh mode */ - SSYNC; -#if defined(EBIU_RSTCTL) /* DDR */ - P0.H = hi(EBIU_RSTCTL); - P0.L = lo(EBIU_RSTCTL); - R2 = [P0]; - BITSET(R2, 3); /* SRREQ enter self-refresh mode */ - [P0] = R2; - SSYNC; -1: - R2 = [P0]; - CC = BITTST(R2, 4); - if !CC JUMP 1b; -#else /* SDRAM */ - P0.L = lo(EBIU_SDGCTL); - P0.H = hi(EBIU_SDGCTL); - P1.L = lo(EBIU_SDSTAT); - P1.H = hi(EBIU_SDSTAT); - - R2 = [P0]; - BITSET(R2, 24); /* SRFS enter self-refresh mode */ - [P0] = R2; - SSYNC; - -1: - R2 = w[P1]; - SSYNC; - cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */ - if !cc jump 1b; - - R2 = [P0]; - BITCLR(R2, 0); /* SCTLE disable CLKOUT */ - [P0] = R2; -#endif - RTS; -ENDPROC(_set_dram_srfs) - -ENTRY(_unset_dram_srfs) - /* set the dram out of self refresh mode */ - -#if defined(EBIU_RSTCTL) /* DDR */ - P0.H = hi(EBIU_RSTCTL); - P0.L = lo(EBIU_RSTCTL); - R2 = [P0]; - BITCLR(R2, 3); /* clear SRREQ bit */ - [P0] = R2; -#elif defined(EBIU_SDGCTL) /* SDRAM */ - /* release CLKOUT from self-refresh */ - P0.L = lo(EBIU_SDGCTL); - P0.H = hi(EBIU_SDGCTL); - - R2 = [P0]; - BITSET(R2, 0); /* SCTLE enable CLKOUT */ - [P0] = R2 - SSYNC; - - /* release SDRAM from self-refresh */ - R2 = [P0]; - BITCLR(R2, 24); /* clear SRFS bit */ - [P0] = R2 -#endif - - SSYNC; - RTS; -ENDPROC(_unset_dram_srfs) - -ENTRY(_set_sic_iwr) -#ifdef SIC_IWR0 - P0.H = hi(SYSMMR_BASE); - P0.L = lo(SYSMMR_BASE); - [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0; - [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1; -# ifdef SIC_IWR2 - [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2; -# endif -#else - P0.H = hi(SIC_IWR); - P0.L = lo(SIC_IWR); - [P0] = R0; -#endif - - SSYNC; - RTS; -ENDPROC(_set_sic_iwr) - -ENTRY(_test_pll_locked) - P0.H = hi(PLL_STAT); - P0.L = lo(PLL_STAT); -1: - R0 = W[P0] (Z); - CC = BITTST(R0,5); - IF !CC JUMP 1b; - RTS; -ENDPROC(_test_pll_locked) - -.section .text -ENTRY(_do_hibernate) - bfin_cpu_reg_save; - bfin_sys_mmr_save; - bfin_core_mmr_save; - - /* Setup args to hibernate mode early for pipeline optimization */ - R0 = M3; - P1.H = _hibernate_mode; - P1.L = _hibernate_mode; - - /* Save Magic, return address and Stack Pointer */ - P0 = 0; - R1.H = 0xDEAD; /* Hibernate Magic */ - R1.L = 0xBEEF; - R2.H = .Lpm_resume_here; - R2.L = .Lpm_resume_here; - [P0++] = R1; /* Store Hibernate Magic */ - [P0++] = R2; /* Save Return Address */ - [P0++] = SP; /* Save Stack Pointer */ - - /* Must use an indirect call as we need to jump to L1 */ - call (P1); /* Goodbye */ - -.Lpm_resume_here: - - bfin_core_mmr_restore; - bfin_sys_mmr_restore; - bfin_cpu_reg_restore; - - [--sp] = RETI; /* Clear Global Interrupt Disable */ - SP += 4; - - RTS; -ENDPROC(_do_hibernate) diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S deleted file mode 100644 index 8d9431e22e8c..000000000000 --- a/arch/blackfin/mach-common/entry.S +++ /dev/null @@ -1,1711 +0,0 @@ -/* - * Contains the system-call and fault low-level handling routines. - * This also contains the timer-interrupt handler, as well as all - * interrupts and faults that can result in a task-switch. - * - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -/* NOTE: This code handles signal-recognition, which happens every time - * after a timer-interrupt and after each system call. - */ - -#include -#include -#include -#include -#include -#include -#include /* TIF_NEED_RESCHED */ -#include -#include -#include - -#include - - -#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 -.section .l1.text -#else -.text -#endif - -/* Slightly simplified and streamlined entry point for CPLB misses. - * This one does not lower the level to IRQ5, and thus can be used to - * patch up CPLB misses on the kernel stack. - */ -#if ANOMALY_05000261 -#define _ex_dviol _ex_workaround_261 -#define _ex_dmiss _ex_workaround_261 -#define _ex_dmult _ex_workaround_261 - -ENTRY(_ex_workaround_261) - /* - * Work around an anomaly: if we see a new DCPLB fault, return - * without doing anything. Then, if we get the same fault again, - * handle it. - */ - P4 = R7; /* Store EXCAUSE */ - - GET_PDA(p5, r7); - r7 = [p5 + PDA_LFRETX]; - r6 = retx; - [p5 + PDA_LFRETX] = r6; - cc = r6 == r7; - if !cc jump _bfin_return_from_exception; - /* fall through */ - R7 = P4; - R6 = VEC_CPLB_M; /* Data CPLB Miss */ - cc = R6 == R7; - if cc jump _ex_dcplb_miss (BP); -#ifdef CONFIG_MPU - R6 = VEC_CPLB_VL; /* Data CPLB Violation */ - cc = R6 == R7; - if cc jump _ex_dcplb_viol (BP); -#endif - /* Handle Data CPLB Protection Violation - * and Data CPLB Multiple Hits - Linux Trap Zero - */ - jump _ex_trap_c; -ENDPROC(_ex_workaround_261) - -#else -#ifdef CONFIG_MPU -#define _ex_dviol _ex_dcplb_viol -#else -#define _ex_dviol _ex_trap_c -#endif -#define _ex_dmiss _ex_dcplb_miss -#define _ex_dmult _ex_trap_c -#endif - - -ENTRY(_ex_dcplb_viol) -ENTRY(_ex_dcplb_miss) -ENTRY(_ex_icplb_miss) - (R7:6,P5:4) = [sp++]; - /* We leave the previously pushed ASTAT on the stack. */ - SAVE_CONTEXT_CPLB - - /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that - * will change the stack pointer. */ - R0 = SEQSTAT; - R1 = SP; - - DEBUG_HWTRACE_SAVE(p5, r7) - - sp += -12; - call _cplb_hdr; - sp += 12; - CC = R0 == 0; - IF !CC JUMP _handle_bad_cplb; - -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* While we were processing this, did we double fault? */ - r7 = SEQSTAT; /* reason code is in bit 5:0 */ - r6.l = lo(SEQSTAT_EXCAUSE); - r6.h = hi(SEQSTAT_EXCAUSE); - r7 = r7 & r6; - r6 = 0x25; - CC = R7 == R6; - if CC JUMP _double_fault; -#endif - - DEBUG_HWTRACE_RESTORE(p5, r7) - RESTORE_CONTEXT_CPLB - ASTAT = [SP++]; - SP = EX_SCRATCH_REG; - rtx; -ENDPROC(_ex_icplb_miss) - -ENTRY(_ex_syscall) - raise 15; /* invoked by TRAP #0, for sys call */ - jump.s _bfin_return_from_exception; -ENDPROC(_ex_syscall) - -ENTRY(_ex_single_step) - /* If we just returned from an interrupt, the single step event is - for the RTI instruction. */ - r7 = retx; - r6 = reti; - cc = r7 == r6; - if cc jump _bfin_return_from_exception; - -#ifdef CONFIG_KGDB - /* Don't do single step in hardware exception handler */ - p5.l = lo(IPEND); - p5.h = hi(IPEND); - r6 = [p5]; - cc = bittst(r6, 4); - if cc jump _bfin_return_from_exception; - cc = bittst(r6, 5); - if cc jump _bfin_return_from_exception; - - /* skip single step if current interrupt priority is higher than - * that of the first instruction, from which gdb starts single step */ - r6 >>= 6; - r7 = 10; -.Lfind_priority_start: - cc = bittst(r6, 0); - if cc jump .Lfind_priority_done; - r6 >>= 1; - r7 += -1; - cc = r7 == 0; - if cc jump .Lfind_priority_done; - jump.s .Lfind_priority_start; -.Lfind_priority_done: - p4.l = _kgdb_single_step; - p4.h = _kgdb_single_step; - r6 = [p4]; - cc = r6 == 0; - if cc jump .Ldo_single_step; - r6 += -1; - cc = r6 < r7; - if cc jump 1f; -.Ldo_single_step: -#else - /* If we were in user mode, do the single step normally. */ - p5.l = lo(IPEND); - p5.h = hi(IPEND); - r6 = [p5]; - r7 = 0xffe0 (z); - r7 = r7 & r6; - cc = r7 == 0; - if !cc jump 1f; -#endif -#ifdef CONFIG_EXACT_HWERR - /* Read the ILAT, and to check to see if the process we are - * single stepping caused a previous hardware error - * If so, do not single step, (which lowers to IRQ5, and makes - * us miss the error). - */ - p5.l = lo(ILAT); - p5.h = hi(ILAT); - r7 = [p5]; - cc = bittst(r7, EVT_IVHW_P); - if cc jump 1f; -#endif - /* Single stepping only a single instruction, so clear the trace - * bit here. */ - r7 = syscfg; - bitclr (r7, SYSCFG_SSSTEP_P); - syscfg = R7; - jump _ex_trap_c; - -1: - /* - * We were in an interrupt handler. By convention, all of them save - * SYSCFG with their first instruction, so by checking whether our - * RETX points at the entry point, we can determine whether to allow - * a single step, or whether to clear SYSCFG. - * - * First, find out the interrupt level and the event vector for it. - */ - p5.l = lo(EVT0); - p5.h = hi(EVT0); - p5 += -4; -2: - r7 = rot r7 by -1; - p5 += 4; - if !cc jump 2b; - - /* What we actually do is test for the _second_ instruction in the - * IRQ handler. That way, if there are insns following the restore - * of SYSCFG after leaving the handler, we will not turn off SYSCFG - * for them. */ - - r7 = [p5]; - r7 += 2; - r6 = RETX; - cc = R7 == R6; - if !cc jump _bfin_return_from_exception; - - r7 = syscfg; - bitclr (r7, SYSCFG_SSSTEP_P); /* Turn off single step */ - syscfg = R7; - - /* Fall through to _bfin_return_from_exception. */ -ENDPROC(_ex_single_step) - -ENTRY(_bfin_return_from_exception) -#if ANOMALY_05000257 - R7=LC0; - LC0=R7; - R7=LC1; - LC1=R7; -#endif - -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* While we were processing the current exception, - * did we cause another, and double fault? - */ - r7 = SEQSTAT; /* reason code is in bit 5:0 */ - r6.l = lo(SEQSTAT_EXCAUSE); - r6.h = hi(SEQSTAT_EXCAUSE); - r7 = r7 & r6; - r6 = VEC_UNCOV; - CC = R7 == R6; - if CC JUMP _double_fault; -#endif - - (R7:6,P5:4) = [sp++]; - ASTAT = [sp++]; - sp = EX_SCRATCH_REG; - rtx; -ENDPROC(_bfin_return_from_exception) - -ENTRY(_handle_bad_cplb) - DEBUG_HWTRACE_RESTORE(p5, r7) - /* To get here, we just tried and failed to change a CPLB - * so, handle things in trap_c (C code), by lowering to - * IRQ5, just like we normally do. Since this is not a - * "normal" return path, we have a do a lot of stuff to - * the stack to get ready so, we can fall through - we - * need to make a CPLB exception look like a normal exception - */ - RESTORE_CONTEXT_CPLB - /* ASTAT is still on the stack, where it is needed. */ - [--sp] = (R7:6,P5:4); - -ENTRY(_ex_replaceable) - nop; - -ENTRY(_ex_trap_c) - /* The only thing that has been saved in this context is - * (R7:6,P5:4), ASTAT & SP - don't use anything else - */ - - GET_PDA(p5, r6); - - /* Make sure we are not in a double fault */ - p4.l = lo(IPEND); - p4.h = hi(IPEND); - r7 = [p4]; - CC = BITTST (r7, 5); - if CC jump _double_fault; - [p5 + PDA_EXIPEND] = r7; - - /* Call C code (trap_c) to handle the exception, which most - * likely involves sending a signal to the current process. - * To avoid double faults, lower our priority to IRQ5 first. - */ - r7.h = _exception_to_level5; - r7.l = _exception_to_level5; - p4.l = lo(EVT5); - p4.h = hi(EVT5); - [p4] = r7; - csync; - - /* - * Save these registers, as they are only valid in exception context - * (where we are now - as soon as we defer to IRQ5, they can change) - * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3, - * but they are not very interesting, so don't save them - */ - - p4.l = lo(DCPLB_FAULT_ADDR); - p4.h = hi(DCPLB_FAULT_ADDR); - r7 = [p4]; - [p5 + PDA_DCPLB] = r7; - - p4.l = lo(ICPLB_FAULT_ADDR); - p4.h = hi(ICPLB_FAULT_ADDR); - r6 = [p4]; - [p5 + PDA_ICPLB] = r6; - - r6 = retx; - [p5 + PDA_RETX] = r6; - - r6 = SEQSTAT; - [p5 + PDA_SEQSTAT] = r6; - - /* Save the state of single stepping */ - r6 = SYSCFG; - [p5 + PDA_SYSCFG] = r6; - /* Clear it while we handle the exception in IRQ5 mode */ - BITCLR(r6, SYSCFG_SSSTEP_P); - SYSCFG = r6; - - /* Save the current IMASK, since we change in order to jump to level 5 */ - cli r6; - [p5 + PDA_EXIMASK] = r6; - - p4.l = lo(SAFE_USER_INSTRUCTION); - p4.h = hi(SAFE_USER_INSTRUCTION); - retx = p4; - - /* Disable all interrupts, but make sure level 5 is enabled so - * we can switch to that level. - */ - r6 = 0x3f; - sti r6; - - /* In case interrupts are disabled IPEND[4] (global interrupt disable bit) - * clear it (re-enabling interrupts again) by the special sequence of pushing - * RETI onto the stack. This way we can lower ourselves to IVG5 even if the - * exception was taken after the interrupt handler was called but before it - * got a chance to enable global interrupts itself. - */ - [--sp] = reti; - sp += 4; - - raise 5; - jump.s _bfin_return_from_exception; -ENDPROC(_ex_trap_c) - -/* We just realized we got an exception, while we were processing a different - * exception. This is a unrecoverable event, so crash. - * Note: this cannot be ENTRY() as we jump here with "if cc jump" ... - */ -ENTRY(_double_fault) - /* Turn caches & protection off, to ensure we don't get any more - * double exceptions - */ - - P4.L = LO(IMEM_CONTROL); - P4.H = HI(IMEM_CONTROL); - - R5 = [P4]; /* Control Register*/ - BITCLR(R5,ENICPLB_P); - CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ - [P4] = R5; - SSYNC; - - P4.L = LO(DMEM_CONTROL); - P4.H = HI(DMEM_CONTROL); - R5 = [P4]; - BITCLR(R5,ENDCPLB_P); - CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ - [P4] = R5; - SSYNC; - - /* Fix up the stack */ - (R7:6,P5:4) = [sp++]; - ASTAT = [sp++]; - SP = EX_SCRATCH_REG; - - /* We should be out of the exception stack, and back down into - * kernel or user space stack - */ - SAVE_ALL_SYS - - /* The dumping functions expect the return address in the RETI - * slot. */ - r6 = retx; - [sp + PT_PC] = r6; - - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - SP += -12; - pseudo_long_call _double_fault_c, p5; - SP += 12; -.L_double_fault_panic: - JUMP .L_double_fault_panic - -ENDPROC(_double_fault) - -ENTRY(_exception_to_level5) - SAVE_ALL_SYS - - GET_PDA(p5, r7); /* Fetch current PDA */ - r6 = [p5 + PDA_RETX]; - [sp + PT_PC] = r6; - - r6 = [p5 + PDA_SYSCFG]; - [sp + PT_SYSCFG] = r6; - - r6 = [p5 + PDA_SEQSTAT]; /* Read back seqstat */ - [sp + PT_SEQSTAT] = r6; - - /* Restore the hardware error vector. */ - r7.h = _evt_ivhw; - r7.l = _evt_ivhw; - p4.l = lo(EVT5); - p4.h = hi(EVT5); - [p4] = r7; - csync; - -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* Now that we have the hardware error vector programmed properly - * we can re-enable interrupts (IPEND[4]), so if the _trap_c causes - * another hardware error, we can catch it (self-nesting). - */ - [--sp] = reti; - sp += 4; -#endif - - r7 = [p5 + PDA_EXIPEND] /* Read the IPEND from the Exception state */ - [sp + PT_IPEND] = r7; /* Store IPEND onto the stack */ - - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - SP += -12; - pseudo_long_call _trap_c, p4; - SP += 12; - - /* If interrupts were off during the exception (IPEND[4] = 1), turn them off - * before we return. - */ - CC = BITTST(r7, EVT_IRPTEN_P) - if !CC jump 1f; - /* this will load a random value into the reti register - but that is OK, - * since we do restore it to the correct value in the 'RESTORE_ALL_SYS' macro - */ - sp += -4; - reti = [sp++]; -1: - /* restore the interrupt mask (IMASK) */ - r6 = [p5 + PDA_EXIMASK]; - sti r6; - - call _ret_from_exception; - RESTORE_ALL_SYS - rti; -ENDPROC(_exception_to_level5) - -ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ - /* Since the kernel stack can be anywhere, it's not guaranteed to be - * covered by a CPLB. Switch to an exception stack; use RETN as a - * scratch register (for want of a better option). - */ - EX_SCRATCH_REG = sp; - GET_PDA_SAFE(sp); - sp = [sp + PDA_EXSTACK]; - /* Try to deal with syscalls quickly. */ - [--sp] = ASTAT; - [--sp] = (R7:6,P5:4); - - ANOMALY_283_315_WORKAROUND(p5, r7) - -#ifdef CONFIG_EXACT_HWERR - /* Make sure all pending read/writes complete. This will ensure any - * accesses which could cause hardware errors completes, and signal - * the the hardware before we do something silly, like crash the - * kernel. We don't need to work around anomaly 05000312, since - * we are already atomic - */ - ssync; -#endif - -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* - * Save these registers, as they are only valid in exception context - * (where we are now - as soon as we defer to IRQ5, they can change) - * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3, - * but they are not very interesting, so don't save them - */ - - GET_PDA(p5, r7); - p4.l = lo(DCPLB_FAULT_ADDR); - p4.h = hi(DCPLB_FAULT_ADDR); - r7 = [p4]; - [p5 + PDA_DF_DCPLB] = r7; - - p4.l = lo(ICPLB_FAULT_ADDR); - p4.h = hi(ICPLB_FAULT_ADDR); - r7 = [p4]; - [p5 + PDA_DF_ICPLB] = r7; - - r7 = retx; - [p5 + PDA_DF_RETX] = r7; - - r7 = SEQSTAT; /* reason code is in bit 5:0 */ - [p5 + PDA_DF_SEQSTAT] = r7; -#else - r7 = SEQSTAT; /* reason code is in bit 5:0 */ -#endif - r6.l = lo(SEQSTAT_EXCAUSE); - r6.h = hi(SEQSTAT_EXCAUSE); - r7 = r7 & r6; - p5.h = _ex_table; - p5.l = _ex_table; - p4 = r7; - p5 = p5 + (p4 << 2); - p4 = [p5]; - jump (p4); - -.Lbadsys: - r7 = -ENOSYS; /* signextending enough */ - [sp + PT_R0] = r7; /* return value from system call */ - jump .Lsyscall_really_exit; -ENDPROC(_trap) - -ENTRY(_system_call) - /* Store IPEND */ - p2.l = lo(IPEND); - p2.h = hi(IPEND); - csync; - r0 = [p2]; - [sp + PT_IPEND] = r0; - - /* Store RETS for now */ - r0 = rets; - [sp + PT_RESERVED] = r0; - /* Set the stack for the current process */ - r7 = sp; - r6.l = lo(ALIGN_PAGE_MASK); - r6.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r6; /* thread_info */ - p2 = r7; - p2 = [p2]; - - [p2+(TASK_THREAD+THREAD_KSP)] = sp; -#ifdef CONFIG_IPIPE - r0 = sp; - SP += -12; - pseudo_long_call ___ipipe_syscall_root, p0; - SP += 12; - cc = r0 == 1; - if cc jump .Lsyscall_really_exit; - cc = r0 == -1; - if cc jump .Lresume_userspace; - r3 = [sp + PT_R3]; - r4 = [sp + PT_R4]; - p0 = [sp + PT_ORIG_P0]; -#endif /* CONFIG_IPIPE */ - - /* are we tracing syscalls?*/ - r7 = sp; - r6.l = lo(ALIGN_PAGE_MASK); - r6.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r6; - p2 = r7; - r7 = [p2+TI_FLAGS]; - CC = BITTST(r7,TIF_SYSCALL_TRACE); - if CC JUMP _sys_trace; - CC = BITTST(r7,TIF_SINGLESTEP); - if CC JUMP _sys_trace; - - /* Make sure the system call # is valid */ - p4 = __NR_syscall; - /* System call number is passed in P0 */ - cc = p4 <= p0; - if cc jump .Lbadsys; - - /* Execute the appropriate system call */ - - p4 = p0; - p5.l = _sys_call_table; - p5.h = _sys_call_table; - p5 = p5 + (p4 << 2); - r0 = [sp + PT_R0]; - r1 = [sp + PT_R1]; - r2 = [sp + PT_R2]; - p5 = [p5]; - - [--sp] = r5; - [--sp] = r4; - [--sp] = r3; - SP += -12; - call (p5); - SP += 24; - [sp + PT_R0] = r0; - -.Lresume_userspace: - r7 = sp; - r4.l = lo(ALIGN_PAGE_MASK); - r4.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r4; /* thread_info->flags */ - p5 = r7; -.Lresume_userspace_1: - /* Disable interrupts. */ - [--sp] = reti; - reti = [sp++]; - - r7 = [p5 + TI_FLAGS]; - r4.l = lo(_TIF_WORK_MASK); - r4.h = hi(_TIF_WORK_MASK); - r7 = r7 & r4; - -.Lsyscall_resched: -#ifdef CONFIG_IPIPE - cc = BITTST(r7, TIF_IRQ_SYNC); - if !cc jump .Lsyscall_no_irqsync; - /* - * Clear IPEND[4] manually to undo what resume_userspace_1 just did; - * we need this so that high priority domain interrupts may still - * preempt the current domain while the pipeline log is being played - * back. - */ - [--sp] = reti; - SP += 4; /* don't merge with next insn to keep the pattern obvious */ - SP += -12; - pseudo_long_call ___ipipe_sync_root, p4; - SP += 12; - jump .Lresume_userspace_1; -.Lsyscall_no_irqsync: -#endif - cc = BITTST(r7, TIF_NEED_RESCHED); - if !cc jump .Lsyscall_sigpending; - - /* Reenable interrupts. */ - [--sp] = reti; - sp += 4; - - SP += -12; - pseudo_long_call _schedule, p4; - SP += 12; - - jump .Lresume_userspace_1; - -.Lsyscall_sigpending: - cc = BITTST(r7, TIF_SIGPENDING); - if cc jump .Lsyscall_do_signals; - cc = BITTST(r7, TIF_NOTIFY_RESUME); - if !cc jump .Lsyscall_really_exit; -.Lsyscall_do_signals: - /* Reenable interrupts. */ - [--sp] = reti; - sp += 4; - - r0 = sp; - SP += -12; - pseudo_long_call _do_notify_resume, p5; - SP += 12; - -.Lsyscall_really_exit: - r5 = [sp + PT_RESERVED]; - rets = r5; - rts; -ENDPROC(_system_call) - -/* Do not mark as ENTRY() to avoid error in assembler ... - * this symbol need not be global anyways, so ... - */ -_sys_trace: - r0 = sp; - pseudo_long_call _syscall_trace_enter, p5; - - /* Make sure the system call # is valid */ - p4 = [SP + PT_P0]; - p3 = __NR_syscall; - cc = p3 <= p4; - r0 = -ENOSYS; - if cc jump .Lsys_trace_badsys; - - /* Execute the appropriate system call */ - p5.l = _sys_call_table; - p5.h = _sys_call_table; - p5 = p5 + (p4 << 2); - r0 = [sp + PT_R0]; - r1 = [sp + PT_R1]; - r2 = [sp + PT_R2]; - r3 = [sp + PT_R3]; - r4 = [sp + PT_R4]; - r5 = [sp + PT_R5]; - p5 = [p5]; - - [--sp] = r5; - [--sp] = r4; - [--sp] = r3; - SP += -12; - call (p5); - SP += 24; -.Lsys_trace_badsys: - [sp + PT_R0] = r0; - - r0 = sp; - pseudo_long_call _syscall_trace_leave, p5; - jump .Lresume_userspace; -ENDPROC(_sys_trace) - -ENTRY(_resume) - /* - * Beware - when entering resume, prev (the current task) is - * in r0, next (the new task) is in r1. - */ - p0 = r0; - p1 = r1; - [--sp] = rets; - [--sp] = fp; - [--sp] = (r7:4, p5:3); - - /* save usp */ - p2 = usp; - [p0+(TASK_THREAD+THREAD_USP)] = p2; - - /* save current kernel stack pointer */ - [p0+(TASK_THREAD+THREAD_KSP)] = sp; - - /* save program counter */ - r1.l = _new_old_task; - r1.h = _new_old_task; - [p0+(TASK_THREAD+THREAD_PC)] = r1; - - /* restore the kernel stack pointer */ - sp = [p1+(TASK_THREAD+THREAD_KSP)]; - - /* restore user stack pointer */ - p0 = [p1+(TASK_THREAD+THREAD_USP)]; - usp = p0; - - /* restore pc */ - p0 = [p1+(TASK_THREAD+THREAD_PC)]; - jump (p0); - - /* - * Following code actually lands up in a new (old) task. - */ - -_new_old_task: - (r7:4, p5:3) = [sp++]; - fp = [sp++]; - rets = [sp++]; - - /* - * When we come out of resume, r0 carries "old" task, because we are - * in "new" task. - */ - rts; -ENDPROC(_resume) - -ENTRY(_ret_from_exception) -#ifdef CONFIG_IPIPE - p2.l = _ipipe_percpu_domain; - p2.h = _ipipe_percpu_domain; - r0.l = _ipipe_root; - r0.h = _ipipe_root; - r2 = [p2]; - cc = r0 == r2; - if !cc jump 4f; /* not on behalf of the root domain, get out */ -#endif /* CONFIG_IPIPE */ - p2.l = lo(IPEND); - p2.h = hi(IPEND); - - csync; - r0 = [p2]; - [sp + PT_IPEND] = r0; - -1: - r2 = LO(~0x37) (Z); - r0 = r2 & r0; - cc = r0 == 0; - if !cc jump 4f; /* if not return to user mode, get out */ - - /* Make sure any pending system call or deferred exception - * return in ILAT for this process to get executed, otherwise - * in case context switch happens, system call of - * first process (i.e in ILAT) will be carried - * forward to the switched process - */ - - p2.l = lo(ILAT); - p2.h = hi(ILAT); - r0 = [p2]; - r1 = (EVT_IVG14 | EVT_IVG15) (z); - r0 = r0 & r1; - cc = r0 == 0; - if !cc jump 5f; - - /* Set the stack for the current process */ - r7 = sp; - r4.l = lo(ALIGN_PAGE_MASK); - r4.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r4; /* thread_info->flags */ - p5 = r7; - r7 = [p5 + TI_FLAGS]; - r4.l = lo(_TIF_WORK_MASK); - r4.h = hi(_TIF_WORK_MASK); - r7 = r7 & r4; - cc = r7 == 0; - if cc jump 4f; - - p0.l = lo(EVT15); - p0.h = hi(EVT15); - p1.l = _schedule_and_signal; - p1.h = _schedule_and_signal; - [p0] = p1; - csync; - raise 15; /* raise evt15 to do signal or reschedule */ -4: - r0 = syscfg; - bitclr(r0, SYSCFG_SSSTEP_P); /* Turn off single step */ - syscfg = r0; -5: - rts; -ENDPROC(_ret_from_exception) - -#if defined(CONFIG_PREEMPT) - -ENTRY(_up_to_irq14) -#if ANOMALY_05000281 || ANOMALY_05000461 - r0.l = lo(SAFE_USER_INSTRUCTION); - r0.h = hi(SAFE_USER_INSTRUCTION); - reti = r0; -#endif - -#ifdef CONFIG_DEBUG_HWERR - /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#else - /* Only enable irq14 interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#endif - sti r0; - - p0.l = lo(EVT14); - p0.h = hi(EVT14); - p1.l = _evt_up_evt14; - p1.h = _evt_up_evt14; - [p0] = p1; - csync; - - raise 14; -1: - jump 1b; -ENDPROC(_up_to_irq14) - -ENTRY(_evt_up_evt14) -#ifdef CONFIG_DEBUG_HWERR - r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); - sti r0; -#else - cli r0; -#endif -#ifdef CONFIG_TRACE_IRQFLAGS - [--sp] = rets; - sp += -12; - call _trace_hardirqs_off; - sp += 12; - rets = [sp++]; -#endif - [--sp] = RETI; - SP += 4; - - /* restore normal evt14 */ - p0.l = lo(EVT14); - p0.h = hi(EVT14); - p1.l = _evt_evt14; - p1.h = _evt_evt14; - [p0] = p1; - csync; - - rts; -ENDPROC(_evt_up_evt14) - -#endif - -#ifdef CONFIG_IPIPE - -_resume_kernel_from_int: - r1 = LO(~0x8000) (Z); - r1 = r0 & r1; - r0 = 1; - r0 = r1 - r0; - r2 = r1 & r0; - cc = r2 == 0; - /* Sync the root stage only from the outer interrupt level. */ - if !cc jump .Lnosync; - r0.l = ___ipipe_sync_root; - r0.h = ___ipipe_sync_root; - [--sp] = reti; - [--sp] = rets; - [--sp] = ( r7:4, p5:3 ); - SP += -12; - call ___ipipe_call_irqtail - SP += 12; - ( r7:4, p5:3 ) = [sp++]; - rets = [sp++]; - reti = [sp++]; -.Lnosync: - rts -#elif defined(CONFIG_PREEMPT) - -_resume_kernel_from_int: - /* check preempt_count */ - r7 = sp; - r4.l = lo(ALIGN_PAGE_MASK); - r4.h = hi(ALIGN_PAGE_MASK); - r7 = r7 & r4; - p5 = r7; - r7 = [p5 + TI_PREEMPT]; - cc = r7 == 0x0; - if !cc jump .Lreturn_to_kernel; -.Lneed_schedule: - r7 = [p5 + TI_FLAGS]; - r4.l = lo(_TIF_WORK_MASK); - r4.h = hi(_TIF_WORK_MASK); - r7 = r7 & r4; - cc = BITTST(r7, TIF_NEED_RESCHED); - if !cc jump .Lreturn_to_kernel; - /* - * let schedule done at level 15, otherwise sheduled process will run - * at high level and block low level interrupt - */ - r6 = reti; /* save reti */ - r5.l = .Lkernel_schedule; - r5.h = .Lkernel_schedule; - reti = r5; - rti; -.Lkernel_schedule: - [--sp] = rets; - sp += -12; - pseudo_long_call _preempt_schedule_irq, p4; - sp += 12; - rets = [sp++]; - - [--sp] = rets; - sp += -12; - /* up to irq14 so that reti after restore_all can return to irq15(kernel) */ - pseudo_long_call _up_to_irq14, p4; - sp += 12; - rets = [sp++]; - - reti = r6; /* restore reti so that origin process can return to interrupted point */ - - jump .Lneed_schedule; -#else - -#define _resume_kernel_from_int .Lreturn_to_kernel -#endif - -ENTRY(_return_from_int) - /* If someone else already raised IRQ 15, do nothing. */ - csync; - p2.l = lo(ILAT); - p2.h = hi(ILAT); - r0 = [p2]; - cc = bittst (r0, EVT_IVG15_P); - if cc jump .Lreturn_to_kernel; - - /* if not return to user mode, get out */ - p2.l = lo(IPEND); - p2.h = hi(IPEND); - r0 = [p2]; - r1 = 0x17(Z); - r2 = ~r1; - r2.h = 0; - r0 = r2 & r0; - r1 = 1; - r1 = r0 - r1; - r2 = r0 & r1; - cc = r2 == 0; - if !cc jump _resume_kernel_from_int; - - /* Lower the interrupt level to 15. */ - p0.l = lo(EVT15); - p0.h = hi(EVT15); - p1.l = _schedule_and_signal_from_int; - p1.h = _schedule_and_signal_from_int; - [p0] = p1; - csync; -#if ANOMALY_05000281 || ANOMALY_05000461 - r0.l = lo(SAFE_USER_INSTRUCTION); - r0.h = hi(SAFE_USER_INSTRUCTION); - reti = r0; -#endif - r0 = 0x801f (z); - STI r0; - raise 15; /* raise evt15 to do signal or reschedule */ - rti; -.Lreturn_to_kernel: - rts; -ENDPROC(_return_from_int) - -ENTRY(_lower_to_irq14) -#if ANOMALY_05000281 || ANOMALY_05000461 - r0.l = lo(SAFE_USER_INSTRUCTION); - r0.h = hi(SAFE_USER_INSTRUCTION); - reti = r0; -#endif - -#ifdef CONFIG_DEBUG_HWERR - /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#else - /* Only enable irq14 interrupt, until we transition to _evt_evt14 */ - r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); -#endif - sti r0; - raise 14; - rti; -ENDPROC(_lower_to_irq14) - -ENTRY(_evt_evt14) -#ifdef CONFIG_DEBUG_HWERR - r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); - sti r0; -#else - cli r0; -#endif -#ifdef CONFIG_TRACE_IRQFLAGS - [--sp] = rets; - sp += -12; - call _trace_hardirqs_off; - sp += 12; - rets = [sp++]; -#endif - [--sp] = RETI; - SP += 4; - rts; -ENDPROC(_evt_evt14) - -ENTRY(_schedule_and_signal_from_int) - /* To end up here, vector 15 was changed - so we have to change it - * back. - */ - p0.l = lo(EVT15); - p0.h = hi(EVT15); - p1.l = _evt_system_call; - p1.h = _evt_system_call; - [p0] = p1; - csync; - - /* Set orig_p0 to -1 to indicate this isn't the end of a syscall. */ - r0 = -1 (x); - [sp + PT_ORIG_P0] = r0; - - p1 = rets; - [sp + PT_RESERVED] = p1; - -#ifdef CONFIG_TRACE_IRQFLAGS - /* trace_hardirqs_on() checks if all irqs are disabled. But here IRQ 15 - * is turned on, so disable all irqs. */ - cli r0; - sp += -12; - call _trace_hardirqs_on; - sp += 12; -#endif -#ifdef CONFIG_SMP - GET_PDA(p0, r0); /* Fetch current PDA (can't migrate to other CPU here) */ - r0 = [p0 + PDA_IRQFLAGS]; -#else - p0.l = _bfin_irq_flags; - p0.h = _bfin_irq_flags; - r0 = [p0]; -#endif - sti r0; - - /* finish the userspace "atomic" functions for it */ - r1.l = lo(FIXED_CODE_END); - r1.h = hi(FIXED_CODE_END); - r2 = [sp + PT_PC]; - cc = r1 <= r2; - if cc jump .Lresume_userspace (bp); - - r0 = sp; - sp += -12; - - pseudo_long_call _finish_atomic_sections, p5; - sp += 12; - jump.s .Lresume_userspace; -ENDPROC(_schedule_and_signal_from_int) - -ENTRY(_schedule_and_signal) - SAVE_CONTEXT_SYSCALL - /* To end up here, vector 15 was changed - so we have to change it - * back. - */ - p0.l = lo(EVT15); - p0.h = hi(EVT15); - p1.l = _evt_system_call; - p1.h = _evt_system_call; - [p0] = p1; - csync; - p0.l = 1f; - p0.h = 1f; - [sp + PT_RESERVED] = P0; - call .Lresume_userspace; -1: - RESTORE_CONTEXT - rti; -ENDPROC(_schedule_and_signal) - -/* We handle this 100% in exception space - to reduce overhead - * Only potiential problem is if the software buffer gets swapped out of the - * CPLB table - then double fault. - so we don't let this happen in other places - */ -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND -ENTRY(_ex_trace_buff_full) - [--sp] = P3; - [--sp] = P2; - [--sp] = LC0; - [--sp] = LT0; - [--sp] = LB0; - P5.L = _trace_buff_offset; - P5.H = _trace_buff_offset; - P3 = [P5]; /* trace_buff_offset */ - P5.L = lo(TBUFSTAT); - P5.H = hi(TBUFSTAT); - R7 = [P5]; - R7 <<= 1; /* double, since we need to read twice */ - LC0 = R7; - R7 <<= 2; /* need to shift over again, - * to get the number of bytes */ - P5.L = lo(TBUF); - P5.H = hi(TBUF); - R6 = ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*1024) - 1; - - P2 = R7; - P3 = P3 + P2; - R7 = P3; - R7 = R7 & R6; - P3 = R7; - P2.L = _trace_buff_offset; - P2.H = _trace_buff_offset; - [P2] = P3; - - P2.L = _software_trace_buff; - P2.H = _software_trace_buff; - - LSETUP (.Lstart, .Lend) LC0; -.Lstart: - R7 = [P5]; /* read TBUF */ - P4 = P3 + P2; - [P4] = R7; - P3 += -4; - R7 = P3; - R7 = R7 & R6; -.Lend: - P3 = R7; - - LB0 = [sp++]; - LT0 = [sp++]; - LC0 = [sp++]; - P2 = [sp++]; - P3 = [sp++]; - jump _bfin_return_from_exception; -ENDPROC(_ex_trace_buff_full) - -#if CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN == 4 -.data -#else -.section .l1.data.B -#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN */ -ENTRY(_trace_buff_offset) - .long 0; -ALIGN -ENTRY(_software_trace_buff) - .rept ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*256); - .long 0 - .endr -#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */ - -#ifdef CONFIG_EARLY_PRINTK -__INIT -ENTRY(_early_trap) - SAVE_ALL_SYS - trace_buffer_stop(p0,r0); - - ANOMALY_283_315_WORKAROUND(p4, r5) - - /* Turn caches off, to ensure we don't get double exceptions */ - - P4.L = LO(IMEM_CONTROL); - P4.H = HI(IMEM_CONTROL); - - R5 = [P4]; /* Control Register*/ - BITCLR(R5,ENICPLB_P); - CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ - [P4] = R5; - SSYNC; - - P4.L = LO(DMEM_CONTROL); - P4.H = HI(DMEM_CONTROL); - R5 = [P4]; - BITCLR(R5,ENDCPLB_P); - CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */ - [P4] = R5; - SSYNC; - - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - r1 = RETX; - - SP += -12; - call _early_trap_c; - SP += 12; -ENDPROC(_early_trap) -__FINIT -#endif /* CONFIG_EARLY_PRINTK */ - -/* - * Put these in the kernel data section - that should always be covered by - * a CPLB. This is needed to ensure we don't get double fault conditions - */ - -#ifdef CONFIG_SYSCALL_TAB_L1 -.section .l1.data -#else -.data -#endif - -ENTRY(_ex_table) - /* entry for each EXCAUSE[5:0] - * This table must be in sync with the table in ./kernel/traps.c - * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined - */ - .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */ - .long _ex_trap_c /* 0x01 - User Defined - Software breakpoint */ -#ifdef CONFIG_KGDB - .long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection - and break signal trap */ -#else - .long _ex_replaceable /* 0x02 - User Defined */ -#endif - .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */ - .long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */ - .long _ex_replaceable /* 0x05 - User Defined */ - .long _ex_replaceable /* 0x06 - User Defined */ - .long _ex_replaceable /* 0x07 - User Defined */ - .long _ex_replaceable /* 0x08 - User Defined */ - .long _ex_replaceable /* 0x09 - User Defined */ - .long _ex_replaceable /* 0x0A - User Defined */ - .long _ex_replaceable /* 0x0B - User Defined */ - .long _ex_replaceable /* 0x0C - User Defined */ - .long _ex_replaceable /* 0x0D - User Defined */ - .long _ex_replaceable /* 0x0E - User Defined */ - .long _ex_replaceable /* 0x0F - User Defined */ - .long _ex_single_step /* 0x10 - HW Single step */ -#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND - .long _ex_trace_buff_full /* 0x11 - Trace Buffer Full */ -#else - .long _ex_trap_c /* 0x11 - Trace Buffer Full */ -#endif - .long _ex_trap_c /* 0x12 - Reserved */ - .long _ex_trap_c /* 0x13 - Reserved */ - .long _ex_trap_c /* 0x14 - Reserved */ - .long _ex_trap_c /* 0x15 - Reserved */ - .long _ex_trap_c /* 0x16 - Reserved */ - .long _ex_trap_c /* 0x17 - Reserved */ - .long _ex_trap_c /* 0x18 - Reserved */ - .long _ex_trap_c /* 0x19 - Reserved */ - .long _ex_trap_c /* 0x1A - Reserved */ - .long _ex_trap_c /* 0x1B - Reserved */ - .long _ex_trap_c /* 0x1C - Reserved */ - .long _ex_trap_c /* 0x1D - Reserved */ - .long _ex_trap_c /* 0x1E - Reserved */ - .long _ex_trap_c /* 0x1F - Reserved */ - .long _ex_trap_c /* 0x20 - Reserved */ - .long _ex_trap_c /* 0x21 - Undefined Instruction */ - .long _ex_trap_c /* 0x22 - Illegal Instruction Combination */ - .long _ex_dviol /* 0x23 - Data CPLB Protection Violation */ - .long _ex_trap_c /* 0x24 - Data access misaligned */ - .long _ex_trap_c /* 0x25 - Unrecoverable Event */ - .long _ex_dmiss /* 0x26 - Data CPLB Miss */ - .long _ex_dmult /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero */ - .long _ex_trap_c /* 0x28 - Emulation Watchpoint */ - .long _ex_trap_c /* 0x29 - Instruction fetch access error (535 only) */ - .long _ex_trap_c /* 0x2A - Instruction fetch misaligned */ - .long _ex_trap_c /* 0x2B - Instruction CPLB protection Violation */ - .long _ex_icplb_miss /* 0x2C - Instruction CPLB miss */ - .long _ex_trap_c /* 0x2D - Instruction CPLB Multiple Hits */ - .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */ - .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */ - .long _ex_trap_c /* 0x2F - Reserved */ - .long _ex_trap_c /* 0x30 - Reserved */ - .long _ex_trap_c /* 0x31 - Reserved */ - .long _ex_trap_c /* 0x32 - Reserved */ - .long _ex_trap_c /* 0x33 - Reserved */ - .long _ex_trap_c /* 0x34 - Reserved */ - .long _ex_trap_c /* 0x35 - Reserved */ - .long _ex_trap_c /* 0x36 - Reserved */ - .long _ex_trap_c /* 0x37 - Reserved */ - .long _ex_trap_c /* 0x38 - Reserved */ - .long _ex_trap_c /* 0x39 - Reserved */ - .long _ex_trap_c /* 0x3A - Reserved */ - .long _ex_trap_c /* 0x3B - Reserved */ - .long _ex_trap_c /* 0x3C - Reserved */ - .long _ex_trap_c /* 0x3D - Reserved */ - .long _ex_trap_c /* 0x3E - Reserved */ - .long _ex_trap_c /* 0x3F - Reserved */ -END(_ex_table) - -ENTRY(_sys_call_table) - .long _sys_restart_syscall /* 0 */ - .long _sys_exit - .long _sys_ni_syscall /* fork */ - .long _sys_read - .long _sys_write - .long _sys_open /* 5 */ - .long _sys_close - .long _sys_ni_syscall /* old waitpid */ - .long _sys_creat - .long _sys_link - .long _sys_unlink /* 10 */ - .long _sys_execve - .long _sys_chdir - .long _sys_time - .long _sys_mknod - .long _sys_chmod /* 15 */ - .long _sys_chown /* chown16 */ - .long _sys_ni_syscall /* old break syscall holder */ - .long _sys_ni_syscall /* old stat */ - .long _sys_lseek - .long _sys_getpid /* 20 */ - .long _sys_mount - .long _sys_ni_syscall /* old umount */ - .long _sys_setuid - .long _sys_getuid - .long _sys_stime /* 25 */ - .long _sys_ptrace - .long _sys_alarm - .long _sys_ni_syscall /* old fstat */ - .long _sys_pause - .long _sys_ni_syscall /* old utime */ /* 30 */ - .long _sys_ni_syscall /* old stty syscall holder */ - .long _sys_ni_syscall /* old gtty syscall holder */ - .long _sys_access - .long _sys_nice - .long _sys_ni_syscall /* 35 */ /* old ftime syscall holder */ - .long _sys_sync - .long _sys_kill - .long _sys_rename - .long _sys_mkdir - .long _sys_rmdir /* 40 */ - .long _sys_dup - .long _sys_pipe - .long _sys_times - .long _sys_ni_syscall /* old prof syscall holder */ - .long _sys_brk /* 45 */ - .long _sys_setgid - .long _sys_getgid - .long _sys_ni_syscall /* old sys_signal */ - .long _sys_geteuid /* geteuid16 */ - .long _sys_getegid /* getegid16 */ /* 50 */ - .long _sys_acct - .long _sys_umount /* recycled never used phys() */ - .long _sys_ni_syscall /* old lock syscall holder */ - .long _sys_ioctl - .long _sys_fcntl /* 55 */ - .long _sys_ni_syscall /* old mpx syscall holder */ - .long _sys_setpgid - .long _sys_ni_syscall /* old ulimit syscall holder */ - .long _sys_ni_syscall /* old old uname */ - .long _sys_umask /* 60 */ - .long _sys_chroot - .long _sys_ustat - .long _sys_dup2 - .long _sys_getppid - .long _sys_getpgrp /* 65 */ - .long _sys_setsid - .long _sys_ni_syscall /* old sys_sigaction */ - .long _sys_sgetmask - .long _sys_ssetmask - .long _sys_setreuid /* setreuid16 */ /* 70 */ - .long _sys_setregid /* setregid16 */ - .long _sys_ni_syscall /* old sys_sigsuspend */ - .long _sys_ni_syscall /* old sys_sigpending */ - .long _sys_sethostname - .long _sys_setrlimit /* 75 */ - .long _sys_ni_syscall /* old getrlimit */ - .long _sys_getrusage - .long _sys_gettimeofday - .long _sys_settimeofday - .long _sys_getgroups /* getgroups16 */ /* 80 */ - .long _sys_setgroups /* setgroups16 */ - .long _sys_ni_syscall /* old_select */ - .long _sys_symlink - .long _sys_ni_syscall /* old lstat */ - .long _sys_readlink /* 85 */ - .long _sys_uselib - .long _sys_ni_syscall /* sys_swapon */ - .long _sys_reboot - .long _sys_ni_syscall /* old_readdir */ - .long _sys_ni_syscall /* sys_mmap */ /* 90 */ - .long _sys_munmap - .long _sys_truncate - .long _sys_ftruncate - .long _sys_fchmod - .long _sys_fchown /* fchown16 */ /* 95 */ - .long _sys_getpriority - .long _sys_setpriority - .long _sys_ni_syscall /* old profil syscall holder */ - .long _sys_statfs - .long _sys_fstatfs /* 100 */ - .long _sys_ni_syscall - .long _sys_ni_syscall /* old sys_socketcall */ - .long _sys_syslog - .long _sys_setitimer - .long _sys_getitimer /* 105 */ - .long _sys_newstat - .long _sys_newlstat - .long _sys_newfstat - .long _sys_ni_syscall /* old uname */ - .long _sys_ni_syscall /* iopl for i386 */ /* 110 */ - .long _sys_vhangup - .long _sys_ni_syscall /* obsolete idle() syscall */ - .long _sys_ni_syscall /* vm86old for i386 */ - .long _sys_wait4 - .long _sys_ni_syscall /* 115 */ /* sys_swapoff */ - .long _sys_sysinfo - .long _sys_ni_syscall /* old sys_ipc */ - .long _sys_fsync - .long _sys_ni_syscall /* old sys_sigreturn */ - .long _bfin_clone /* 120 */ - .long _sys_setdomainname - .long _sys_newuname - .long _sys_ni_syscall /* old sys_modify_ldt */ - .long _sys_adjtimex - .long _sys_mprotect /* 125 */ - .long _sys_ni_syscall /* old sys_sigprocmask */ - .long _sys_ni_syscall /* old "creat_module" */ - .long _sys_init_module - .long _sys_delete_module - .long _sys_ni_syscall /* 130: old "get_kernel_syms" */ - .long _sys_quotactl - .long _sys_getpgid - .long _sys_fchdir - .long _sys_bdflush - .long _sys_ni_syscall /* 135 */ /* sys_sysfs */ - .long _sys_personality - .long _sys_ni_syscall /* for afs_syscall */ - .long _sys_setfsuid /* setfsuid16 */ - .long _sys_setfsgid /* setfsgid16 */ - .long _sys_llseek /* 140 */ - .long _sys_getdents - .long _sys_ni_syscall /* sys_select */ - .long _sys_flock - .long _sys_msync - .long _sys_readv /* 145 */ - .long _sys_writev - .long _sys_getsid - .long _sys_fdatasync - .long _sys_sysctl - .long _sys_mlock /* 150 */ - .long _sys_munlock - .long _sys_mlockall - .long _sys_munlockall - .long _sys_sched_setparam - .long _sys_sched_getparam /* 155 */ - .long _sys_sched_setscheduler - .long _sys_sched_getscheduler - .long _sys_sched_yield - .long _sys_sched_get_priority_max - .long _sys_sched_get_priority_min /* 160 */ - .long _sys_sched_rr_get_interval - .long _sys_nanosleep - .long _sys_mremap - .long _sys_setresuid /* setresuid16 */ - .long _sys_getresuid /* getresuid16 */ /* 165 */ - .long _sys_ni_syscall /* for vm86 */ - .long _sys_ni_syscall /* old "query_module" */ - .long _sys_ni_syscall /* sys_poll */ - .long _sys_ni_syscall /* old nfsservctl */ - .long _sys_setresgid /* setresgid16 */ /* 170 */ - .long _sys_getresgid /* getresgid16 */ - .long _sys_prctl - .long _sys_rt_sigreturn - .long _sys_rt_sigaction - .long _sys_rt_sigprocmask /* 175 */ - .long _sys_rt_sigpending - .long _sys_rt_sigtimedwait - .long _sys_rt_sigqueueinfo - .lo