From 6c3ff8b11a16ec69199ab85b74a5fae6d9c59db7 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 30 Oct 2013 18:21:09 -0700 Subject: ARM: Introduce CPU_METHOD_OF_DECLARE() for cpu hotplug/smp The goal of multi-platform kernels is to remove the need for mach directories and machine descriptors. To further that goal, introduce CPU_METHOD_OF_DECLARE() to allow cpu hotplug/smp support to be separated from the machine descriptors. Implementers should specify an enable-method property in their cpus node and then implement a matching set of smp_ops in their hotplug/smp code, wiring it up with the CPU_METHOD_OF_DECLARE() macro. When the kernel is compiled we'll collect all the enable-method smp_ops into one section for use at boot. At boot time we'll look for an enable-method in each cpu node and try to match that against all known CPU enable methods in the kernel. If there are no enable-methods in the cpu nodes we fallback to the cpus node and try to use any enable-method found there. If that doesn't work we fall back to the old way of using the machine descriptor. Acked-by: Mark Rutland Cc: Russell King Cc: Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala --- arch/arm/include/asm/smp.h | 9 +++++++++ arch/arm/kernel/devtree.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 22a3b9b5d4a1..772435b08207 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -114,6 +114,15 @@ struct smp_operations { #endif }; +struct of_cpu_method { + const char *method; + struct smp_operations *ops; +}; + +#define CPU_METHOD_OF_DECLARE(name, _method, _ops) \ + static const struct of_cpu_method __cpu_method_of_table_##name \ + __used __section(__cpu_method_of_table) \ + = { .method = _method, .ops = _ops } /* * set platform specific SMP operations */ diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index f751714d52c1..c7419a585ddc 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -63,6 +64,34 @@ void __init arm_dt_memblock_reserve(void) } } +#ifdef CONFIG_SMP +extern struct of_cpu_method __cpu_method_of_table_begin[]; +extern struct of_cpu_method __cpu_method_of_table_end[]; + +static int __init set_smp_ops_by_method(struct device_node *node) +{ + const char *method; + struct of_cpu_method *m = __cpu_method_of_table_begin; + + if (of_property_read_string(node, "enable-method", &method)) + return 0; + + for (; m < __cpu_method_of_table_end; m++) + if (!strcmp(m->method, method)) { + smp_set_ops(m->ops); + return 1; + } + + return 0; +} +#else +static inline int set_smp_ops_by_method(struct device_node *node) +{ + return 1; +} +#endif + + /* * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree * and builds the cpu logical map array containing MPIDR values related to @@ -79,6 +108,7 @@ void __init arm_dt_init_cpu_maps(void) * read as 0. */ struct device_node *cpu, *cpus; + int found_method = 0; u32 i, j, cpuidx = 1; u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; @@ -150,8 +180,18 @@ void __init arm_dt_init_cpu_maps(void) } tmp_map[i] = hwid; + + if (!found_method) + found_method = set_smp_ops_by_method(cpu); } + /* + * Fallback to an enable-method in the cpus node if nothing found in + * a cpu node. + */ + if (!found_method) + set_smp_ops_by_method(cpus); + if (!bootcpu_valid) { pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n"); return; -- cgit v1.2.3 From 188611af42648299a4785cfe6901cad9ed3ce629 Mon Sep 17 00:00:00 2001 From: Rohit Vaswani Date: Tue, 21 May 2013 19:13:29 -0700 Subject: ARM: qcom: Re-organize platsmp to make it extensible This makes it easy to add SMP support for new devices by keying on a device node for the release sequence. We add the enable-method property for the cpus property to specify that we want to use the gcc-msm8660 release sequence (which is going to look for the global clock controller device node to map some Scorpion specific power and control registers). We also remove the nr_cpus detection code as that is done generically in the DT CPU detection code. Signed-off-by: Rohit Vaswani [sboyd: Port to CPU_METHOD_OF_DECLARE] Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala --- arch/arm/mach-msm/common.h | 2 - arch/arm/mach-qcom/board.c | 14 ----- arch/arm/mach-qcom/platsmp.c | 118 ++++++++++++++++++++++++------------------- 3 files changed, 65 insertions(+), 69 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h index 0a4899b7d85c..572479a3c7be 100644 --- a/arch/arm/mach-msm/common.h +++ b/arch/arm/mach-msm/common.h @@ -23,8 +23,6 @@ extern void msm_map_qsd8x50_io(void); extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, unsigned int mtype, void *caller); -extern struct smp_operations msm_smp_ops; - struct msm_mmc_platform_data; extern void msm_add_devices(void); diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c index 830f69c3a3ce..bae617ef0b31 100644 --- a/arch/arm/mach-qcom/board.c +++ b/arch/arm/mach-qcom/board.c @@ -11,30 +11,16 @@ */ #include -#include -#include #include -#include - -extern struct smp_operations qcom_smp_ops; static const char * const qcom_dt_match[] __initconst = { "qcom,msm8660-surf", "qcom,msm8960-cdp", - NULL -}; - -static const char * const apq8074_dt_match[] __initconst = { "qcom,apq8074-dragonboard", NULL }; DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)") - .smp = smp_ops(qcom_smp_ops), .dt_compat = qcom_dt_match, MACHINE_END - -DT_MACHINE_START(APQ_DT, "Qualcomm (Flattened Device Tree)") - .dt_compat = apq8074_dt_match, -MACHINE_END diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c index 9c53ea70550d..ec8604d6dfb5 100644 --- a/arch/arm/mach-qcom/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c @@ -13,17 +13,18 @@ #include #include #include +#include +#include #include #include -#include #include #include "scm-boot.h" -#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 -#define SCSS_CPU1CORE_RESET 0xD80 -#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 +#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0 +#define SCSS_CPU1CORE_RESET 0x2d80 +#define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64 extern void secondary_startup(void); @@ -36,12 +37,6 @@ static void __ref qcom_cpu_die(unsigned int cpu) } #endif -static inline int get_core_count(void) -{ - /* 1 + the PART[1:0] field of MIDR */ - return ((read_cpuid_id() >> 4) & 3) + 1; -} - static void qcom_secondary_init(unsigned int cpu) { /* @@ -51,33 +46,41 @@ static void qcom_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -static void prepare_cold_cpu(unsigned int cpu) +static int scss_release_secondary(unsigned int cpu) { - int ret; - ret = scm_set_boot_addr(virt_to_phys(secondary_startup), - SCM_FLAG_COLDBOOT_CPU1); - if (ret == 0) { - void __iomem *sc1_base_ptr; - sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); - if (sc1_base_ptr) { - writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); - writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET); - writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP); - iounmap(sc1_base_ptr); - } - } else - printk(KERN_DEBUG "Failed to set secondary core boot " - "address\n"); + struct device_node *node; + void __iomem *base; + + node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660"); + if (!node) { + pr_err("%s: can't find node\n", __func__); + return -ENXIO; + } + + base = of_iomap(node, 0); + of_node_put(node); + if (!base) + return -ENOMEM; + + writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); + writel_relaxed(0, base + SCSS_CPU1CORE_RESET); + writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); + mb(); + iounmap(base); + + return 0; } -static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle) +static DEFINE_PER_CPU(int, cold_boot_done); + +static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int)) { - static int cold_boot_done; + int ret = 0; - /* Only need to bring cpu out of reset this way once */ - if (cold_boot_done == false) { - prepare_cold_cpu(cpu); - cold_boot_done = true; + if (!per_cpu(cold_boot_done, cpu)) { + ret = func(cpu); + if (!ret) + per_cpu(cold_boot_done, cpu) = true; } /* @@ -99,39 +102,48 @@ static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle) */ spin_unlock(&boot_lock); - return 0; + return ret; } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. The msm8x60 - * does not support the ARM SCU, so just set the possible cpu mask to - * NR_CPUS. - */ -static void __init qcom_smp_init_cpus(void) +static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle) { - unsigned int i, ncores = get_core_count(); - - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); + return qcom_boot_secondary(cpu, scss_release_secondary); } static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) { + int cpu, map; + unsigned int flags = 0; + static const int cold_boot_flags[] = { + 0, + SCM_FLAG_COLDBOOT_CPU1, + }; + + for_each_present_cpu(cpu) { + map = cpu_logical_map(cpu); + if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) { + set_cpu_present(cpu, false); + continue; + } + flags |= cold_boot_flags[map]; + } + + if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags)) { + for_each_present_cpu(cpu) { + if (cpu == smp_processor_id()) + continue; + set_cpu_present(cpu, false); + } + pr_warn("Failed to set CPU boot address, disabling SMP\n"); + } } -struct smp_operations qcom_smp_ops __initdata = { - .smp_init_cpus = qcom_smp_init_cpus, +static struct smp_operations smp_msm8660_ops __initdata = { .smp_prepare_cpus = qcom_smp_prepare_cpus, .smp_secondary_init = qcom_secondary_init, - .smp_boot_secondary = qcom_boot_secondary, + .smp_boot_secondary = msm8660_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = qcom_cpu_die, #endif }; +CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops); -- cgit v1.2.3 From 6267809f1660cdd72fbb1032ab566facb12a3193 Mon Sep 17 00:00:00 2001 From: Rohit Vaswani Date: Tue, 21 May 2013 19:13:50 -0700 Subject: ARM: qcom: Add SMP support for KPSSv1 Implement support for the Krait CPU release sequence when the CPUs are part of the first version of the krait processor subsystem. Signed-off-by: Rohit Vaswani Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala --- arch/arm/mach-qcom/platsmp.c | 106 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-qcom/scm-boot.h | 8 ++-- 2 files changed, 111 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c index ec8604d6dfb5..cb0783f3ed75 100644 --- a/arch/arm/mach-qcom/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c @@ -26,6 +26,16 @@ #define SCSS_CPU1CORE_RESET 0x2d80 #define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64 +#define APCS_CPU_PWR_CTL 0x04 +#define PLL_CLAMP BIT(8) +#define CORE_PWRD_UP BIT(7) +#define COREPOR_RST BIT(5) +#define CORE_RST BIT(4) +#define L2DT_SLP BIT(3) +#define CLAMP BIT(0) + +#define APCS_SAW2_VCTL 0x14 + extern void secondary_startup(void); static DEFINE_SPINLOCK(boot_lock); @@ -71,6 +81,85 @@ static int scss_release_secondary(unsigned int cpu) return 0; } +static int kpssv1_release_secondary(unsigned int cpu) +{ + int ret = 0; + void __iomem *reg, *saw_reg; + struct device_node *cpu_node, *acc_node, *saw_node; + u32 val; + + cpu_node = of_get_cpu_node(cpu, NULL); + if (!cpu_node) + return -ENODEV; + + acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); + if (!acc_node) { + ret = -ENODEV; + goto out_acc; + } + + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + if (!saw_node) { + ret = -ENODEV; + goto out_saw; + } + + reg = of_iomap(acc_node, 0); + if (!reg) { + ret = -ENOMEM; + goto out_acc_map; + } + + saw_reg = of_iomap(saw_node, 0); + if (!saw_reg) { + ret = -ENOMEM; + goto out_saw_map; + } + + /* Turn on CPU rail */ + writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); + mb(); + udelay(512); + + /* Krait bring-up sequence */ + val = PLL_CLAMP | L2DT_SLP | CLAMP; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + val &= ~L2DT_SLP; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + ndelay(300); + + val |= COREPOR_RST; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(2); + + val &= ~CLAMP; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(2); + + val &= ~COREPOR_RST; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(100); + + val |= CORE_PWRD_UP; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + + iounmap(saw_reg); +out_saw_map: + iounmap(reg); +out_acc_map: + of_node_put(saw_node); +out_saw: + of_node_put(acc_node); +out_acc: + of_node_put(cpu_node); + return ret; +} + static DEFINE_PER_CPU(int, cold_boot_done); static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int)) @@ -110,6 +199,11 @@ static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle) return qcom_boot_secondary(cpu, scss_release_secondary); } +static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + return qcom_boot_secondary(cpu, kpssv1_release_secondary); +} + static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) { int cpu, map; @@ -117,6 +211,8 @@ static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) static const int cold_boot_flags[] = { 0, SCM_FLAG_COLDBOOT_CPU1, + SCM_FLAG_COLDBOOT_CPU2, + SCM_FLAG_COLDBOOT_CPU3, }; for_each_present_cpu(cpu) { @@ -147,3 +243,13 @@ static struct smp_operations smp_msm8660_ops __initdata = { #endif }; CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops); + +static struct smp_operations qcom_smp_kpssv1_ops __initdata = { + .smp_prepare_cpus = qcom_smp_prepare_cpus, + .smp_secondary_init = qcom_secondary_init, + .smp_boot_secondary = kpssv1_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = qcom_cpu_die, +#endif +}; +CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops); diff --git a/arch/arm/mach-qcom/scm-boot.h b/arch/arm/mach-qcom/scm-boot.h index 7be32ff5d687..6aabb2428176 100644 --- a/arch/arm/mach-qcom/scm-boot.h +++ b/arch/arm/mach-qcom/scm-boot.h @@ -13,9 +13,11 @@ #define __MACH_SCM_BOOT_H #define SCM_BOOT_ADDR 0x1 -#define SCM_FLAG_COLDBOOT_CPU1 0x1 -#define SCM_FLAG_WARMBOOT_CPU1 0x2 -#define SCM_FLAG_WARMBOOT_CPU0 0x4 +#define SCM_FLAG_COLDBOOT_CPU1 0x01 +#define SCM_FLAG_COLDBOOT_CPU2 0x08 +#define SCM_FLAG_COLDBOOT_CPU3 0x20 +#define SCM_FLAG_WARMBOOT_CPU0 0x04 +#define SCM_FLAG_WARMBOOT_CPU1 0x02 int scm_set_boot_addr(phys_addr_t addr, int flags); -- cgit v1.2.3 From 6990c132abc984bd6e75ac2be1f1d657cd600f63 Mon Sep 17 00:00:00 2001 From: Rohit Vaswani Date: Fri, 21 Jun 2013 17:09:13 -0700 Subject: ARM: qcom: Add SMP support for KPSSv2 Implement support for the Krait CPU release sequence when the CPUs are part of the second version of the Krait processor subsystem. Signed-off-by: Rohit Vaswani Signed-off-by: Stephen Boyd Signed-off-by: Kumar Gala --- arch/arm/mach-qcom/platsmp.c | 123 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c index cb0783f3ed75..d6908569ecaf 100644 --- a/arch/arm/mach-qcom/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c @@ -34,7 +34,15 @@ #define L2DT_SLP BIT(3) #define CLAMP BIT(0) +#define APC_PWR_GATE_CTL 0x14 +#define BHS_CNT_SHIFT 24 +#define LDO_PWR_DWN_SHIFT 16 +#define LDO_BYP_SHIFT 8 +#define BHS_SEG_SHIFT 1 +#define BHS_EN BIT(0) + #define APCS_SAW2_VCTL 0x14 +#define APCS_SAW2_2_VCTL 0x1c extern void secondary_startup(void); @@ -160,6 +168,106 @@ out_acc: return ret; } +static int kpssv2_release_secondary(unsigned int cpu) +{ + void __iomem *reg; + struct device_node *cpu_node, *l2_node, *acc_node, *saw_node; + void __iomem *l2_saw_base; + unsigned reg_val; + int ret; + + cpu_node = of_get_cpu_node(cpu, NULL); + if (!cpu_node) + return -ENODEV; + + acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); + if (!acc_node) { + ret = -ENODEV; + goto out_acc; + } + + l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0); + if (!l2_node) { + ret = -ENODEV; + goto out_l2; + } + + saw_node = of_parse_phandle(l2_node, "qcom,saw", 0); + if (!saw_node) { + ret = -ENODEV; + goto out_saw; + } + + reg = of_iomap(acc_node, 0); + if (!reg) { + ret = -ENOMEM; + goto out_map; + } + + l2_saw_base = of_iomap(saw_node, 0); + if (!l2_saw_base) { + ret = -ENOMEM; + goto out_saw_map; + } + + /* Turn on the BHS, turn off LDO Bypass and power down LDO */ + reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN; + writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); + mb(); + /* wait for the BHS to settle */ + udelay(1); + + /* Turn on BHS segments */ + reg_val |= 0x3f << BHS_SEG_SHIFT; + writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); + mb(); + /* wait for the BHS to settle */ + udelay(1); + + /* Finally turn on the bypass so that BHS supplies power */ + reg_val |= 0x3f << LDO_BYP_SHIFT; + writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); + + /* enable max phases */ + writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL); + mb(); + udelay(50); + + reg_val = COREPOR_RST | CLAMP; + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(2); + + reg_val &= ~CLAMP; + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(2); + + reg_val &= ~COREPOR_RST; + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); + mb(); + + reg_val |= CORE_PWRD_UP; + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); + mb(); + + ret = 0; + + iounmap(l2_saw_base); +out_saw_map: + iounmap(reg); +out_map: + of_node_put(saw_node); +out_saw: + of_node_put(l2_node); +out_l2: + of_node_put(acc_node); +out_acc: + of_node_put(cpu_node); + + return ret; +} + static DEFINE_PER_CPU(int, cold_boot_done); static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int)) @@ -204,6 +312,11 @@ static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle) return qcom_boot_secondary(cpu, kpssv1_release_secondary); } +static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + return qcom_boot_secondary(cpu, kpssv2_release_secondary); +} + static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) { int cpu, map; @@ -253,3 +366,13 @@ static struct smp_operations qcom_smp_kpssv1_ops __initdata = { #endif }; CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops); + +static struct smp_operations qcom_smp_kpssv2_ops __initdata = { + .smp_prepare_cpus = qcom_smp_prepare_cpus, + .smp_secondary_init = qcom_secondary_init, + .smp_boot_secondary = kpssv2_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = qcom_cpu_die, +#endif +}; +CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops); -- cgit v1.2.3 From 5f809932419375af8203561a39c70ed1a994c877 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 11 Feb 2014 01:44:13 +0100 Subject: ARM: tegra: don't timeout if CPU is powergated When booting secondary CPU(s) which are not yet powergated, a wrong check lead to a timeout after 100 jiffies. With this patch, we only delay powergating if CPUs are still not powered yet. Signed-off-by: Stefan Agner Reviewed-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index eb72ae709124..929d1046e2b4 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -114,7 +114,7 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle) /* Wait for the power to come up. */ timeout = jiffies + msecs_to_jiffies(100); - while (tegra_pmc_cpu_is_powered(cpu)) { + while (!tegra_pmc_cpu_is_powered(cpu)) { if (time_after(jiffies, timeout)) return -ETIMEDOUT; udelay(10); -- cgit v1.2.3 From a553b7f536de9cf48cee7db410ff6c9108b67344 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 7 Feb 2014 13:35:01 +0900 Subject: ARM: trusted_foundations: fix vendor prefix typos of_register_trusted_foundations() and the firmware Kconfig used the wrong vendor prefix for Trusted Logic Mobility. Signed-off-by: Alexandre Courbot Acked-by: Olof Johansson Signed-off-by: Stephen Warren --- arch/arm/firmware/Kconfig | 2 +- arch/arm/include/asm/trusted_foundations.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig index bb00ccf00d66..bb126594995e 100644 --- a/arch/arm/firmware/Kconfig +++ b/arch/arm/firmware/Kconfig @@ -20,7 +20,7 @@ config TRUSTED_FOUNDATIONS This option allows the kernel to invoke the secure monitor whenever required on devices using Trusted Foundations. See arch/arm/include/asm/trusted_foundations.h or the - tl,trusted-foundations device tree binding documentation for details + tlm,trusted-foundations device tree binding documentation for details on how to use it. Say n if you don't know what this is about. diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h index 3bd36e2c5f2e..997862fd5d77 100644 --- a/arch/arm/include/asm/trusted_foundations.h +++ b/arch/arm/include/asm/trusted_foundations.h @@ -59,7 +59,7 @@ static inline void of_register_trusted_foundations(void) * If we find the target should enable TF but does not support it, * fail as the system won't be able to do much anyway */ - if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations")) + if (of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations")) register_trusted_foundations(NULL); } #endif /* CONFIG_TRUSTED_FOUNDATIONS */ -- cgit v1.2.3 From c3af6d68550c50597be25f29bc1cb742c10c63c0 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 7 Feb 2014 13:35:02 +0900 Subject: ARM: trusted_foundations: fallback when TF support is missing When Trusted Foundations is detected as present on the system, but Trusted Foundations support is not built into the kernel, the kernel used to issue a panic very early during boot, leaving little clue to the user as to what is going wrong. It turns out that even without TF support built-in, the kernel can boot on a TF-enabled system provided that SMP and cpuidle are disabled. This patch does this and continue booting on one CPU, leaving the user with a usable (however degraded) system. Signed-off-by: Alexandre Courbot Acked-by: Olof Johansson Signed-off-by: Stephen Warren --- arch/arm/include/asm/trusted_foundations.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h index 997862fd5d77..b5f7705abcb0 100644 --- a/arch/arm/include/asm/trusted_foundations.h +++ b/arch/arm/include/asm/trusted_foundations.h @@ -30,6 +30,8 @@ #include #include #include +#include +#include struct trusted_foundations_platform_data { unsigned int version_major; @@ -47,10 +49,13 @@ static inline void register_trusted_foundations( struct trusted_foundations_platform_data *pd) { /* - * If we try to register TF, this means the system needs it to continue. - * Its absence if thus a fatal error. + * If the system requires TF and we cannot provide it, continue booting + * but disable features that cannot be provided. */ - panic("No support for Trusted Foundations, stopping...\n"); + pr_err("No support for Trusted Foundations, continuing in degraded mode.\n"); + pr_err("Secondary processors as well as CPU PM will be disabled.\n"); + setup_max_cpus = 0; + cpu_idle_poll_ctrl(true); } static inline void of_register_trusted_foundations(void) -- cgit v1.2.3 From 5b154f18086f11096567aad55543af4bc44a0aa0 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 7 Feb 2014 13:35:03 +0900 Subject: ARM: firmware: enable Trusted Foundations by default As discussed previously (https://lkml.org/lkml/2013/11/26/289), enable Trusted Foundation support by default since it already depends on a supporting architecture being selected. Signed-off-by: Alexandre Courbot Acked-by: Olof Johansson Signed-off-by: Stephen Warren --- arch/arm/firmware/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig index bb126594995e..ad396af68e47 100644 --- a/arch/arm/firmware/Kconfig +++ b/arch/arm/firmware/Kconfig @@ -11,6 +11,7 @@ menu "Firmware options" config TRUSTED_FOUNDATIONS bool "Trusted Foundations secure monitor support" depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS + default y help Some devices (including most Tegra-based consumer devices on the market) are booted with the Trusted Foundations secure monitor -- cgit v1.2.3 From cd42145cd993fa1a7426d63648fc7e3423fb2e1d Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 7 Feb 2014 13:35:04 +0900 Subject: ARM: firmware: add prepare_idle() operation Some firmwares do not put the CPU into idle mode themselves, but still need to be informed that the CPU is about to enter idle mode before this happens. Add a prepare_idle() operation to the firmware_ops structure to handle such cases. Signed-off-by: Alexandre Courbot Acked-by: Olof Johansson Signed-off-by: Stephen Warren --- arch/arm/include/asm/firmware.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h index 15631300c238..2c9f10df7568 100644 --- a/arch/arm/include/asm/firmware.h +++ b/arch/arm/include/asm/firmware.h @@ -21,6 +21,10 @@ * A filled up structure can be registered with register_firmware_ops(). */ struct firmware_ops { + /* + * Inform the firmware we intend to enter CPU idle mode + */ + int (*prepare_idle)(void); /* * Enters CPU idle mode */ -- cgit v1.2.3 From b77b6e885c592815f272d70749fb8d391038f97a Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 7 Feb 2014 13:35:05 +0900 Subject: ARM: trusted_foundations: implement prepare_idle() Support the prepare_idle() firmware call, which is necessary to properly support CPU idling. Signed-off-by: Alexandre Courbot Acked-by: Olof Johansson Signed-off-by: Stephen Warren --- arch/arm/firmware/trusted_foundations.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index ef1e3d8f4af0..3fb1b5a1dce9 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -22,6 +22,15 @@ #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 +#define TF_CPU_PM 0xfffffffc +#define TF_CPU_PM_S3 0xffffffe3 +#define TF_CPU_PM_S2 0xffffffe6 +#define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5 +#define TF_CPU_PM_S1 0xffffffe4 +#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7 + +static unsigned long cpu_boot_addr; + static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) { asm volatile( @@ -41,13 +50,22 @@ static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) { - tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0); + cpu_boot_addr = boot_addr; + tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0); + + return 0; +} + +static int tf_prepare_idle(void) +{ + tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr); return 0; } static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, + .prepare_idle = tf_prepare_idle, }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd) -- cgit v1.2.3 From 338f2aadca7ed4e30e5937fdebc3ff72fda210b6 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 12 Feb 2014 11:43:44 +0900 Subject: ARM: tegra: cpuidle: use firmware for power down Attempt to invoke the prepare_idle() and do_idle() firmware calls to power down a CPU so an underlying firmware gets informed of the idle operation and performs it by itself if designed in such a way. Signed-off-by: Alexandre Courbot Acked-by: Olof Johansson Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/cpuidle-tegra114.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index e0b87300243d..b5fb7c110c64 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -45,7 +46,11 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev, clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); + call_firmware_op(prepare_idle); + + /* Do suspend by ourselves if the firmware does not implement it */ + if (call_firmware_op(do_idle) == -ENOSYS) + cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); -- cgit v1.2.3 From 3bff54740369d1cb45b308af8902ff62489606ea Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 21 Feb 2014 11:09:50 +0000 Subject: ARM: dts: msm: Add krait-pmu to platforms with Krait CPUs Allows us to probe the performance counters on Krait CPUs. Signed-off-by: Stephen Boyd Signed-off-by: Will Deacon [olof: Moved 8960 contents to the dtsi instead] Signed-off-by: Olof Johansson --- arch/arm/boot/dts/qcom-msm8960.dtsi | 6 ++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 5 +++++ 2 files changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index ff002826552a..3a9c3caa9aad 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -9,6 +9,12 @@ compatible = "qcom,msm8960"; interrupt-parent = <&intc>; + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + qcom,no-pc-write; + }; + intc: interrupt-controller@2000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 9e5dadb101eb..1eff4130cde0 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -9,6 +9,11 @@ compatible = "qcom,msm8974"; interrupt-parent = <&intc>; + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 7 0xf04>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 99b3d2946253713e8c7aa6544cb9474b0e226843 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 17 Feb 2014 15:23:19 +0100 Subject: ARM: mvebu: rename armada-370-xp.c to board-v7.c In preparation to the introduction of the support of Armada 375 and Armada 38x, this commit renames arch/arm/mach-mvebu/armada-370-xp.c to arch/arm/mach-mvebu/board-v7.c. The board-v7.c name as we expect this file to ultimately contain the DT_MACHINE_START definitions for all ARMv7 Marvell EBU platforms (370, 375, 38x, XP and Dove as of today). In relation to this file rename, this commit also: * Renames the hidden Kconfig symbol MACH_ARMADA_370_XP to MACH_MVEBU_V7. This hidden symbol is selected by the various per-SoC visible Kconfig options to trigger the build of board-v7.c. * Renames a certain number of functions in board-v7.c so that their armada_370_xp prefix is replaced by a mvebu prefix. The .dt_compat array keeps its armada_370_xp prefix because the new SOCs will be introduced with separate .dt_compat arrays, due to the need for different SMP operations. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 6 +-- arch/arm/mach-mvebu/Makefile | 5 +- arch/arm/mach-mvebu/armada-370-xp.c | 91 ------------------------------------- arch/arm/mach-mvebu/board-v7.c | 91 +++++++++++++++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 96 deletions(-) delete mode 100644 arch/arm/mach-mvebu/armada-370-xp.c create mode 100644 arch/arm/mach-mvebu/board-v7.c (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 5e269d7263ce..eac46054a0ef 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -21,7 +21,7 @@ if ARCH_MVEBU menu "Marvell SOC with device tree" -config MACH_ARMADA_370_XP +config MACH_MVEBU_V7 bool select ARMADA_370_XP_TIMER select HAVE_SMP @@ -31,7 +31,7 @@ config MACH_ARMADA_370_XP config MACH_ARMADA_370 bool "Marvell Armada 370 boards" select ARMADA_370_CLK - select MACH_ARMADA_370_XP + select MACH_MVEBU_V7 select PINCTRL_ARMADA_370 help Say 'Y' here if you want your kernel to support boards based @@ -40,7 +40,7 @@ config MACH_ARMADA_370 config MACH_ARMADA_XP bool "Marvell Armada XP boards" select ARMADA_XP_CLK - select MACH_ARMADA_370_XP + select MACH_MVEBU_V7 select PINCTRL_ARMADA_XP help Say 'Y' here if you want your kernel to support boards based diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index d99846103bbb..2c1db29db2ca 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -3,7 +3,8 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a -obj-y += coherency.o coherency_ll.o pmsu.o system-controller.o mvebu-soc-id.o -obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o +obj-y += system-controller.o mvebu-soc-id.o +obj-$(CONFIG_MACH_MVEBU_V7) += board-v7.o +obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c deleted file mode 100644 index 161cf2f54220..000000000000 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Device Tree support for Armada 370 and XP platforms. - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "armada-370-xp.h" -#include "common.h" -#include "coherency.h" -#include "mvebu-soc-id.h" - -static void __init armada_370_xp_timer_and_clk_init(void) -{ - of_clk_init(NULL); - clocksource_of_init(); - coherency_init(); - BUG_ON(mvebu_mbus_dt_init()); -#ifdef CONFIG_CACHE_L2X0 - l2x0_of_init(0, ~0UL); -#endif -} - -static void __init i2c_quirk(void) -{ - struct device_node *np; - u32 dev, rev; - - /* - * Only revisons more recent than A0 support the offload - * mechanism. We can exit only if we are sure that we can - * get the SoC revision and it is more recent than A0. - */ - if (mvebu_get_soc_id(&rev, &dev) == 0 && dev > MV78XX0_A0_REV) - return; - - for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") { - struct property *new_compat; - - new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL); - - new_compat->name = kstrdup("compatible", GFP_KERNEL); - new_compat->length = sizeof("marvell,mv78230-a0-i2c"); - new_compat->value = kstrdup("marvell,mv78230-a0-i2c", - GFP_KERNEL); - - of_update_property(np, new_compat); - } - return; -} - -static void __init armada_370_xp_dt_init(void) -{ - if (of_machine_is_compatible("plathome,openblocks-ax3-4")) - i2c_quirk(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static const char * const armada_370_xp_dt_compat[] = { - "marvell,armada-370-xp", - NULL, -}; - -DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") - .smp = smp_ops(armada_xp_smp_ops), - .init_machine = armada_370_xp_dt_init, - .init_time = armada_370_xp_timer_and_clk_init, - .restart = mvebu_restart, - .dt_compat = armada_370_xp_dt_compat, -MACHINE_END diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c new file mode 100644 index 000000000000..304f5f8b39f6 --- /dev/null +++ b/arch/arm/mach-mvebu/board-v7.c @@ -0,0 +1,91 @@ +/* + * Device Tree support for Armada 370 and XP platforms. + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "armada-370-xp.h" +#include "common.h" +#include "coherency.h" +#include "mvebu-soc-id.h" + +static void __init mvebu_timer_and_clk_init(void) +{ + of_clk_init(NULL); + clocksource_of_init(); + coherency_init(); + BUG_ON(mvebu_mbus_dt_init()); +#ifdef CONFIG_CACHE_L2X0 + l2x0_of_init(0, ~0UL); +#endif +} + +static void __init i2c_quirk(void) +{ + struct device_node *np; + u32 dev, rev; + + /* + * Only revisons more recent than A0 support the offload + * mechanism. We can exit only if we are sure that we can + * get the SoC revision and it is more recent than A0. + */ + if (mvebu_get_soc_id(&rev, &dev) == 0 && dev > MV78XX0_A0_REV) + return; + + for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") { + struct property *new_compat; + + new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL); + + new_compat->name = kstrdup("compatible", GFP_KERNEL); + new_compat->length = sizeof("marvell,mv78230-a0-i2c"); + new_compat->value = kstrdup("marvell,mv78230-a0-i2c", + GFP_KERNEL); + + of_update_property(np, new_compat); + } + return; +} + +static void __init mvebu_dt_init(void) +{ + if (of_machine_is_compatible("plathome,openblocks-ax3-4")) + i2c_quirk(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const armada_370_xp_dt_compat[] = { + "marvell,armada-370-xp", + NULL, +}; + +DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") + .smp = smp_ops(armada_xp_smp_ops), + .init_machine = mvebu_dt_init, + .init_time = mvebu_timer_and_clk_init, + .restart = mvebu_restart, + .dt_compat = armada_370_xp_dt_compat, +MACHINE_END -- cgit v1.2.3 From a017dbb6ee1b55a15ffffbc1aef0e782f96948c6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 17 Feb 2014 15:23:20 +0100 Subject: ARM: mvebu: rename DT machine structure for Armada 370/XP Due to a mistake made when merging Armada 370 and Armada XP DT machine structures, the name of the structure was incorrectly chosen as being ARMADA_XP_DT, while the structure also covers Armada 370. Therefore, we rename the structure to ARMADA_370_XP_DT. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/board-v7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c index 304f5f8b39f6..fa6fa2821f24 100644 --- a/arch/arm/mach-mvebu/board-v7.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -82,7 +82,7 @@ static const char * const armada_370_xp_dt_compat[] = { NULL, }; -DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") +DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)") .smp = smp_ops(armada_xp_smp_ops), .init_machine = mvebu_dt_init, .init_time = mvebu_timer_and_clk_init, -- cgit v1.2.3 From 798ec443ad30f1366ae6bff909eec77e8debffb4 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 17 Feb 2014 15:23:21 +0100 Subject: ARM: mvebu: make CPU_PJ4B selection a per-SoC choice Until now, the CPU_PJ4B Kconfig option was selected by MACH_ARMADA_MVEBU, i.e for all Armada MVEBU SOCs. In preparation to the introduction of Cortex-A9 based Armada MVEBU SOCs, this selection is moved down to the Armada 370 and Armada XP specific options. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index eac46054a0ef..d9d32aa077f8 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -26,11 +26,11 @@ config MACH_MVEBU_V7 select ARMADA_370_XP_TIMER select HAVE_SMP select CACHE_L2X0 - select CPU_PJ4B config MACH_ARMADA_370 bool "Marvell Armada 370 boards" select ARMADA_370_CLK + select CPU_PJ4B select MACH_MVEBU_V7 select PINCTRL_ARMADA_370 help @@ -40,6 +40,7 @@ config MACH_ARMADA_370 config MACH_ARMADA_XP bool "Marvell Armada XP boards" select ARMADA_XP_CLK + select CPU_PJ4B select MACH_MVEBU_V7 select PINCTRL_ARMADA_XP help -- cgit v1.2.3 From df863de19fc5a7b3a982a8204f9e2e8bb6e2d96d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 17 Feb 2014 15:23:22 +0100 Subject: ARM: mvebu: add Armada 375 support to the system-controller driver The system controller block in the Armada 375 has different register offsets for the system reset and other related functions. Therefore, this commit introduces the new "armada-375-system-controller" compatible string to identify the Armada 375 variant of the system controller. Signed-off-by: Thomas Petazzoni Reviewed-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/system-controller.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index e6e300afe836..614ba6832ff3 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -1,5 +1,5 @@ /* - * System controller support for Armada 370 and XP platforms. + * System controller support for Armada 370, 375 and XP platforms. * * Copyright (C) 2012 Marvell * @@ -11,7 +11,7 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. * - * The Armada 370 and Armada XP SoCs both have a range of + * The Armada 370, 375 and Armada XP SoCs have a range of * miscellaneous registers, that do not belong to a particular device, * but rather provide system-level features. This basic * system-controller driver provides a device tree binding for those @@ -47,6 +47,13 @@ static const struct mvebu_system_controller armada_370_xp_system_controller = { .system_soft_reset = 0x1, }; +static const struct mvebu_system_controller armada_375_system_controller = { + .rstoutn_mask_offset = 0x54, + .system_soft_reset_offset = 0x58, + .rstoutn_mask_reset_out_en = 0x1, + .system_soft_reset = 0x1, +}; + static const struct mvebu_system_controller orion_system_controller = { .rstoutn_mask_offset = 0x108, .system_soft_reset_offset = 0x10c, @@ -61,6 +68,9 @@ static const struct of_device_id of_system_controller_table[] = { }, { .compatible = "marvell,armada-370-xp-system-controller", .data = (void *) &armada_370_xp_system_controller, + }, { + .compatible = "marvell,armada-375-system-controller", + .data = (void *) &armada_375_system_controller, }, { /* end of list */ }, }; -- cgit v1.2.3 From d3ce7f2594ad57caf72250d948fde0e68ea5940e Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 17 Feb 2014 15:23:23 +0100 Subject: ARM: mvebu: add initial support for the Armada 375 SOCs This commit adds the basic support for the Armada 375 SOCs. These SoCs share most of their IP with the Armada 370/XP SoCs. The main difference is the use of a Cortex A9 CPU instead of the PJ4B CPU. The interrupt controller and the L2 cache controller are also different they are respectively the GIC and the PL310. The support is introduced in board-v7.c, together with Armada 370/XP, but a separate DT structure is added, because Armada 375 will need a different set of SMP operations when the SMP support is introduced. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 14 ++++++++++++++ arch/arm/mach-mvebu/board-v7.c | 11 +++++++++++ 2 files changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index d9d32aa077f8..3b74a8450947 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -37,6 +37,20 @@ config MACH_ARMADA_370 Say 'Y' here if you want your kernel to support boards based on the Marvell Armada 370 SoC with device tree. +config MACH_ARMADA_375 + bool "Marvell Armada 375 boards" + select ARM_ERRATA_720789 + select ARM_ERRATA_753970 + select ARM_GIC + select ARMADA_375_CLK + select CPU_V7 + select MACH_MVEBU_V7 + select NEON + select PINCTRL_ARMADA_375 + help + Say 'Y' here if you want your kernel to support boards based + on the Marvell Armada 375 SoC with device tree. + config MACH_ARMADA_XP bool "Marvell Armada XP boards" select ARMADA_XP_CLK diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c index fa6fa2821f24..a6234bfc1d69 100644 --- a/arch/arm/mach-mvebu/board-v7.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -89,3 +89,14 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)") .restart = mvebu_restart, .dt_compat = armada_370_xp_dt_compat, MACHINE_END + +static const char * const armada_375_dt_compat[] = { + "marvell,armada375", + NULL, +}; + +DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)") + .init_time = mvebu_timer_and_clk_init, + .restart = mvebu_restart, + .dt_compat = armada_375_dt_compat, +MACHINE_END -- cgit v1.2.3 From ca4a6f87150b2cec4feab2610ef7a0d6d7fcd800 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 17 Feb 2014 15:23:24 +0100 Subject: ARM: mvebu: add workaround for data abort issue on Armada 375 Early versions of Armada 375 SoC have a bug where the BootROM leaves an external data abort pending. The kernel is hit by this data abort as soon as it enters userspace, because it unmasks the data aborts at this moment. We register a custom abort handler below to ignore the first data abort to work around this problem. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/board-v7.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c index a6234bfc1d69..087668c7d46a 100644 --- a/arch/arm/mach-mvebu/board-v7.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -31,6 +31,27 @@ #include "coherency.h" #include "mvebu-soc-id.h" +/* + * Early versions of Armada 375 SoC have a bug where the BootROM + * leaves an external data abort pending. The kernel is hit by this + * data abort as soon as it enters userspace, because it unmasks the + * data aborts at this moment. We register a custom abort handler + * below to ignore the first data abort to work around this + * problem. + */ +static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + static int ignore_first; + + if (!ignore_first && fsr == 0x1406) { + ignore_first = 1; + return 0; + } + + return 1; +} + static void __init mvebu_timer_and_clk_init(void) { of_clk_init(NULL); @@ -40,6 +61,10 @@ static void __init mvebu_timer_and_clk_init(void) #ifdef CONFIG_CACHE_L2X0 l2x0_of_init(0, ~0UL); #endif + + if (of_machine_is_compatible("marvell,armada375")) + hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0, + "imprecise external abort"); } static void __init i2c_quirk(void) -- cgit v1.2.3 From 9aa30f1c13d1df2fc82ef0d0fd506306d8c8cef2 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 17 Feb 2014 15:23:27 +0100 Subject: ARM: mvebu: add initial support for the Armada 380/385 SOCs This commit adds the basic support for the Armada 380 and Armada 385 SOCs. These SoCs share most of their IP with the Armada 370/XP SoCs. The main difference is the use of a Cortex A9 CPU instead of the PJ4B CPU. The Armada 380 is a single core Cortex-A9, while the Armada 385 is a dual-core Cortex-A9. The support is introduced in board-v7.c, together with Armada 370/XP, but a separate DT structure is added, because Armada 38x will need a different set of SMP operations when the SMP support is introduced. Signed-off-by: Thomas Petazzoni Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 14 ++++++++++++++ arch/arm/mach-mvebu/board-v7.c | 12 ++++++++++++ 2 files changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 3b74a8450947..884b275ab056 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -51,6 +51,20 @@ config MACH_ARMADA_375 Say 'Y' here if you want your kernel to support boards based on the Marvell Armada 375 SoC with device tree. +config MACH_ARMADA_38X + bool "Marvell Armada 380/385 boards" + select ARM_ERRATA_720789 + select ARM_ERRATA_753970 + select ARM_GIC + select ARMADA_38X_CLK + select CPU_V7 + select MACH_MVEBU_V7 + select NEON + select PINCTRL_ARMADA_38X + help + Say 'Y' here if you want your kernel to support boards based + on the Marvell Armada 380/385 SoC with device tree. + config MACH_ARMADA_XP bool "Marvell Armada XP boards" select ARMADA_XP_CLK diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c index 087668c7d46a..746134ecdfc2 100644 --- a/arch/arm/mach-mvebu/board-v7.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -125,3 +125,15 @@ DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)") .restart = mvebu_restart, .dt_compat = armada_375_dt_compat, MACHINE_END + +static const char * const armada_38x_dt_compat[] = { + "marvell,armada380", + "marvell,armada385", + NULL, +}; + +DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)") + .init_time = mvebu_timer_and_clk_init, + .restart = mvebu_restart, + .dt_compat = armada_38x_dt_compat, +MACHINE_END -- cgit v1.2.3 From b92f10be479b3b63e753968a0c6cb3f605ad7142 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 20 Feb 2014 15:23:34 -0300 Subject: ARM: mvebu: Rename the ARCH_MVEBU menu option The previous name "Marvell SOCs with Device Tree support" is a bit ambiguous and not too informative for users. Instead, use a more appropriate name. Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 5e269d7263ce..1ba825ee3fe5 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -1,5 +1,5 @@ config ARCH_MVEBU - bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7 + bool "Marvell Engineering Business Unit (MVEBU) SoCs" if ARCH_MULTI_V7 select ARCH_SUPPORTS_BIG_ENDIAN select CLKSRC_MMIO select COMMON_CLK @@ -19,7 +19,7 @@ config ARCH_MVEBU if ARCH_MVEBU -menu "Marvell SOC with device tree" +menu "Marvell EBU SoC variants" config MACH_ARMADA_370_XP bool -- cgit v1.2.3 From c3b6144acb6b684bf1e9ae413e2f09825e314c61 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 22 Feb 2014 20:14:43 +0100 Subject: ARM: kirkwood: Give pm.c its own header file. The pm code needs to be separated from common.h in order to split DT and non-DT systems apart. Move the declarations into a header file of its own and include it where needed. Signed-off-by: Andrew Lunn Acked-by: Ezequiel Garcia Acked-by: Arnd Bergmann Tested-by: Jason Gunthorpe (on kirkwood) Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/board-dt.c | 1 + arch/arm/mach-kirkwood/common.c | 1 + arch/arm/mach-kirkwood/common.h | 6 ------ arch/arm/mach-kirkwood/pm.h | 26 ++++++++++++++++++++++++++ 4 files changed, 28 insertions(+), 6 deletions(-) create mode 100644 arch/arm/mach-kirkwood/pm.h (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 78188159484d..ceffdc8ffbbd 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -24,6 +24,7 @@ #include #include #include "common.h" +#include "pm.h" #define MV643XX_ETH_MAC_ADDR_LOW 0x0414 #define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f3407a5db216..52aca25432a7 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -36,6 +36,7 @@ #include #include #include "common.h" +#include "pm.h" /* These can go away once Kirkwood uses the mvebu-mbus DT binding */ #define KIRKWOOD_MBUS_NAND_TARGET 0x01 diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 05fd648df543..1296de94febf 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -58,12 +58,6 @@ void kirkwood_cpufreq_init(void); void kirkwood_restart(enum reboot_mode, const char *); void kirkwood_clk_init(void); -#ifdef CONFIG_PM -void kirkwood_pm_init(void); -#else -static inline void kirkwood_pm_init(void) {}; -#endif - /* board init functions for boards not fully converted to fdt */ #ifdef CONFIG_MACH_MV88F6281GTW_GE_DT void mv88f6281gtw_ge_init(void); diff --git a/arch/arm/mach-kirkwood/pm.h b/arch/arm/mach-kirkwood/pm.h new file mode 100644 index 000000000000..21e7530f368b --- /dev/null +++ b/arch/arm/mach-kirkwood/pm.h @@ -0,0 +1,26 @@ +/* + * Power Management driver for Marvell Kirkwood SoCs + * + * Copyright (C) 2013 Ezequiel Garcia + * Copyright (C) 2010 Simon Guinot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, + * version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_KIRKWOOD_PM_H +#define __ARCH_KIRKWOOD_PM_H + +#ifdef CONFIG_PM +void kirkwood_pm_init(void); +#else +static inline void kirkwood_pm_init(void) {}; +#endif + +#endif -- cgit v1.2.3 From e7c8f3808be854379c9784745663a55371cbf232 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 22 Feb 2014 20:14:45 +0100 Subject: ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT The mv88f6281gtw_ge has a ethernet switch connected to the ethernet port of the SoC. Convert the platform device instantiation to a DT instantiation. Signed-off-by: Andrew Lunn Acked-by: Arnd Bergmann Tested-by: Jason Gunthorpe Cc: florian@openwrt.org Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 62 ++++++++++++++++++++++++++ arch/arm/mach-kirkwood/Kconfig | 7 --- arch/arm/mach-kirkwood/Makefile | 1 - arch/arm/mach-kirkwood/board-dt.c | 3 -- arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c | 50 --------------------- arch/arm/mach-kirkwood/common.h | 7 --- 6 files changed, 62 insertions(+), 68 deletions(-) delete mode 100644 arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index dc86429756d7..2cb0dc529165 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -122,4 +122,66 @@ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0>; + dsa,mii-bus = <ðphy0>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0>; /* MDIO address 0, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@ff { + reg = <0xff>; /* No phy attached */ + speed = <1000>; + duplex = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; }; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index fe8319ad3158..df4b26340ae4 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -106,13 +106,6 @@ config ARCH_KIRKWOOD_DT Say 'Y' here if you want your kernel to support the Marvell Kirkwood using flattened device tree. -config MACH_MV88F6281GTW_GE_DT - bool "Marvell 88F6281 GTW GE Board (Flattened Device Tree)" - depends on ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Marvell 88F6281 GTW GE Board (Flattened Device Tree). - endmenu endif diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 144b51102939..dc22bf5b21ed 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -13,4 +13,3 @@ obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o -obj-$(CONFIG_MACH_MV88F6281GTW_GE_DT) += board-mv88f6281gtw_ge.o diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index ceffdc8ffbbd..e74b31aa9736 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -131,9 +131,6 @@ static void __init kirkwood_dt_init(void) kexec_reinit = kirkwood_enable_pcie; #endif - if (of_machine_is_compatible("marvell,mv88f6281gtw-ge")) - mv88f6281gtw_ge_init(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c b/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c deleted file mode 100644 index ee5eea678c11..000000000000 --- a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c - * - * Marvell 88F6281 GTW GE Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = { - .port_names[0] = "lan1", - .port_names[1] = "lan2", - .port_names[2] = "lan3", - .port_names[3] = "lan4", - .port_names[4] = "wan", - .port_names[5] = "cpu", -}; - -static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = { - .nr_chips = 1, - .chip = &mv88f6281gtw_ge_switch_chip_data, -}; - -void __init mv88f6281gtw_ge_init(void) -{ - kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data); - kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ); -} diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 1296de94febf..832a4e2ab8d7 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -58,13 +58,6 @@ void kirkwood_cpufreq_init(void); void kirkwood_restart(enum reboot_mode, const char *); void kirkwood_clk_init(void); -/* board init functions for boards not fully converted to fdt */ -#ifdef CONFIG_MACH_MV88F6281GTW_GE_DT -void mv88f6281gtw_ge_init(void); -#else -static inline void mv88f6281gtw_ge_init(void) {}; -#endif - /* early init functions not converted to fdt yet */ char *kirkwood_id(void); void kirkwood_l2_init(void); -- cgit v1.2.3 From 15a705ec849829be7866a989a52dbd56e498e760 Mon Sep 17 00:00:00 2001 From: Andrew Lunn