From 143b13d6e603abb0dc374cf31ec22f5dd28500eb Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 2 Jan 2014 22:05:04 +0100 Subject: ARM: sun4i: a10: Add missing serial aliases Some UART aliases have been defined, but not all of them. Add the remaining ones to be consistent and to ease the parsing of the DT by the bootloaders. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 040bb0eba152..28273f993677 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -19,6 +19,12 @@ ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; }; cpus { -- cgit v1.2.3 From 4dd4065f80ccd09e336388e7ff8e3a4a1dcf8e83 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 2 Jan 2014 22:05:04 +0100 Subject: ARM: sun5i: a10s: Add missing serial aliases Some UART aliases have been defined, but not all of them. Add the remaining ones to be consistent and to ease the parsing of the DT by the bootloaders. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index ea16054857a4..231808201efb 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -18,6 +18,10 @@ aliases { ethernet0 = &emac; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; }; cpus { -- cgit v1.2.3 From 54428d4025c2ce1f26bd6f677edaa7170a974787 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 2 Jan 2014 22:05:04 +0100 Subject: ARM: sun6i: Add missing serial aliases Some UART aliases have been defined, but not all of them. Add the remaining ones to be consistent and to ease the parsing of the DT by the bootloaders. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 5256ad9be52c..092bf97c3005 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -16,6 +16,16 @@ / { interrupt-parent = <&gic>; + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 4566b4beafe4582488907b84cb04e6c0efba384a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 2 Jan 2014 22:05:04 +0100 Subject: ARM: sun7i: Add missing serial aliases Some UART aliases have been defined, but not all of them. Add the remaining ones to be consistent and to ease the parsing of the DT by the bootloaders. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 119f066f0d98..b47685587eb0 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -18,6 +18,14 @@ aliases { ethernet0 = &emac; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; }; cpus { -- cgit v1.2.3 From 7f624cecb7f57f2687f0ae2267a7e886230d00bf Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Mon, 13 Jan 2014 14:15:01 +0100 Subject: ARM: sun4i: dt: Add basic board support for LinkSprite pcDuino This patch will add a basic board support DT for the LinkSprite pcDuino board. Signed-off-by: Zoltan HERPAI Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun4i-a10-pcduino.dts | 48 +++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 arch/arm/boot/dts/sun4i-a10-pcduino.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9d6a8b485e0..f5ee94352418 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -282,6 +282,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun4i-a10-cubieboard.dtb \ sun4i-a10-mini-xplus.dtb \ sun4i-a10-hackberry.dtb \ + sun4i-a10-pcduino.dtb \ sun5i-a10s-olinuxino-micro.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts new file mode 100644 index 000000000000..f5692a3b80db --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2014 Zoltan HERPAI + * Zoltan HERPAI + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun4i-a10.dtsi" + +/ { + model = "LinkSprite pcDuino"; + compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; + + soc@01c00000 { + emac: ethernet@01c0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; + }; + + mdio@01c0b080 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + }; +}; -- cgit v1.2.3 From 4261ec43b199a214f6b0ae5fefefff2e524f8977 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 14 Jan 2014 22:49:50 +0800 Subject: ARM: dts: sun7i: add pin muxing options for UART2 UART2 is used on CubieTruck to connect to the Bluetooth module. Add the pin set used in this case. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index b47685587eb0..bfb2cf283dbb 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -381,6 +381,13 @@ allwinner,pull = <0>; }; + uart2_pins_a: uart2@0 { + allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,function = "uart2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart6_pins_a: uart6@0 { allwinner,pins = "PI12", "PI13"; allwinner,function = "uart6"; -- cgit v1.2.3 From 0cc774ef2524ec54e9d2db8771ba3739cb8ebc99 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 13 Jan 2014 11:08:47 +0100 Subject: ARM: sun5i: a13: Add missing serial aliases Some UART aliases have been defined, but not all of them. Add the remaining ones to be consistent and to ease the parsing of the DT by the bootloaders. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 320335abfccd..6de40b6abff4 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -16,6 +16,11 @@ / { interrupt-parent = <&intc>; + aliases { + serial0 = &uart1; + serial1 = &uart3; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 3795e91d2abb25164dda5687ca680a7ab940c447 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Wed, 27 Nov 2013 12:16:24 -0800 Subject: arm: dt: zynq: Add fclk-enable property to clkc node Signed-off-by: Soren Brinkmann Acked-by: Michal Simek Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 8b67b19392ec..93d1980a755d 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -134,6 +134,7 @@ #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; ps-clk-frequency = <33333333>; + fclk-enable = <0>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", -- cgit v1.2.3 From 52e62f7f4b25d4f087395f805768e985e9d91bd0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 29 Dec 2013 22:41:56 +0100 Subject: ARM: shmobile: dts: Remove r8a7791-koelsch-reference.dts The dts file has been superseded by r8a7791-koelsch.dts and been removed from the ARCH_SHMOBILE_LEGACY dtb target. Remove it. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch-reference.dts | 115 ------------------------ 1 file changed, 115 deletions(-) delete mode 100644 arch/arm/boot/dts/r8a7791-koelsch-reference.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts deleted file mode 100644 index 588ca17ea1f0..000000000000 --- a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Device Tree Source for the Koelsch board - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include - -/ { - model = "Koelsch"; - compatible = "renesas,koelsch-reference", "renesas,r8a7791"; - - chosen { - bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = <30>; - label = "SW30"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = <48>; - label = "SW31"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = <46>; - label = "SW32"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = <32>; - label = "SW33"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = <18>; - label = "SW34"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = <33>; - label = "SW35"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = <34>; - label = "SW36"; - gpio-key,wakeup; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pfc { - pinctrl-0 = <&scif0_pins &scif1_pins>; - pinctrl-names = "default"; - - scif0_pins: serial0 { - renesas,groups = "scif0_data_d"; - renesas,function = "scif0"; - }; - - scif1_pins: serial1 { - renesas,groups = "scif1_data_d"; - renesas,function = "scif1"; - }; -}; -- cgit v1.2.3 From aff5274fdc5b53a44d906c39a834efa6ba9c30ef Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 19 Dec 2013 16:28:42 +0100 Subject: ARM: shmobile: Add GPIO keys to Koelsch DTS The Koelsh reference device tree is going away, copy the missing GPIO keys device node to the Koeslch device tree file. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 54 +++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index fd556c3483e3..c6f5de385940 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -31,6 +31,60 @@ #size-cells = <1>; }; + gpio-keys { + compatible = "gpio-keys"; + + key-a { + gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + linux,code = <30>; + label = "SW30"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = <48>; + label = "SW31"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; + linux,code = <46>; + label = "SW32"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-d { + gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; + linux,code = <32>; + label = "SW33"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-e { + gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + linux,code = <18>; + label = "SW34"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-f { + gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; + linux,code = <33>; + label = "SW35"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-g { + gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + linux,code = <34>; + label = "SW36"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; led6 { -- cgit v1.2.3 From 4cd1bad45182c7f1426353d73a481e0260d236b1 Mon Sep 17 00:00:00 2001 From: Takashi Yoshii Date: Sun, 22 Dec 2013 18:27:23 +0900 Subject: ARM: shmobile: koelsch: (1+1)GiB memory in DT Fix dts to have memory 1GiB @ 0_4000_0000 + 1GiB @ 2_0000_0000 according to Koelsch's hardware manual. Signed-off-by: Takashi Yoshii Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index c6f5de385940..d30527dee0c9 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -23,7 +23,12 @@ memory@40000000 { device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; }; lbsc { -- cgit v1.2.3 From 563bc8eb0243783afd7a71204ad696e8bdf44391 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 7 Jan 2014 19:57:13 +0100 Subject: ARM: shmobile: r8a7791: Add thermal clock in device tree Add the missing thermal MSTP clock to the thermal device node. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 19c65509a22d..34f5d39220e3 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -151,6 +151,7 @@ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupt-parent = <&gic>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; }; timer { -- cgit v1.2.3 From d3a439dbe3ff1610156c39cdffcc2c3257fadd62 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 7 Jan 2014 19:57:14 +0100 Subject: ARM: shmobile: r8a7790: Add thermal clock in device tree Add the missing thermal MSTP clock to the thermal device node. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 71b1251f79c7..96fc7313149c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -168,6 +168,7 @@ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupt-parent = <&gic>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; }; timer { -- cgit v1.2.3 From 9640cf259c9496d56bf44df8ae86f00f7b417ecc Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 14:14:22 +0100 Subject: ARM: shmobile: r8a7791: Add serial ports to the device tree Add all serial ports marked as disabled. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 180 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 34f5d39220e3..00ed0e0a9bcb 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -186,6 +186,186 @@ #gpio-range-cells = <3>; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupt-parent = <&gic>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + interrupt-parent = <&gic>; + reg = <0 0xe6c50000 0 64>; + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + interrupt-parent = <&gic>; + reg = <0 0xe6c60000 0 64>; + interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + interrupt-parent = <&gic>; + reg = <0 0xe6c70000 0 64>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + interrupt-parent = <&gic>; + reg = <0 0xe6c78000 0 64>; + interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7791", "renesas,scifa"; + interrupt-parent = <&gic>; + reg = <0 0xe6c80000 0 64>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7791", "renesas,scifb"; + interrupt-parent = <&gic>; + reg = <0 0xe6c20000 0 64>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7791", "renesas,scifb"; + interrupt-parent = <&gic>; + reg = <0 0xe6c30000 0 64>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7791", "renesas,scifb"; + interrupt-parent = <&gic>; + reg = <0 0xe6ce0000 0 64>; + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + interrupt-parent = <&gic>; + reg = <0 0xe6e60000 0 64>; + interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + interrupt-parent = <&gic>; + reg = <0 0xe6e68000 0 64>; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + interrupt-parent = <&gic>; + reg = <0 0xe6e58000 0 64>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + interrupt-parent = <&gic>; + reg = <0 0xe6ea8000 0 64>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + interrupt-parent = <&gic>; + reg = <0 0xe6ee0000 0 64>; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7791", "renesas,scif"; + interrupt-parent = <&gic>; + reg = <0 0xe6ee8000 0 64>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7791", "renesas,hscif"; + interrupt-parent = <&gic>; + reg = <0 0xe62c0000 0 96>; + interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7791", "renesas,hscif"; + interrupt-parent = <&gic>; + reg = <0 0xe62c8000 0 96>; + interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7791", "renesas,hscif"; + interrupt-parent = <&gic>; + reg = <0 0xe62d0000 0 96>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From 597af20fa8f810a26c84179a8ac58cb3fce6c102 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 29 Oct 2013 16:23:12 +0100 Subject: ARM: shmobile: r8a7790: Add serial ports to the device tree The platform code serial port instantiation mechanism is kept for the non-DT platforms only. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 100 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 96fc7313149c..15e2a97e5bdf 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -300,6 +300,106 @@ status = "disabled"; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic"; + reg = <0 0xe6c40000 0 64>; + interrupt-parent = <&gic>; + interrupts = <0 144 4>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic"; + interrupt-parent = <&gic>; + reg = <0 0xe6c50000 0 64>; + interrupts = <0 145 4>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic"; + interrupt-parent = <&gic>; + reg = <0 0xe6c60000 0 64>; + interrupts = <0 151 4>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic"; + interrupt-parent = <&gic>; + reg = <0 0xe6c20000 0 64>; + interrupts = <0 148 4>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic"; + interrupt-parent = <&gic>; + reg = <0 0xe6c30000 0 64>; + interrupts = <0 149 4>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic"; + interrupt-parent = <&gic>; + reg = <0 0xe6ce0000 0 64>; + interrupts = <0 150 4>; + clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7790", "renesas,scif-generic"; + interrupt-parent = <&gic>; + reg = <0 0xe6e60000 0 64>; + interrupts = <0 152 4>; + clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7790", "renesas,scif-generic"; + interrupt-parent = <&gic>; + reg = <0 0xe6e68000 0 64>; + interrupts = <0 153 4>; + clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic"; + interrupt-parent = <&gic>; + reg = <0 0xe62c0000 0 96>; + interrupts = <0 154 4>; + clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic"; + interrupt-parent = <&gic>; + reg = <0 0xe62c8000 0 96>; + interrupts = <0 155 4>; + clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From 3f2beaa9f2d7229c041975e40868dee2e3c4a598 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 7 Jan 2014 09:22:53 +0100 Subject: ARM: shmobile: r8a7790: Add VIN clocks to device tree Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 15e2a97e5bdf..9e4202c92819 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -708,10 +708,13 @@ mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&p_clk>; + clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>; #clock-cells = <1>; - renesas,clock-indices = ; - clock-output-names = "ether"; + renesas,clock-indices = < + R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 + R8A7790_CLK_VIN0 R8A7790_CLK_ETHER + >; + clock-output-names = "vin3", "vin2", "vin1", "vin0", "ether"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From 09c983463dd576d005c95dfdc0997f064629d321 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 7 Jan 2014 09:22:54 +0100 Subject: ARM: shmobile: r8a7791: Add VIN clocks to device tree Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 00ed0e0a9bcb..93c6f4d2866c 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -655,10 +655,13 @@ mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&p_clk>; + clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>; #clock-cells = <1>; - renesas,clock-indices = ; - clock-output-names = "ether"; + renesas,clock-indices = < + R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 + R8A7791_CLK_ETHER + >; + clock-output-names = "vin2", "vin1", "vin0", "ether"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From bccccc3d861567876a87441bc92f2e3b46cb38a9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 7 Jan 2014 09:22:55 +0100 Subject: ARM: shmobile: r8a7790: Add SATA clocks to device tree Signed-off-by: Laurent Pinchart Tested-by: Valentine Barshak Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 9e4202c92819..8cc68f78cd24 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -708,13 +708,16 @@ mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>; + clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, + <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 - R8A7790_CLK_VIN0 R8A7790_CLK_ETHER + R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 + R8A7790_CLK_SATA0 >; - clock-output-names = "vin3", "vin2", "vin1", "vin0", "ether"; + clock-output-names = + "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From 65f05c38749f393f775c360b9b247fa4d63b72de Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 7 Jan 2014 09:22:56 +0100 Subject: ARM: shmobile: r8a7791: Add SATA clocks to device tree Signed-off-by: Laurent Pinchart Tested-by: Valentine Barshak Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 93c6f4d2866c..94e3cc17448c 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -655,13 +655,15 @@ mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>; + clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 - R8A7791_CLK_ETHER + R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 >; - clock-output-names = "vin2", "vin1", "vin0", "ether"; + clock-output-names = + "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From b8532c699a163702bfcadaaa4c23c4ff71b67eec Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 14 Jan 2014 21:05:40 +0400 Subject: ARM: shmobile: r8a7791: Add SATA nodes to r8a7791.dtsi This adds SATA[01] device nodes to r8a7791.dtsi. Signed-off-by: Valentine Barshak Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 94e3cc17448c..d5cc3626dd60 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -366,6 +366,24 @@ status = "disabled"; }; + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7791"; + reg = <0 0xee300000 0 0x2000>; + interrupt-parent = <&gic>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_SATA0>; + status = "disabled"; + }; + + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7791"; + reg = <0 0xee500000 0 0x2000>; + interrupt-parent = <&gic>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7791_CLK_SATA1>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From 760c277b23973a3db181b2ae98d9a87f6e8f843e Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 14 Jan 2014 21:05:41 +0400 Subject: ARM: shmobile: koelsch: Enable SATA0 in r8a7791-koelsch.dts This enables SATA0 in Koelsch device tree. SATA1 is not available on Koelsch since its pinmux configuration is fixed to PCIe. Signed-off-by: Valentine Barshak Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index d30527dee0c9..74f098596b5c 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -122,3 +122,7 @@ renesas,function = "scif1"; }; }; + +&sata0 { + status = "okay"; +}; -- cgit v1.2.3 From cde630f763b07ff5d8ff7d34969f9dd05a2a4001 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 14 Jan 2014 21:05:30 +0400 Subject: ARM: shmobile: r8a7790: Add SATA nodes to r8a7790.dtsi This adds SATA[01] device nodes to r8a7790.dtsi Signed-off-by: Valentine Barshak Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 8cc68f78cd24..091492152911 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -400,6 +400,24 @@ status = "disabled"; }; + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7790"; + reg = <0 0xee300000 0 0x2000>; + interrupt-parent = <&gic>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_SATA0>; + status = "disabled"; + }; + + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7790"; + reg = <0 0xee500000 0 0x2000>; + interrupt-parent = <&gic>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_SATA1>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From c6181b9f06b0821e8d34e47174e044801f03edce Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 14 Jan 2014 21:05:31 +0400 Subject: ARM: shmobile: lager: Enable SATA1 in r8a7790-lager.dts This enables SATA1 in Lager device tree. SATA0 is not available on Lager since its pinmux is fixed to USB3.0. Signed-off-by: Valentine Barshak Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 57569cba1528..1081c5e91ac4 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -91,3 +91,7 @@ non-removable; status = "okay"; }; + +&sata1 { + status = "okay"; +}; -- cgit v1.2.3 From 59d2b5173bbe8dbc324e34263ceae4d6131058f2 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 21 Jan 2014 13:48:38 +0100 Subject: ARM: shmobile: r8a7790: Fix serial ports DT compatible strings Remove the -generic suffix that has been added by mistake from the serial port compatible strings. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 091492152911..51c897835628 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -301,7 +301,7 @@ }; scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic"; + compatible = "renesas,scifa-r8a7790", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupt-parent = <&gic>; interrupts = <0 144 4>; @@ -311,7 +311,7 @@ }; scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic"; + compatible = "renesas,scifa-r8a7790", "renesas,scifa"; interrupt-parent = <&gic>; reg = <0 0xe6c50000 0 64>; interrupts = <0 145 4>; @@ -321,7 +321,7 @@ }; scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic"; + compatible = "renesas,scifa-r8a7790", "renesas,scifa"; interrupt-parent = <&gic>; reg = <0 0xe6c60000 0 64>; interrupts = <0 151 4>; @@ -331,7 +331,7 @@ }; scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic"; + compatible = "renesas,scifb-r8a7790", "renesas,scifb"; interrupt-parent = <&gic>; reg = <0 0xe6c20000 0 64>; interrupts = <0 148 4>; @@ -341,7 +341,7 @@ }; scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic"; + compatible = "renesas,scifb-r8a7790", "renesas,scifb"; interrupt-parent = <&gic>; reg = <0 0xe6c30000 0 64>; interrupts = <0 149 4>; @@ -351,7 +351,7 @@ }; scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic"; + compatible = "renesas,scifb-r8a7790", "renesas,scifb"; interrupt-parent = <&gic>; reg = <0 0xe6ce0000 0 64>; interrupts = <0 150 4>; @@ -361,7 +361,7 @@ }; scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7790", "renesas,scif-generic"; + compatible = "renesas,scif-r8a7790", "renesas,scif"; interrupt-parent = <&gic>; reg = <0 0xe6e60000 0 64>; interrupts = <0 152 4>; @@ -371,7 +371,7 @@ }; scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7790", "renesas,scif-generic"; + compatible = "renesas,scif-r8a7790", "renesas,scif"; interrupt-parent = <&gic>; reg = <0 0xe6e68000 0 64>; interrupts = <0 153 4>; @@ -381,7 +381,7 @@ }; hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic"; + compatible = "renesas,hscif-r8a7790", "renesas,hscif"; interrupt-parent = <&gic>; reg = <0 0xe62c0000 0 96>; interrupts = <0 154 4>; @@ -391,7 +391,7 @@ }; hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic"; + compatible = "renesas,hscif-r8a7790", "renesas,hscif"; interrupt-parent = <&gic>; reg = <0 0xe62c8000 0 96>; interrupts = <0 155 4>; -- cgit v1.2.3 From 1f4c745b2c5a083c49dc11d2f0827d9a381f1ee1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 21 Jan 2014 13:48:39 +0100 Subject: ARM: shmobile: r8a7790: Replace IRQ type numerical values with macros Replace the hardcoded value 4 with IRQ_TYPE_LEVEL_HIGH. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 51c897835628..ba0ef9a864c8 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -304,7 +304,7 @@ compatible = "renesas,scifa-r8a7790", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupt-parent = <&gic>; - interrupts = <0 144 4>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; clock-names = "sci_ick"; status = "disabled"; @@ -314,7 +314,7 @@ compatible = "renesas,scifa-r8a7790", "renesas,scifa"; interrupt-parent = <&gic>; reg = <0 0xe6c50000 0 64>; - interrupts = <0 145 4>; + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; clock-names = "sci_ick"; status = "disabled"; @@ -324,7 +324,7 @@ compatible = "renesas,scifa-r8a7790", "renesas,scifa"; interrupt-parent = <&gic>; reg = <0 0xe6c60000 0 64>; - interrupts = <0 151 4>; + interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; clock-names = "sci_ick"; status = "disabled"; @@ -334,7 +334,7 @@ compatible = "renesas,scifb-r8a7790", "renesas,scifb"; interrupt-parent = <&gic>; reg = <0 0xe6c20000 0 64>; - interrupts = <0 148 4>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; clock-names = "sci_ick"; status = "disabled"; @@ -344,7 +344,7 @@ compatible = "renesas,scifb-r8a7790", "renesas,scifb"; interrupt-parent = <&gic>; reg = <0 0xe6c30000 0 64>; - interrupts = <0 149 4>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; clock-names = "sci_ick"; status = "disabled"; @@ -354,7 +354,7 @@ compatible = "renesas,scifb-r8a7790", "renesas,scifb"; interrupt-parent = <&gic>; reg = <0 0xe6ce0000 0 64>; - interrupts = <0 150 4>; + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; clock-names = "sci_ick"; status = "disabled"; @@ -364,7 +364,7 @@ compatible = "renesas,scif-r8a7790", "renesas,scif"; interrupt-parent = <&gic>; reg = <0 0xe6e60000 0 64>; - interrupts = <0 152 4>; + interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; clock-names = "sci_ick"; status = "disabled"; @@ -374,7 +374,7 @@ compatible = "renesas,scif-r8a7790", "renesas,scif"; interrupt-parent = <&gic>; reg = <0 0xe6e68000 0 64>; - interrupts = <0 153 4>; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; clock-names = "sci_ick"; status = "disabled"; @@ -384,7 +384,7 @@ compatible = "renesas,hscif-r8a7790", "renesas,hscif"; interrupt-parent = <&gic>; reg = <0 0xe62c0000 0 96>; - interrupts = <0 154 4>; + interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; clock-names = "sci_ick"; status = "disabled"; @@ -394,7 +394,7 @@ compatible = "renesas,hscif-r8a7790", "renesas,hscif"; interrupt-parent = <&gic>; reg = <0 0xe62c8000 0 96>; - interrupts = <0 155 4>; + interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; clock-names = "sci_ick"; status = "disabled"; -- cgit v1.2.3 From 8320062928161911bc46b0340e5a7cc0b3e3bb8e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 3 Feb 2014 14:32:20 +0100 Subject: ARM: ux500: move AB8500 GPIOs to device tree Move the AB8500 muxing and biasing settings over from the board file to the device tree, include it in the reference designs using the AB8500: HREF prior to v60, v60plus and Snowball. Set up these GPIO lines using hogs, just like in the board file. Cc: Patrice Chotard Cc: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-ab8500.dtsi | 253 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/ste-hrefprev60.dtsi | 1 + arch/arm/boot/dts/ste-hrefv60plus.dtsi | 1 + arch/arm/boot/dts/ste-snowball.dts | 1 + arch/arm/mach-ux500/board-mop500-pins.c | 79 ---------- 5 files changed, 256 insertions(+), 79 deletions(-) create mode 100644 arch/arm/boot/dts/ste-href-ab8500.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi new file mode 100644 index 000000000000..58b00d0f023e --- /dev/null +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -0,0 +1,253 @@ +/* + * Copyright 2014 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + soc { + prcmu@80157000 { + ab8500 { + ab8500-gpio { + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_default_mode>, + <&gpio4_default_mode>, + <&gpio10_default_mode>, + <&gpio11_default_mode>, + <&gpio12_default_mode>, + <&gpio13_default_mode>, + <&gpio16_default_mode>, + <&gpio24_default_mode>, + <&gpio25_default_mode>, + <&gpio36_default_mode>, + <&gpio37_default_mode>, + <&gpio38_default_mode>, + <&gpio39_default_mode>, + <&gpio42_default_mode>, + <&gpio26_default_mode>, + <&gpio35_default_mode>; + + /* + * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 + * are muxed in as GPIO, and configured as INPUT PULL DOWN + */ + gpio2 { + gpio2_default_mode: gpio2_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio2_a_1"; + }; + default_cfg { + ste,pins = "GPIO2_T9"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio4 { + gpio4_default_mode: gpio4_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio4_a_1"; + }; + default_cfg { + ste,pins = "GPIO4_W2"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio10 { + gpio10_default_mode: gpio10_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio10_d_1"; + }; + default_cfg { + ste,pins = "GPIO10_U17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio11 { + gpio11_default_mode: gpio11_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio11_d_1"; + }; + default_cfg { + ste,pins = "GPIO11_AA18"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio12 { + gpio12_default_mode: gpio12_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio12_d_1"; + }; + default_cfg { + ste,pins = "GPIO12_U16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio13 { + gpio13_default_mode: gpio13_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio13_d_1"; + }; + default_cfg { + ste,pins = "GPIO13_W17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio16 { + gpio16_default_mode: gpio16_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio16_a_1"; + }; + default_cfg { + ste,pins = "GPIO16_F15"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio24 { + gpio24_default_mode: gpio24_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio24_a_1"; + }; + default_cfg { + ste,pins = "GPIO24_T14"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio25 { + gpio25_default_mode: gpio25_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio25_a_1"; + }; + default_cfg { + ste,pins = "GPIO25_R16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio36 { + gpio36_default_mode: gpio36_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio36_a_1"; + }; + default_cfg { + ste,pins = "GPIO36_A17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio37 { + gpio37_default_mode: gpio37_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio37_a_1"; + }; + default_cfg { + ste,pins = "GPIO37_E15"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio38 { + gpio38_default_mode: gpio38_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio38_a_1"; + }; + default_cfg { + ste,pins = "GPIO38_C17"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio39 { + gpio39_default_mode: gpio39_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio39_a_1"; + }; + default_cfg { + ste,pins = "GPIO39_E16"; + input-enable; + bias-pull-down; + }; + }; + }; + gpio42 { + gpio42_default_mode: gpio42_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio42_a_1"; + }; + default_cfg { + ste,pins = "GPIO42_U2"; + input-enable; + bias-pull-down; + }; + }; + }; + /* + * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW + */ + gpio26 { + gpio26_default_mode: gpio26_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio26_d_1"; + }; + default_cfg { + ste,pins = "GPIO26_M16"; + output-low; + }; + }; + }; + gpio35 { + gpio35_default_mode: gpio35_default { + default_mux { + ste,function = "gpio"; + ste,pins = "gpio35_d_1"; + }; + default_cfg { + ste,pins = "GPIO35_W15"; + output-low; + }; + }; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index 40f0ecdf9303..abc762e24fcb 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -12,6 +12,7 @@ */ #include "ste-dbx5x0.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-href.dtsi" / { diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 3b6d1181939b..c2341061b943 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -10,6 +10,7 @@ */ #include "ste-dbx5x0.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-href.dtsi" / { diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 97d5d21b7db7..a2f632d0be2a 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "ste-dbx5x0.dtsi" +#include "ste-href-ab8500.dtsi" #include "ste-href-family-pinctrl.dtsi" / { diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index f63619b69113..139298043685 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -18,7 +18,6 @@ /* These simply sets bias for pins */ #define BIAS(a,b) static unsigned long a[] = { b } -BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); @@ -50,10 +49,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = { AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP), AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP), - /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */ - AB8500_MUX_HOG("gpio2_a_1", "gpio"), - AB8500_PIN_HOG("GPIO2_T9", in_pd), - /* Sysclkreq4 */ AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT), AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT), @@ -61,10 +56,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = { AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP), AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP), - /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */ - AB8500_MUX_HOG("gpio4_a_1", "gpio"), - AB8500_PIN_HOG("GPIO4_W2", in_pd), - /* * pins 6,7,8 and 9 are muxed in YCBCR0123 * configured in INPUT PULL UP @@ -75,22 +66,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = { AB8500_PIN_HOG("GPIO8_W18", in_nopull), AB8500_PIN_HOG("GPIO9_AA19", in_nopull), - /* - * pins 10,11,12 and 13 are muxed in GPIO - * configured in INPUT PULL DOWN - */ - AB8500_MUX_HOG("gpio10_d_1", "gpio"), - AB8500_PIN_HOG("GPIO10_U17", in_pd), - - AB8500_MUX_HOG("gpio11_d_1", "gpio"), - AB8500_PIN_HOG("GPIO11_AA18", in_pd), - - AB8500_MUX_HOG("gpio12_d_1", "gpio"), - AB8500_PIN_HOG("GPIO12_U16", in_pd), - - AB8500_MUX_HOG("gpio13_d_1", "gpio"), - AB8500_PIN_HOG("GPIO13_W17", in_pd), - /* * pins 14,15 are muxed in PWM1 and PWM2 * configured in INPUT PULL DOWN @@ -101,13 +76,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = { AB8500_MUX_HOG("pwmout2_d_1", "pwmout"), AB8500_PIN_HOG("GPIO15_B17", in_pd), - /* - * pins 16 is muxed in GPIO - * configured in INPUT PULL DOWN - */ - AB8500_MUX_HOG("gpio16_a_1", "gpio"), - AB8500_PIN_HOG("GPIO14_F14", in_pd), - /* * pins 17,18,19 and 20 are muxed in AUDIO interface 1 * configured in INPUT PULL DOWN @@ -127,23 +95,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = { AB8500_PIN_HOG("GPIO22_G20", in_pd), AB8500_PIN_HOG("GPIO23_G19", in_pd), - /* - * pins 24,25 are muxed in GPIO - * configured in INPUT PULL DOWN - */ - AB8500_MUX_HOG("gpio24_a_1", "gpio"), - AB8500_PIN_HOG("GPIO24_T14", in_pd), - - AB8500_MUX_HOG("gpio25_a_1", "gpio"), - AB8500_PIN_HOG("GPIO25_R16", in_pd), - - /* - * pins 26 is muxed in GPIO - * configured in OUTPUT LOW - */ - AB8500_MUX_HOG("gpio26_d_1", "gpio"), - AB8500_PIN_HOG("GPIO26_M16", out_lo), - /* * pins 27,28 are muxed in DMIC12 * configured in INPUT PULL DOWN @@ -175,29 +126,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = { AB8500_MUX_HOG("extcpena_d_1", "extcpena"), AB8500_PIN_HOG("GPIO34_R17", in_pd), - /* - * pins 35 is muxed in GPIO - * configured in OUTPUT LOW - */ - AB8500_MUX_HOG("gpio35_d_1", "gpio"), - AB8500_PIN_HOG("GPIO35_W15", in_pd), - - /* - * pins 36,37,38 and 39 are muxed in GPIO - * configured in INPUT PULL DOWN - */ - AB8500_MUX_HOG("gpio36_a_1", "gpio"), - AB8500_PIN_HOG("GPIO36_A17", in_pd), - - AB8500_MUX_HOG("gpio37_a_1", "gpio"), - AB8500_PIN_HOG("GPIO37_E15", in_pd), - - AB8500_MUX_HOG("gpio38_a_1", "gpio"), - AB8500_PIN_HOG("GPIO38_C17", in_pd), - - AB8500_MUX_HOG("gpio39_a_1", "gpio"), - AB8500_PIN_HOG("GPIO39_E16", in_pd), - /* * pins 40 and 41 are muxed in MODCSLSDA * configured INPUT PULL DOWN @@ -205,13 +133,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = { AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"), AB8500_PIN_HOG("GPIO40_T19", in_pd), AB8500_PIN_HOG("GPIO41_U19", in_pd), - - /* - * pins 42 is muxed in GPIO - * configured INPUT PULL DOWN - */ - AB8500_MUX_HOG("gpio42_a_1", "gpio"), - AB8500_PIN_HOG("GPIO42_U2", in_pd), }; static struct pinctrl_map __initdata ab8505_pinmap[] = { -- cgit v1.2.3 From fd385b33762620a48d098e0490b98782fe9d07a6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 3 Feb 2014 14:46:19 +0100 Subject: ARM: ux500: move AB8500 YCBCR settings to device tree This moves the pin control settings for the YCBCR connector on the AB8500 over to the device tree as a hog. Cc: Patrice Chotard Cc: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-ab8500.dtsi | 23 ++++++++++++++++++++++- arch/arm/mach-ux500/board-mop500-pins.c | 10 ---------- 2 files changed, 22 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi index 58b00d0f023e..2b548e90878e 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -31,7 +31,8 @@ <&gpio39_default_mode>, <&gpio42_default_mode>, <&gpio26_default_mode>, - <&gpio35_default_mode>; + <&gpio35_default_mode>, + <&ycbcr_default_mode>; /* * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 @@ -246,6 +247,26 @@ }; }; }; + /* + * This sets up the YCBCR connector pins, i.e. analog video out. + * Set as input with no bias. + */ + ycbcr { + ycbcr_default_mode: ycbcr_default { + default_mux { + ste,function = "ycbcr"; + ste,pins = "ycbcr0123_d_1"; + }; + default_cfg { + ste,pins = "GPIO6_Y18", + "GPIO7_AA20", + "GPIO8_W18", + "GPIO9_AA19"; + input-enable; + bias-disable; + }; + }; + }; }; }; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 139298043685..d58513b08a6d 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -56,16 +56,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = { AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP), AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP), - /* - * pins 6,7,8 and 9 are muxed in YCBCR0123 - * configured in INPUT PULL UP - */ - AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"), - AB8500_PIN_HOG("GPIO6_Y18", in_nopull), - AB8500_PIN_HOG("GPIO7_AA20", in_nopull), - AB8500_PIN_HOG("GPIO8_W18", in_nopull), - AB8500_PIN_HOG("GPIO9_AA19", in_nopull), - /* * pins 14,15 are muxed in PWM1 and PWM2 * configured in INPUT PULL DOWN -- cgit v1.2.3 From e2377c8107e33ac4ace7ec7ee86101d7c70fbbf9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 3 Feb 2014 14:57:22 +0100 Subject: ARM: ux500: move AB8500 PWM out settings to device tree This moves the muxing and biasing of the AB8500 PWM output pins over to the device tree for affected platforms. Cc: Patrice Chotard Cc: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-ab8500.dtsi | 18 +++++++++++++++++- arch/arm/mach-ux500/board-mop500-pins.c | 10 ---------- 2 files changed, 17 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi index 2b548e90878e..cdf2b3fd22dc 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -32,7 +32,8 @@ <&gpio42_default_mode>, <&gpio26_default_mode>, <&gpio35_default_mode>, - <&ycbcr_default_mode>; + <&ycbcr_default_mode>, + <&pwm_default_mode>; /* * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 @@ -267,6 +268,21 @@ }; }; }; + /* This sets up the PWM pins 14 and 15 */ + pwm { + pwm_default_mode: pwm_default { + default_mux { + ste,function = "pwmout"; + ste,pins = "pwmout1_d_1", "pwmout2_d_1"; + }; + default_cfg { + ste,pins = "GPIO14_F14", + "GPIO15_B17"; + input-enable; + bias-pull-down; + }; + }; + }; }; }; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index d58513b08a6d..b75089faf956 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -56,16 +56,6 @@ static struct pinctrl_map __initdata ab8500_pinmap[] = { AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP), AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP), - /* - * pins 14,15 are muxed in PWM1 and PWM2 - * configured in INPUT PULL DOWN - */ - AB8500_MUX_HOG("pwmout1_d_1", "pwmout"), - AB8500_PIN_HOG("GPIO14_F14", in_pd), - - AB8500_MUX_HOG("pwmout2_d_1", "pwmout"), - AB8500_PIN_HOG("GPIO15_B17", in_pd), - /* * pins 17,18,19 and 20 are muxed in AUDIO interface 1 * configured in INPUT PULL DOWN -- cgit v1.2.3 From b2985cf7f08325519405942770d203da8fd46fa8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 3 Feb 2014 15:43:22 +0100 Subject: ARM: ux500: move AB8500 audio interface 1 settings to DT This moves the pin muxing and configuration for audio interface one over to the device tree as a hog configuration. Cc: Patrice Chotard Cc: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-ab8500.dtsi | 20 +++++++++++++++++++- arch/arm/mach-ux500/board-mop500-pins.c | 10 ---------- 2 files changed, 19 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi index cdf2b3fd22dc..3aae4ec5bcc9 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -33,7 +33,8 @@ <&gpio26_default_mode>, <&gpio35_default_mode>, <&ycbcr_default_mode>, - <&pwm_default_mode>; + <&pwm_default_mode>, + <&adi1_default_mode>; /* * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42 @@ -283,6 +284,23 @@ }; }; }; + /* This sets up audio interface 1 */ + adi1 { + adi1_default_mode: adi1_default { + default_mux { + ste,function = "adi1"; + ste,pins = "adi1_d_1"; + }; + default_cfg { + ste,pins = "GPIO17_P5", + "GPIO18_R5", + "GP