From c842b8c4ff9859f750447f3ca08f64b2ed23cebc Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Sun, 1 Dec 2019 17:07:06 +0000 Subject: ARM: dts: am335x-sancloud-bbe: fix phy mode The phy mode should be rgmii-id. For some reason, it used to work with rgmii-txid but doesn't any more. Signed-off-by: Mans Rullgard Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sancloud-bbe.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts index 8678e6e35493..e5fdb7abb0d5 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts +++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts @@ -108,7 +108,7 @@ &cpsw_emac0 { phy-handle = <ðphy0>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii-id"; }; &i2c0 { -- cgit v1.2.3 From 90d79edc57a5625b9adaf397719e3a760b051167 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 4 Dec 2019 19:45:33 +0200 Subject: ARM: omap2plus_defconfig: enable NET_SWITCHDEV The TI_CPSW_SWITCHDEV definition in Kconfig was changed from "select NET_SWITCHDEV" to "depends on NET_SWITCHDEV", and therefore it is required to explicitelly enable NET_SWITCHDEV config option in omap2plus_defconfig. Fixes: 3727d259ddaf ("arm: omap2plus_defconfig: enable new cpsw switchdev driver") Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 8c37cc8ab6f2..15e1b2b2410c 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -92,6 +92,7 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NETFILTER=y CONFIG_PHONET=m +CONFIG_NET_SWITCHDEV=y CONFIG_CAN=m CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m @@ -181,6 +182,7 @@ CONFIG_SMSC911X=y # CONFIG_NET_VENDOR_STMICRO is not set CONFIG_TI_DAVINCI_EMAC=y CONFIG_TI_CPSW=y +CONFIG_TI_CPSW_SWITCHDEV=y CONFIG_TI_CPTS=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set @@ -556,4 +558,3 @@ CONFIG_DEBUG_INFO_DWARF4=y CONFIG_MAGIC_SYSRQ=y CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_TI_CPSW_SWITCHDEV=y -- cgit v1.2.3 From e00b59d30506dc9ef91caf2f3c584209cc9f61e4 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 9 Dec 2019 13:41:17 -0800 Subject: ARM: omap2plus_defconfig: Add back DEBUG_FS Commit 0e4a459f56c3 ("tracing: Remove unnecessary DEBUG_FS dependency") removed select for DEBUG_FS but we still need it at least for enabling deeper idle states for the SoCs. Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 15e1b2b2410c..c32c338f7704 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -556,5 +556,6 @@ CONFIG_DEBUG_INFO=y CONFIG_DEBUG_INFO_SPLIT=y CONFIG_DEBUG_INFO_DWARF4=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_BUGVERBOSE is not set -- cgit v1.2.3 From c6b16761c6908d3dc167a0a566578b4b0b972905 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 14 Nov 2019 11:39:48 +0200 Subject: ARM: dts: am437x-gp/epos-evm: fix panel compatible The LCD panel on AM4 GP EVMs and ePOS boards seems to be osd070t1718-19ts. The current dts files say osd057T0559-34ts. Possibly the panel has changed since the early EVMs, or there has been a mistake with the panel type. Update the DT files accordingly. Acked-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 2 +- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index cae4500194fe..811c8cae315b 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -86,7 +86,7 @@ }; lcd0: display { - compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; + compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; label = "lcd"; backlight = <&lcd_bl>; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 95314121d111..078cb473fa7d 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -42,7 +42,7 @@ }; lcd0: display { - compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; + compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; label = "lcd"; backlight = <&lcd_bl>; -- cgit v1.2.3 From 90bdfa0b05e3cc809a7c1aa3b1f162b46ea1b330 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: OMAP2+: Fix ti_sysc_find_one_clockdomain to check for to_clk_hw_omap We must bail out early if the clock is not hw_omap. Otherwise we will try to access invalid address with hwclk->clkdm_name: Unable to handle kernel paging request at virtual address ffffffff Internal error: Oops: 27 [#1] ARM ... (strcmp) from [] (clkdm_lookup+0x40/0x60) [] (clkdm_lookup) from [] (ti_sysc_clkdm_init+0x5c/0x64) [] (ti_sysc_clkdm_init) from [] (sysc_probe+0x948/0x117c) [] (sysc_probe) from [] (platform_drv_probe+0x48/0x98) ... Fixes: 2b2f7def058a ("bus: ti-sysc: Add support for missing clockdomain handling") Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pdata-quirks.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index ca52271de5a8..e95c224ffc4d 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -306,10 +306,14 @@ static void __init dra7x_evm_mmc_quirk(void) static struct clockdomain *ti_sysc_find_one_clockdomain(struct clk *clk) { + struct clk_hw *hw = __clk_get_hw(clk); struct clockdomain *clkdm = NULL; struct clk_hw_omap *hwclk; - hwclk = to_clk_hw_omap(__clk_get_hw(clk)); + hwclk = to_clk_hw_omap(hw); + if (!omap2_clk_is_hw_omap(hw)) + return NULL; + if (hwclk && hwclk->clkdm_name) clkdm = clkdm_lookup(hwclk->clkdm_name); -- cgit v1.2.3 From 65b5969e58de22cf9facac0dd8c772b018cc0b69 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: dts: Add generic compatible for omap sdma instances We need this to pass auxdata to all the sdma instances. Cc: devicetree@vger.kernel.org Cc: Aaro Koskinen Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 2 +- arch/arm/boot/dts/omap4-l4.dtsi | 2 +- arch/arm/boot/dts/omap5-l4.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 7e7aa101d8a4..55f42c8655c5 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -212,7 +212,7 @@ ranges = <0x0 0x56000 0x1000>; sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma"; + compatible = "ti,omap4430-sdma", "ti,omap-sdma"; reg = <0x0 0x1000>; interrupts = , , diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 83f803be8ee2..1219e5e9b506 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -160,7 +160,7 @@ ranges = <0x0 0x56000 0x1000>; sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma"; + compatible = "ti,omap4430-sdma", "ti,omap-sdma"; reg = <0x0 0x1000>; interrupts = , , diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 25aacf1ba708..a6493e818bdf 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -237,7 +237,7 @@ ranges = <0x0 0x56000 0x1000>; sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma"; + compatible = "ti,omap4430-sdma", "ti,omap-sdma"; reg = <0x0 0x1000>; interrupts = , , -- cgit v1.2.3 From eb6b38b26edf51ab8eb169ade49ff0ecd4d5a39b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: dts: Configure interconnect target module for omap2 sdma We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Note that we want to use separate compatible for omap2420 and omap2430 so let's do that here too while at it. Cc: devicetree@vger.kernel.org Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2.dtsi | 42 +++++++++++++++++++++++++++++++---------- arch/arm/boot/dts/omap2430.dtsi | 4 ++++ 2 files changed, 36 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 000bf16de651..6b1552d8c011 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include #include #include #include @@ -79,17 +80,38 @@ reg = <0x480FE000 0x1000>; }; - sdma: dma-controller@48056000 { - compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; + target-module@48056000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "dma"; - reg = <0x48056000 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <64>; + reg = <0x48056000 0x4>, + <0x4805602c 0x4>, + <0x48056028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,syss-mask = <1>; + clocks = <&core_l3_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48056000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap2420-sdma", "ti,omap-sdma"; + reg = <0 0x1000>; + interrupts = <12>, + <13>, + <14>, + <15>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <64>; + }; }; i2c1: i2c@48070000 { diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 7f57af2f10ac..15ef7593be12 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -309,6 +309,10 @@ }; }; +&sdma { + compatible = "ti,omap2430-sdma", "ti,omap-sdma"; +}; + &i2c1 { compatible = "ti,omap2430-i2c"; }; -- cgit v1.2.3 From bfab07ee52a257b14529264bea908ba0382328ac Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: dts: Configure interconnect target module for omap3 sdma We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Note that we want to use separate compatible for omap34xx and omap36xx so let's do that here too while at it. Cc: devicetree@vger.kernel.org Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n900.dts | 5 +++++ arch/arm/boot/dts/omap3.dtsi | 45 +++++++++++++++++++++++++++++++--------- arch/arm/boot/dts/omap36xx.dtsi | 4 ++++ 3 files changed, 44 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index a638e059135b..c3c6d7d04a76 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -482,6 +482,11 @@ regulator-always-on; }; +/* First two dma channels are reserved on secure omap3 */ +&sdma { + dma-channel-mask = <0xfffffffc>; +}; + &twl { twl_audio: audio { compatible = "ti,twl4030-audio"; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 5698a3e241aa..06d9108a8385 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -206,17 +206,42 @@ reg = <0x48200000 0x1000>; }; - sdma: dma-controller@48056000 { - compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; - reg = <0x48056000 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <96>; + target-module@48056000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "dma"; + reg = <0x48056000 0x4>, + <0x4805602c 0x4>, + <0x48056028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ + clocks = <&core_l3_ick>; + clock-names = "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48056000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap3430-sdma", "ti,omap-sdma"; + reg = <0x0 0x1000>; + interrupts = <12>, + <13>, + <14>, + <15>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <96>; + }; }; gpio1: gpio@48310000 { diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index c618cb257d00..71f3c8f1f924 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -223,6 +223,10 @@ }; }; +&sdma { + compatible = "ti,omap3630-sdma", "ti,omap-sdma"; +}; + /* OMAP3630 needs dss_96m_fck for VENC */ &venc { clocks = <&dss_tv_fck>, <&dss_96m_fck>; -- cgit v1.2.3 From 28b5afcd06d2b24e31ca4a643ddee9eb92b5bcb1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: OMAP2+: Drop unused sdma functions We still have lots of legacy code for sdma, but some of it is now unused. To simplify phasing out the old legacy sdma code, let's first remove all currently unused functions: omap_enable_dma_irq omap_set_dma_write_mode omap_set_dma_params omap_dma_link_lch omap_set_dma_callback omap_dma_set_global_params And with this, omap_dma_set_global_params now becomes static. Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dma.c | 149 +---------------------------------------------- 1 file changed, 1 insertion(+), 148 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 08c99413d02c..8f441f125ce1 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -65,8 +65,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; static struct omap_system_dma_plat_info *p; static struct omap_dma_dev_attr *d; static void omap_clear_dma(int lch); -static int omap_dma_set_prio_lch(int lch, unsigned char read_prio, - unsigned char write_prio); static int enable_1510_mode; static u32 errata; @@ -95,20 +93,6 @@ static struct dma_link_info *dma_linked_lch; #ifndef CONFIG_ARCH_OMAP1 /* Chain handling macros */ -#define OMAP_DMA_CHAIN_QINIT(chain_id) \ - do { \ - dma_linked_lch[chain_id].q_head = \ - dma_linked_lch[chain_id].q_tail = \ - dma_linked_lch[chain_id].q_count = 0; \ - } while (0) -#define OMAP_DMA_CHAIN_QFULL(chain_id) \ - (dma_linked_lch[chain_id].no_of_lchs_linked == \ - dma_linked_lch[chain_id].q_count) -#define OMAP_DMA_CHAIN_QLAST(chain_id) \ - do { \ - ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ - dma_linked_lch[chain_id].q_count) \ - } while (0) #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ (0 == dma_linked_lch[chain_id].q_count) #define __OMAP_DMA_CHAIN_INCQ(end) \ @@ -118,12 +102,6 @@ static struct dma_link_info *dma_linked_lch; __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ dma_linked_lch[chain_id].q_count--; \ } while (0) - -#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ - do { \ - __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ - dma_linked_lch[chain_id].q_count++; \ - } while (0) #endif static int dma_lch_count; @@ -137,9 +115,6 @@ static inline void disable_lnk(int lch); static void omap_disable_channel_irq(int lch); static inline void omap_enable_channel_irq(int lch); -#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ - __func__); - #ifdef CONFIG_ARCH_OMAP15XX /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ static int omap_dma_in_1510_mode(void) @@ -278,19 +253,6 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, } EXPORT_SYMBOL(omap_set_dma_transfer_params); -void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) -{ - if (dma_omap2plus()) { - u32 csdp; - - csdp = p->dma_read(CSDP, lch); - csdp &= ~(0x3 << 16); - csdp |= (mode << 16); - p->dma_write(csdp, CSDP, lch); - } -} -EXPORT_SYMBOL(omap_set_dma_write_mode); - void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) { if (dma_omap1() && !dma_omap15xx()) { @@ -332,25 +294,6 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode, } EXPORT_SYMBOL(omap_set_dma_src_params); -void omap_set_dma_params(int lch, struct omap_dma_channel_params *params) -{ - omap_set_dma_transfer_params(lch, params->data_type, - params->elem_count, params->frame_count, - params->sync_mode, params->trigger, - params->src_or_dst_synch); - omap_set_dma_src_params(lch, params->src_port, - params->src_amode, params->src_start, - params->src_ei, params->src_fi); - - omap_set_dma_dest_params(lch, params->dst_port, - params->dst_amode, params->dst_start, - params->dst_ei, params->dst_fi); - if (params->read_prio || params->write_prio) - omap_dma_set_prio_lch(lch, params->read_prio, - params->write_prio); -} -EXPORT_SYMBOL(omap_set_dma_params); - void omap_set_dma_src_data_pack(int lch, int enable) { u32 l; @@ -507,12 +450,6 @@ static inline void omap_disable_channel_irq(int lch) p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); } -void omap_enable_dma_irq(int lch, u16 bits) -{ - dma_chan[lch].enabled_irqs |= bits; -} -EXPORT_SYMBOL(omap_enable_dma_irq); - void omap_disable_dma_irq(int lch, u16 bits) { dma_chan[lch].enabled_irqs &= ~bits; @@ -721,7 +658,7 @@ EXPORT_SYMBOL(omap_free_dma); * DMA_THREAD_RESERVE_TWOT * DMA_THREAD_RESERVE_THREET */ -void +static void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) { u32 reg; @@ -742,39 +679,6 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) p->dma_write(reg, GCR, 0); } -EXPORT_SYMBOL(omap_dma_set_global_params); - -/** - * @brief omap_dma_set_prio_lch : Set channel wise priority settings - * - * @param lch - * @param read_prio - Read priority - * @param write_prio - Write priority - * Both of the above can be set with one of the following values : - * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW - */ -static int -omap_dma_set_prio_lch(int lch, unsigned char read_prio, - unsigned char write_prio) -{ - u32 l; - - if (unlikely((lch < 0 || lch >= dma_lch_count))) { - printk(KERN_ERR "Invalid channel id\n"); - return -EINVAL; - } - l = p->dma_read(CCR, lch); - l &= ~((1 << 6) | (1 << 26)); - if (d->dev_caps & IS_RW_PRIORITY) - l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); - else - l |= ((read_prio & 0x1) << 6); - - p->dma_write(l, CCR, lch); - - return 0; -} - /* * Clears any DMA state so the DMA engine is ready to restart with new buffers @@ -926,29 +830,6 @@ EXPORT_SYMBOL(omap_stop_dma); * Allows changing the DMA callback function or data. This may be needed if * the driver shares a single DMA channel for multiple dma triggers. */ -int omap_set_dma_callback(int lch, - void (*callback)(int lch, u16 ch_status, void *data), - void *data) -{ - unsigned long flags; - - if (lch < 0) - return -ENODEV; - - spin_lock_irqsave(&dma_chan_lock, flags); - if (dma_chan[lch].dev_id == -1) { - printk(KERN_ERR "DMA callback for not set for free channel\n"); - spin_unlock_irqrestore(&dma_chan_lock, flags); - return -EINVAL; - } - dma_chan[lch].callback = callback; - dma_chan[lch].data = data; - spin_unlock_irqrestore(&dma_chan_lock, flags); - - return 0; -} -EXPORT_SYMBOL(omap_set_dma_callback); - /* * Returns current physical source address for the given DMA channel. * If the channel is running the caller must disable interrupts prior calling @@ -1048,34 +929,6 @@ int omap_dma_running(void) return 0; } -/* - * lch_queue DMA will start right after lch_head one is finished. - * For this DMA link to start, you still need to start (see omap_start_dma) - * the first one. That will fire up the entire queue. - */ -void omap_dma_link_lch(int lch_head, int lch_queue) -{ - if (omap_dma_in_1510_mode()) { - if (lch_head == lch_queue) { - p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8), - CCR, lch_head); - return; - } - printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); - BUG(); - return; - } - - if ((dma_chan[lch_head].dev_id == -1) || - (dma_chan[lch_queue].dev_id == -1)) { - pr_err("omap_dma: trying to link non requested channels\n"); - dump_stack(); - } - - dma_chan[lch_head].next_lch = lch_queue; -} -EXPORT_SYMBOL(omap_dma_link_lch); - /*----------------------------------------------------------------------------*/ #ifdef CONFIG_ARCH_OMAP1 -- cgit v1.2.3 From 755cbfd8cf89c09e53be796d7d5c22f2d197ef1a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: OMAP2+: Drop sdma interrupt handling for mach-omap2 All device tree probing omap SoCs only have device drivers that are using Linux dmaengine API with the IRQENABLE_L1 interrupts. Only omap1 is still using old legacy dma. This means we can remove the legacy sdma interrupt handling for IRQENABLE_L0, and only rely on the dmaengine driver using IRQENABLE_L1. The legacy code still allocates the channels, but that will be deal with in the following patches. Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/dma.c | 3 - arch/arm/plat-omap/dma.c | 245 ++-------------------------------------------- 2 files changed, 8 insertions(+), 240 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 0c105baa5e88..c138703aab90 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -272,9 +272,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) d->dev_caps |= HS_CHANNELS_RESERVED; - if (platform_get_irq_byname(pdev, "0") < 0) - d->dev_caps |= DMA_ENGINE_HANDLE_IRQ; - /* Check the capabilities register for descriptor loading feature */ if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) dma_common_ch_end = CCDN; diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 8f441f125ce1..8aea155b10a8 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -88,22 +88,6 @@ struct dma_link_info { }; -static struct dma_link_info *dma_linked_lch; - -#ifndef CONFIG_ARCH_OMAP1 - -/* Chain handling macros */ -#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ - (0 == dma_linked_lch[chain_id].q_count) -#define __OMAP_DMA_CHAIN_INCQ(end) \ - ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) -#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ - do { \ - __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ - dma_linked_lch[chain_id].q_count--; \ - } while (0) -#endif - static int dma_lch_count; static int dma_chan_count; static int omap_dma_reserve_channels; @@ -469,12 +453,6 @@ static inline void enable_lnk(int lch) if (dma_chan[lch].next_lch != -1) l = dma_chan[lch].next_lch | (1 << 15); -#ifndef CONFIG_ARCH_OMAP1 - if (dma_omap2plus()) - if (dma_chan[lch].next_linked_ch != -1) - l = dma_chan[lch].next_linked_ch | (1 << 15); -#endif - p->dma_write(l, CLNK_CTRL, lch); } @@ -501,42 +479,6 @@ static inline void disable_lnk(int lch) dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; } -static inline void omap2_enable_irq_lch(int lch) -{ - u32 val; - unsigned long flags; - - if (dma_omap1()) - return; - - spin_lock_irqsave(&dma_chan_lock, flags); - /* clear IRQ STATUS */ - p->dma_write(1 << lch, IRQSTATUS_L0, lch); - /* Enable interrupt */ - val = p->dma_read(IRQENABLE_L0, lch); - val |= 1 << lch; - p->dma_write(val, IRQENABLE_L0, lch); - spin_unlock_irqrestore(&dma_chan_lock, flags); -} - -static inline void omap2_disable_irq_lch(int lch) -{ - u32 val; - unsigned long flags; - - if (dma_omap1()) - return; - - spin_lock_irqsave(&dma_chan_lock, flags); - /* Disable interrupt */ - val = p->dma_read(IRQENABLE_L0, lch); - val &= ~(1 << lch); - p->dma_write(val, IRQENABLE_L0, lch); - /* clear IRQ STATUS */ - p->dma_write(1 << lch, IRQSTATUS_L0, lch); - spin_unlock_irqrestore(&dma_chan_lock, flags); -} - int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch_out) @@ -565,9 +507,6 @@ int omap_request_dma(int dev_id, const char *dev_name, if (p->clear_lch_regs) p->clear_lch_regs(free_ch); - if (dma_omap2plus()) - omap_clear_dma(free_ch); - spin_unlock_irqrestore(&dma_chan_lock, flags); chan->dev_name = dev_name; @@ -575,20 +514,10 @@ int omap_request_dma(int dev_id, const char *dev_name, chan->data = data; chan->flags = 0; -#ifndef CONFIG_ARCH_OMAP1 - if (dma_omap2plus()) { - chan->chain_id = -1; - chan->next_linked_ch = -1; - } -#endif - chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; if (dma_omap1()) chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; - else if (dma_omap2plus()) - chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | - OMAP2_DMA_TRANS_ERR_IRQ; if (dma_omap16xx()) { /* If the sync device is set, configure it dynamically. */ @@ -605,11 +534,6 @@ int omap_request_dma(int dev_id, const char *dev_name, p->dma_write(dev_id, CCR, free_ch); } - if (dma_omap2plus()) { - omap_enable_channel_irq(free_ch); - omap2_enable_irq_lch(free_ch); - } - *dma_ch_out = free_ch; return 0; @@ -626,20 +550,12 @@ void omap_free_dma(int lch) return; } - /* Disable interrupt for logical channel */ - if (dma_omap2plus()) - omap2_disable_irq_lch(lch); - /* Disable all DMA interrupts for the channel. */ omap_disable_channel_irq(lch); /* Make sure the DMA transfer is stopped. */ p->dma_write(0, CCR, lch); - /* Clear registers */ - if (dma_omap2plus()) - omap_clear_dma(lch); - spin_lock_irqsave(&dma_chan_lock, flags); dma_chan[lch].dev_id = -1; dma_chan[lch].next_lch = -1; @@ -989,109 +905,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) #define omap1_dma_irq_handler NULL #endif -#ifdef CONFIG_ARCH_OMAP2PLUS - -static int omap2_dma_handle_ch(int ch) -{ - u32 status = p->dma_read(CSR, ch); - - if (!status) { - if (printk_ratelimit()) - pr_warn("Spurious DMA IRQ for lch %d\n", ch); - p->dma_write(1 << ch, IRQSTATUS_L0, ch); - return 0; - } - if (unlikely(dma_chan[ch].dev_id == -1)) { - if (printk_ratelimit()) - pr_warn("IRQ %04x for non-allocated DMA channel %d\n", - status, ch); - return 0; - } - if (unlikely(status & OMAP_DMA_DROP_IRQ)) - pr_info("DMA synchronization event drop occurred with device %d\n", - dma_chan[ch].dev_id); - if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { - printk(KERN_INFO "DMA transaction error with device %d\n", - dma_chan[ch].dev_id); - if (IS_DMA_ERRATA(DMA_ERRATA_i378)) { - u32 ccr; - - ccr = p->dma_read(CCR, ch); - ccr &= ~OMAP_DMA_CCR_EN; - p->dma_write(ccr, CCR, ch); - dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; - } - } - if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) - printk(KERN_INFO "DMA secure error with device %d\n", - dma_chan[ch].dev_id); - if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) - printk(KERN_INFO "DMA misaligned error with device %d\n", - dma_chan[ch].dev_id); - - p->dma_write(status, CSR, ch); - p->dma_write(1 << ch, IRQSTATUS_L0, ch); - /* read back the register to flush the write */ - p->dma_read(IRQSTATUS_L0, ch); - - /* If the ch is not chained then chain_id will be -1 */ - if (dma_chan[ch].chain_id != -1) { - int chain_id = dma_chan[ch].chain_id; - dma_chan[ch].state = DMA_CH_NOTSTARTED; - if (p->dma_read(CLNK_CTRL, ch) & (1 << 15)) - dma_chan[dma_chan[ch].next_linked_ch].state = - DMA_CH_STARTED; - if (dma_linked_lch[chain_id].chain_mode == - OMAP_DMA_DYNAMIC_CHAIN) - disable_lnk(ch); - - if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) - OMAP_DMA_CHAIN_INCQHEAD(chain_id); - - status = p->dma_read(CSR, ch); - p->dma_write(status, CSR, ch); - } - - if (likely(dma_chan[ch].callback != NULL)) - dma_chan[ch].callback(ch, status, dma_chan[ch].data); - - return 0; -} - -/* STATUS register count is from 1-32 while our is 0-31 */ -static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) -{ - u32 val, enable_reg; - int i; - - val = p->dma_read(IRQSTATUS_L0, 0); - if (val == 0) { - if (printk_ratelimit()) - printk(KERN_WARNING "Spurious DMA IRQ\n"); - return IRQ_HANDLED; - } - enable_reg = p->dma_read(IRQENABLE_L0, 0); - val &= enable_reg; /* Dispatch only relevant interrupts */ - for (i = 0; i < dma_lch_count && val != 0; i++) { - if (val & 1) - omap2_dma_handle_ch(i); - val >>= 1; - } - - return IRQ_HANDLED; -} - -static struct irqaction omap24xx_dma_irq = { - .name = "DMA", - .handler = omap2_dma_irq_handler, -}; - -#else -static struct irqaction omap24xx_dma_irq; -#endif - -/*----------------------------------------------------------------------------*/ - /* * Note that we are currently using only IRQENABLE_L0 and L1. * As the DSP may be using IRQENABLE_L2 and L3, let's not @@ -1139,7 +952,6 @@ static int omap_system_dma_probe(struct platform_device *pdev) int ch, ret = 0; int dma_irq; char irq_name[4]; - int irq_rel; p = pdev->dev.platform_data; if (!p) { @@ -1165,21 +977,9 @@ static int omap_system_dma_probe(struct platform_device *pdev) if (!dma_chan) return -ENOMEM; - if (dma_omap2plus()) { - dma_linked_lch = kcalloc(dma_lch_count, - sizeof(*dma_linked_lch), - GFP_KERNEL); - if (!dma_linked_lch) { - ret = -ENOMEM; - goto exit_dma_lch_fail; - } - } - spin_lock_init(&dma_chan_lock); for (ch = 0; ch < dma_chan_count; ch++) { omap_clear_dma(ch); - if (dma_omap2plus()) - omap2_disable_irq_lch(ch); dma_chan[ch].dev_id = -1; dma_chan[ch].next_lch = -1; @@ -1216,22 +1016,6 @@ static int omap_system_dma_probe(struct platform_device *pdev) omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0); - if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) { - strcpy(irq_name, "0"); - dma_irq = platform_get_irq_byname(pdev, irq_name); - if (dma_irq < 0) { - dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); - ret = dma_irq; - goto exit_dma_lch_fail; - } - ret = setup_irq(dma_irq, &omap24xx_dma_irq); - if (ret) { - dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n", - dma_irq, ret); - goto exit_dma_lch_fail; - } - } - /* reserve dma channels 0 and 1 in high security devices on 34xx */ if (d->dev_caps & HS_CHANNELS_RESERVED) { pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); @@ -1242,34 +1026,21 @@ static int omap_system_dma_probe(struct platform_device *pdev) return 0; exit_dma_irq_fail: - dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n", - dma_irq, ret); - for (irq_rel = 0; irq_rel < ch; irq_rel++) { - dma_irq = platform_get_irq(pdev, irq_rel); - free_irq(dma_irq, (void *)(irq_rel + 1)); - } - -exit_dma_lch_fail: return ret; } static int omap_system_dma_remove(struct platform_device *pdev) { - int dma_irq; + int dma_irq, irq_rel = 0; - if (dma_omap2plus()) { - char irq_name[4]; - strcpy(irq_name, "0"); - dma_irq = platform_get_irq_byname(pdev, irq_name); - if (dma_irq >= 0) - remove_irq(dma_irq, &omap24xx_dma_irq); - } else { - int irq_rel = 0; - for ( ; irq_rel < dma_chan_count; irq_rel++) { - dma_irq = platform_get_irq(pdev, irq_rel); - free_irq(dma_irq, (void *)(irq_rel + 1)); - } + if (dma_omap2plus()) + return 0; + + for ( ; irq_rel < dma_chan_count; irq_rel++) { + dma_irq = platform_get_irq(pdev, irq_rel); + free_irq(dma_irq, (void *)(irq_rel + 1)); } + return 0; } -- cgit v1.2.3 From f002180c3c4608dae5b184bdd8bfdbcf67e14fbe Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: OMAP2+: Configure sdma capabilities directly Only earlier SoCs need to be checked for this, all SoCs starting with omap3630 have CCDN register. This way we get closer to removing the need to ioremap sdma registers in the platform code. Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/dma.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index c138703aab90..a380bf823197 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -273,10 +273,10 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) d->dev_caps |= HS_CHANNELS_RESERVED; /* Check the capabilities register for descriptor loading feature */ - if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) - dma_common_ch_end = CCDN; - else + if (soc_is_omap24xx() || soc_is_omap34xx() || soc_is_am35xx()) dma_common_ch_end = CCFN; + else + dma_common_ch_end = CCDN; return 0; } -- cgit v1.2.3 From c6797bcde3070bb143a5ccbb5fe054f1ef6252e9 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: OMAP2+: Configure dma_plat_info directly and drop dma_dev_attr Let's prepare things for passing dma_plat_info to the dmaengine driver in device tree auxdata. To do that, we want to configure dma_plat_info directly. And we can also drop the related dma_dev_attr data. Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/dma.c | 31 +++++++++++++++++------------- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 8 -------- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 8 -------- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 8 -------- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 8 -------- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 8 -------- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 8 -------- 7 files changed, 18 insertions(+), 61 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index a380bf823197..9dd4807f5ee0 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -211,9 +211,16 @@ static const struct dma_slave_map omap24xx_sdma_dt_map[] = { { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */ }; +static struct omap_dma_dev_attr dma_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .lch_count = 32, +}; + static struct omap_system_dma_plat_info dma_plat_info __initdata = { .reg_map = reg_map, .channel_stride = 0x60, + .dma_attr = &dma_attr, .show_dma_caps = omap2_show_dma_caps, .clear_dma = omap2_clear_dma, .dma_write = dma_write, @@ -230,22 +237,25 @@ static struct platform_device_info omap_dma_dev_info __initdata = { static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) { struct platform_device *pdev; - struct omap_system_dma_plat_info p; - struct omap_dma_dev_attr *d; struct resource *mem; char *name = "omap_dma_system"; - p = dma_plat_info; - p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; - p.errata = configure_dma_errata(); + dma_plat_info.errata = configure_dma_errata(); if (soc_is_omap24xx()) { /* DMA slave map for drivers not yet converted to DT */ - p.slave_map = omap24xx_sdma_dt_map; - p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map); + dma_plat_info.slave_map = omap24xx_sdma_dt_map; + dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map); } - pdev = omap_device_build(name, 0, oh, &p, sizeof(p)); + if (!soc_is_omap242x()) + dma_attr.dev_caps |= IS_RW_PRIORITY; + + if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) + dma_attr.dev_caps |= HS_CHANNELS_RESERVED; + + pdev = omap_device_build(name, 0, oh, &dma_plat_info, + sizeof(dma_plat_info)); if (IS_ERR(pdev)) { pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, name, oh->name); @@ -267,11 +277,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) return -ENOMEM; } - d = oh->dev_attr; - - if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) - d->dev_caps |= HS_CHANNELS_RESERVED; - /* Check the capabilities register for descriptor loading feature */ if (soc_is_omap24xx() || soc_is_omap34xx() || soc_is_am35xx()) dma_common_ch_end = CCFN; diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index d49df96b4052..6127314ee97b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -126,18 +126,10 @@ static struct omap_hwmod omap2420_i2c2_hwmod = { .flags = HWMOD_16BIT_REG, }; -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32, - .lch_count = 32, -}; - static struct omap_hwmod omap2420_dma_system_hwmod = { .name = "dma", .class = &omap2xxx_dma_hwmod_class, .main_clk = "core_l3_ck", - .dev_attr = &dma_dev_attr, .flags = HWMOD_NO_IDLEST, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index c51ef84ff64d..05538f0fb20c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -121,18 +121,10 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { .class = &omap2xxx_gpio_hwmod_class, }; -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - static struct omap_hwmod omap2430_dma_system_hwmod = { .name = "dma", .class = &omap2xxx_dma_hwmod_class, .main_clk = "core_l3_ck", - .dev_attr = &dma_dev_attr, .flags = HWMOD_NO_IDLEST, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index f52438bdfc14..7ceece529c26 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -833,13 +833,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = { .class = &omap3xxx_gpio_hwmod_class, }; -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x002c, @@ -870,7 +863,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = { .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, }, }, - .dev_attr = &dma_dev_attr, .flags = HWMOD_NO_IDLEST, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 292f544bd62d..14167ae2dc2a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -422,13 +422,6 @@ static struct omap_hwmod_class omap44xx_dma_hwmod_class = { .sysc = &omap44xx_dma_sysc, }; -/* dma dev_attr */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - /* dma_system */ static struct omap_hwmod omap44xx_dma_system_hwmod = { .name = "dma_system", @@ -441,7 +434,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, }, }, - .dev_attr = &dma_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index cc5ad6acab1d..125ae4a79a45 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -256,13 +256,6 @@ static struct omap_hwmod_class omap54xx_dma_hwmod_class = { .sysc = &omap54xx_dma_sysc, }; -/* dma dev_attr */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - /* dma_system */ static struct omap_hwmod omap54xx_dma_system_hwmod = { .name = "dma_system", @@ -275,7 +268,6 @@ static struct omap_hwmod omap54xx_dma_system_hwmod = { .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, }, }, - .dev_attr = &dma_dev_attr, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index f8715bd96687..ff28c73112b6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -411,13 +411,6 @@ static struct omap_hwmod_class dra7xx_dma_hwmod_class = { .sysc = &dra7xx_dma_sysc, }; -/* dma dev_attr */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, - .lch_count = 32, -}; - /* dma_system */ static struct omap_hwmod dra7xx_dma_system_hwmod = { .name = "dma_system", @@ -430,7 +423,6 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = { .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, }, }, - .dev_attr = &dma_dev_attr, }; /* -- cgit v1.2.3 From 4c74ecf79227228f31d05d6d4766ccb5f8607b83 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: dmaengine: ti: omap-dma: Add device tree match data and use it for cpu_pm With old DMA code disabled for handling DMA requests for device tree based SoCs, we can move omap3 specific context save and restore to the dmaengine driver. Let's do this by adding cpu_pm notifier handling to save and restore context, and enable it based on device tree match data. This way we can use the match data later to configure more SoC specific features later on too. Note that we only clear the channels in use while the platform code also clears reserved channels 0 and 1 on high-security SoCs. Based on testing on n900, this is not needed though and the system idles just fine. With the dmaengine driver handling context save and restore, we must now remove the old custom calls for context save and restore. Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Acked-by: Vinod Koul Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm34xx.c | 5 ----- arch/arm/plat-omap/dma.c | 43 ------------------------------------------- 2 files changed, 48 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 54254fc92c2e..e66e9948636c 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include @@ -85,7 +84,6 @@ static void omap3_core_save_context(void) omap3_gpmc_save_context(); /* Save the system control module context, padconf already save above*/ omap3_control_save_context(); - omap_dma_global_context_save(); } static void omap3_core_restore_context(void) @@ -96,7 +94,6 @@ static void omap3_core_restore_context(void) omap3_gpmc_restore_context(); /* Restore the interrupt controller context */ omap_intc_restore_context(); - omap_dma_global_context_restore(); } /* @@ -547,9 +544,7 @@ int __init omap3_pm_init(void) local_irq_disable(); - omap_dma_global_context_save(); omap3_save_secure_ram_context(); - omap_dma_global_context_restore(); local_irq_enable(); } diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 8aea155b10a8..0f68c6faecad 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -68,13 +68,6 @@ static void omap_clear_dma(int lch); static int enable_1510_mode; static u32 errata; -static struct omap_dma_global_context_registers { - u32 dma_irqenable_l0; - u32 dma_irqenable_l1; - u32 dma_ocp_sysconfig; - u32 dma_gcr; -} omap_dma_global_context; - struct dma_link_info { int *linked_dmach_q; int no_of_lchs_linked; @@ -905,42 +898,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) #define omap1_dma_irq_handler NULL #endif -/* - * Note that we are currently using only IRQENABLE_L0 and L1. - * As the DSP may be using IRQENABLE_L2 and L3, let's not - * touch those for now. - */ -void omap_dma_global_context_save(void) -{ - omap_dma_global_context.dma_irqenable_l0 = - p->dma_read(IRQENABLE_L0, 0); - omap_dma_global_context.dma_irqenable_l1 = - p->dma_read(IRQENABLE_L1, 0); - omap_dma_global_context.dma_ocp_sysconfig = - p->dma_read(OCP_SYSCONFIG, 0); - omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); -} - -void omap_dma_global_context_restore(void) -{ - int ch; - - p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0); - p->dma_write(omap_dma_global_context.dma_ocp_sysconfig, - OCP_SYSCONFIG, 0); - p->dma_write(omap_dma_global_context.dma_irqenable_l0, - IRQENABLE_L0, 0); - p->dma_write(omap_dma_global_context.dma_irqenable_l1, - IRQENABLE_L1, 0); - - if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) - p->dma_write(0x3 , IRQSTATUS_L0, 0); - - for (ch = 0; ch < dma_chan_count; ch++) - if (dma_chan[ch].dev_id != -1) - omap_clear_dma(ch); -} - struct omap_system_dma_plat_info *omap_get_plat_info(void) { return p; -- cgit v1.2.3 From f60c41257fa06d496c9653d3f77d34b7426d9274 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:09 -0800 Subject: ARM: dts: Configure interconnect target module for am4 qspi We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Jean Pihet Acked-by: Jean Pihet Tested-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 38 ++++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index ca0aa3f26c0a..d0478530515b 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -305,17 +305,35 @@ status = "disabled"; }; - qspi: spi@47900000 { - compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>, - <0x30000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - #address-cells = <1>; - #size-cells = <0>; + target-module@47900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "qspi"; - interrupts = <0 138 0x4>; - num-cs = <4>; - status = "disabled"; + reg = <0x47900000 0x4>, + <0x47900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x47900000 0x1000>, + <0x30000000 0x30000000 0x4000000>; + + qspi: spi@0 { + compatible = "ti,am4372-qspi"; + reg = <0 0x100>, + <0x30000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; + clocks = <&dpll_per_m2_div4_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 138 0x4>; + num-cs = <4>; + }; }; dss: dss@4832a000 { -- cgit v1.2.3 From e36afc29ea98319247c3a33ff8d3590d00b5414e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:14 -0800 Subject: ARM: dts: Configure interconnect target module for am3 sham We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. I could not find any documentation for the sysc register on this one, but it seems to work just fine with "ti,sysc-omap3-sham" compatible style configuration. Cc: Keerthy Cc: Tero Kristo Tested-by: Tero Kristo Reviewed-by: Tero Kristo Tested-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 646f11430dad..0d7323b235ae 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -439,13 +439,33 @@ status = "disabled"; }; - sham: sham@53100000 { - compatible = "ti,omap4-sham"; + sham_target: target-module@53100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; ti,hwmods = "sham"; - reg = <0x53100000 0x200>; - interrupts = <109>; - dmas = <&edma 36 0>; - dma-names = "rx"; + reg = <0x53100100 0x4>, + <0x53100110 0x4>, + <0x53100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l3_clkdm */ + clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap4-sham"; + reg = <0 0x200>; + interrupts = <109>; + dmas = <&edma 36 0>; + dma-names = "rx"; + }; }; aes: aes@53500000 { -- cgit v1.2.3 From ed8e44dfa75762218368717a6a37b3b2bbdc5efd Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:14 -0800 Subject: ARM: dts: Configure interconnect target module for am4 sham We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Similar to am3, I could not find any documentation for the sysc register on this one, but it seems to work just fine based on "ti,sysc-omap3-sham" compatible style configuration. Cc: Keerthy Cc: Tero Kristo Tested-by: Tero Kristo Reviewed-by: Tero Kristo Tested-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d0478530515b..4496f767c7a4 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -256,13 +256,33 @@ }; }; - sham: sham@53100000 { - compatible = "ti,omap5-sham"; + sham_target: target-module@53100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; ti,hwmods = "sham"; - reg = <0x53100000 0x300>; - dmas = <&edma 36 0>; - dma-names = "rx"; - interrupts = ; + reg = <0x53100100 0x4>, + <0x53100110 0x4>, + <0x53100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l3_clkdm */ + clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap5-sham"; + reg = <0 0x300>; + dmas = <&edma 36 0>; + dma-names = "rx"; + interrupts = ; + }; }; aes: aes@53501000 { -- cgit v1.2.3 From e132681cef0aedf0a10858bc8cca74a0e9338025 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:15 -0800 Subject: ARM: dts: Configure interconnect target module for dra7 sham We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Similar to am3, I could not find any documentation for the sysc register on this one, but it seems to work just fine based on "ti,sysc-omap3-sham" compatible style configuration. Cc: Keerthy Cc: Tero Kristo Tested-by: Tero Kristo Reviewed-by: Tero Kristo Tested-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 73e5011f531a..bf8c10053b04 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -685,15 +685,35 @@ clock-names = "fck"; }; - sham: sham@53100000 { - compatible = "ti,omap5-sham"; + sham_target: target-module@4b101000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; ti,hwmods = "sham"; - reg = <0x4b101000 0x300>; - interrupts = ; - dmas = <&edma_xbar 119 0>; - dma-names = "rx"; - clocks = <&l3_iclk_div>; + reg = <0x4b101100 0x4>, + <0x4b101110 0x4>, + <0x4b101114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b101000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap5-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&edma_xbar 119 0>; + dma-names = "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; }; opp_supply_mpu: opp-supply@4a003b20 { -- cgit v1.2.3 From b4679c0544fe68361b9bbe63f0b43a2e45f6fd27 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:15 -0800 Subject: ARM: dts: Configure interconnect target module for am3 aes We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Keerthy Cc: Tero Kristo Tested-by: Tero Kristo Reviewed-by: Tero Kristo Tested-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 35 ++++++++++++++++++++++++++++------- 1 file changed, 28 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 0d7323b235ae..7db9f72a03d5 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -468,14 +468,35 @@ }; }; - aes: aes@53500000 { - compatible = "ti,omap4-aes"; + aes_target: target-module@53500000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "aes"; - reg = <0x53500000 0xa0>; - interrupts = <103>; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; + reg = <0x53500080 0x4>, + <0x53500084 0x4>, + <0x53500088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l3_clkdm */ + clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53500000 0x1000>; + + aes: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = <103>; + dmas = <&edma 6 0>, + <&edma 5 0>; + dma-names = "tx", "rx"; + }; }; }; }; -- cgit v1.2.3 From e9225f22c760c6a6a04290eb4195ade079c22625 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:16 -0800 Subject: ARM: dts: Configure interconnect target module for am4 aes We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Keerthy Cc: Tero Kristo Tested-by: Tero Kristo Reviewed-by: Tero Kristo Tested-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 35 ++++++++++++++++++++++++++++------- 1 file changed, 28 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 4496f767c7a4..9c98c7b3d658 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -285,14 +285,35 @@ }; }; - aes: aes@53501000 { - compatible = "ti,omap4-aes"; + aes_target: target-module@53501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "aes"; - reg = <0x53501000 0xa0>; - interrupts = ; - dmas = <&edma 6 0>, - <&edma 5 0>; - dma-names = "tx", "rx"; + reg = <0x53501080 0x4>, + <0x53501084 0x4>, + <0x53501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l3_clkdm */ + clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53501000 0x1000>; + + aes: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&edma 6 0>, + <&edma 5 0>; + dma-names = "tx", "rx"; + }; }; des: des@53701000 { -- cgit v1.2.3 From 2ea3ce2cf6abbdc446b4742c97f6528e73b74345 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Dec 2019 09:46:16 -0800 Subject: ARM: dts: Configure interconnect target module for dra7 aes We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Keerthy Cc: Tero Kristo Tested-by: Tero Kristo Reviewed-by: Tero Kristo Tested-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 70 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 56 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index bf8c10053b04..e591add8a4ac 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -652,26 +652,68 @@ }; }; - aes1: aes@4b500000 { - compatible = "ti,omap4-aes"; + aes1_target: target-module@4b500000 { + compatible = "ti,sysc-om