From 5ea40f7106aaa4e2736d18075ca635389797fc16 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 22 Jul 2019 16:08:16 +0200 Subject: ARM: dts: sunxi: Unify the DE2 bus clocks order The DE2 bus takes two clocks, named bus and mod according to the binding. However, the order of these clocks change from one SoC to another. Even though it might not be an issue in most cases, having consistency will help if we ever need to have some code to deal with deprecated bindings, and in general it's just better. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 9cc9bdde81ac..60afacfe141d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -228,10 +228,10 @@ display_clocks: clock@0 { compatible = "allwinner,sun50i-a64-de2-clk"; reg = <0x0 0x100000>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "bus"; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; resets = <&ccu RST_BUS_DE>; #clock-cells = <1>; #reset-cells = <1>; -- cgit v1.2.3 From 042c805545d04f8d358475c83a54178da14f60ed Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 22 Jul 2019 16:08:17 +0200 Subject: arm64: dts: allwinner: h6: Fix SID node name The SID node one the H6 doesn't have a standard node name. Switch to the one we use for the other SoCs. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 7628a7c83096..0f571798fc95 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -215,7 +215,7 @@ #dma-cells = <1>; }; - sid: sid@3006000 { + sid: efuse@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; }; -- cgit v1.2.3 From d40113fb5f7e632232546a74aae6e6d8ca2e70e2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 23 Jul 2019 10:44:07 +0200 Subject: ARM: dts: sunxi: Fix the HDMI PHY name Even though the binding mentions that the PHY name must be "phy", it turns out that all our DTs had "hdmi-phy" instead. The code doesn't care about the phy-names property, so we can just change our DTs to match the binding, without any side effect. Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 60afacfe141d..aa9897f270ba 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1015,7 +1015,7 @@ resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; + phy-names = "phy"; status = "disabled"; ports { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 0f571798fc95..35942bae0a34 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -504,7 +504,7 @@ resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; reset-names = "ctrl", "hdcp"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; + phy-names = "phy"; pinctrl-names = "default"; pinctrl-0 = <&hdmi_pins>; status = "disabled"; -- cgit v1.2.3 From 44a4f416c8388449fc5f9263788857d449e2a65f Mon Sep 17 00:00:00 2001 From: Igors Makejevs Date: Sat, 8 Jun 2019 01:10:55 +0200 Subject: arm64: dts: allwinner: a64: Add IR node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IR peripheral is completely compatible with A31 one. Signed-off-by: Igors Makejevs Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron Acked-by: Sean Young Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index aa9897f270ba..ddb6f11e89df 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1094,6 +1094,19 @@ #size-cells = <0>; }; + r_ir: ir@1f02000 { + compatible = "allwinner,sun50i-a64-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01f02000 0x400>; + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_APB0_IR>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "disabled"; + }; + r_pwm: pwm@1f03800 { compatible = "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm"; @@ -1121,6 +1134,11 @@ function = "s_i2c"; }; + r_ir_rx_pin: r-ir-rx-pin { + pins = "PL11"; + function = "s_cir_rx"; + }; + r_pwm_pin: r-pwm-pin { pins = "PL10"; function = "s_pwm"; -- cgit v1.2.3 From 63eb1e149576294717e3e5de48e902ca9d2f080d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 8 Jun 2019 01:10:56 +0200 Subject: arm64: dts: allwinner: a64: Enable IR on Orange Pi Win MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OrangePi Win board contains IR receiver. Enable it. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron Acked-by: Sean Young Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index 5ef3c62c765e..04446e4716c4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -190,6 +190,10 @@ status = "okay"; }; +&r_ir { + status = "okay"; +}; + &r_rsb { status = "okay"; -- cgit v1.2.3 From 9267811aad3524c857cf2e16bbadd8c569e15ab9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Sat, 8 Jun 2019 01:10:58 +0200 Subject: arm64: dts: allwinner: h6: Add IR receiver node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allwinner H6 IR is similar to A31 and can use same driver. Add support for it. Signed-off-by: Clément Péron Acked-by: Sean Young Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 35942bae0a34..e8bed58e7246 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -675,6 +675,25 @@ pins = "PL0", "PL1"; function = "s_i2c"; }; + + r_ir_rx_pin: r-ir-rx-pin { + pins = "PL9"; + function = "s_cir_rx"; + }; + }; + + r_ir: ir@7040000 { + compatible = "allwinner,sun50i-h6-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x07040000 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_APB1_IR>, + <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_R_APB1_IR>; + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "disabled"; }; r_i2c: i2c@7081400 { -- cgit v1.2.3 From 86be740845e3811c4517de1a8a36121190155e22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Sat, 8 Jun 2019 01:10:59 +0200 Subject: arm64: dts: allwinner: h6: Enable IR on H6 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Beelink GS1, OrangePi H6 boards and Pine H64 have an IR receiver. Enable it in their device-tree. Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 4 ++++ arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++++ 3 files changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 0dc33c90dd60..680dc29cb089 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -232,6 +232,10 @@ }; }; +&r_ir { + status = "okay"; +}; + &r_pio { /* * PL0 and PL1 are used for PMIC I2C diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi index 62e27948a3fa..ec9b6a578e3f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -189,6 +189,10 @@ }; }; +&r_ir { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 189834518391..30102daf83cc 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -255,6 +255,10 @@ }; }; +&r_ir { + status = "okay"; +}; + &r_pio { vcc-pm-supply = <®_aldo1>; }; -- cgit v1.2.3 From 802cbe1b46dca72c922f1ed33333e1d19e4c988e Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 6 Aug 2019 17:57:43 +0200 Subject: arm64: dts: allwinner: orange-pi-3: Enable HDMI output Orange Pi 3 has a DDC_CEC_EN signal connected to PH2, that enables the DDC I2C bus voltage shifter. Before EDID can be read, we need to pull PH2 high. This is realized by the ddc-en-gpios property. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 17d496990108..eda9d5f640b9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -21,6 +21,18 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -50,6 +62,10 @@ cpu-supply = <®_dcdca>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -58,6 +74,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -- cgit v1.2.3 From f95b598df4195c7e2a7116ba3eeb3742a4cb3e9b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Mon, 12 Aug 2019 12:51:14 +0200 Subject: arm64: dts: allwinner: Add SPDIF node for Allwinner H6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Allwinner H6 has a SPDIF controller called OWA (One Wire Audio). Only one pinmuxing is available so set it as default. Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index e8bed58e7246..02d79c6431c5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -282,6 +282,11 @@ bias-pull-up; }; + spdif_tx_pin: spdif-tx-pin { + pins = "PH7"; + function = "spdif"; + }; + uart0_ph_pins: uart0-ph-pins { pins = "PH0", "PH1"; function = "uart0"; @@ -411,6 +416,21 @@ }; }; + spdif: spdif@5093000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-h6-spdif"; + reg = <0x05093000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + clock-names = "apb", "spdif"; + resets = <&ccu RST_BUS_SPDIF>; + dmas = <&dma 2>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "disabled"; + }; + usb2otg: usb@5100000 { compatible = "allwinner,sun50i-h6-musb", "allwinner,sun8i-a33-musb"; -- cgit v1.2.3 From 45dd5cf87291fabcef8ce8817d8f2277ccdd14f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Mon, 12 Aug 2019 12:51:15 +0200 Subject: arm64: dts: allwinner: h6: Enable SPDIF for Beelink GS1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Beelink GS1 board has a SPDIF out connector, so enable it in the device-tree and add a simple SPDIF soundcard. Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 680dc29cb089..675c602b0e33 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -51,6 +51,24 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun50i-h6-spdif"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; }; &de { @@ -247,6 +265,10 @@ vcc-pm-supply = <®_aldo1>; }; +&spdif { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; -- cgit v1.2.3 From f46f408c152ac925e56c0f38138ae49ba16bbc23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Mon, 12 Aug 2019 12:23:55 +0200 Subject: arm64: dts: allwinner: Enable DDC regulator for Beelink GS1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Beelink GS1 has a DDC I2C bus voltage shifter. This is actually missing and video is limited to 1024x768 due to missing EDID information. Add the DDC regulator in the device-tree. Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 675c602b0e33..1d05d570142f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -25,6 +25,7 @@ connector { compatible = "hdmi-connector"; type = "a"; + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ port { hdmi_con_in: endpoint { -- cgit v1.2.3 From 89336e1f096d6e8d99e74df63652f8e64d788cac Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Fri, 16 Aug 2019 14:13:09 +0530 Subject: arm64: allwinner: h6: add I2C nodes Add device-tree nodes for i2c0 to i2c2, and also add relevant pinctrl nodes. Suggested-by: Icenowy Zheng Signed-off-by: Bhushan Shah Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 60 +++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 02d79c6431c5..67b732e34091 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -256,6 +256,21 @@ function = "hdmi"; }; + i2c0_pins: i2c0-pins { + pins = "PD25", "PD26"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PH5", "PH6"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PD23", "PD24"; + function = "i2c2"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -396,6 +411,48 @@ status = "disabled"; }; + i2c0: i2c@5002000 { + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@5002400 { + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@5002800 { + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@5020000 { compatible = "allwinner,sun50i-h6-emac", "allwinner,sun50i-a64-emac"; @@ -717,7 +774,8 @@ }; r_i2c: i2c@7081400 { - compatible = "allwinner,sun6i-a31-i2c"; + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; reg = <0x07081400 0x400>; interrupts = ; clocks = <&r_ccu CLK_R_APB2_I2C>; -- cgit v1.2.3 From 652a458eb92018c5126701e721255356fdab94a9 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 16 Aug 2019 22:53:42 +0200 Subject: arm64: dts: allwinner: h6: Introduce Tanix TX6 board Tanix TX6 is an Allwinner H6 based TV box, which supports: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 4GiB DDR3 RAM (3GiB useable) - 100Mbps EMAC via AC200 EPHY - Cdtech 47822BS Wifi/BT - 2x USB 2.0 Host and 1x USB 3.0 Host - HDMI port - IR receiver - 64GiB eMMC - 5V/2A DC power supply Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 100 +++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index f6db0611cb85..395fe76f6819 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -25,3 +25,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts new file mode 100644 index 000000000000..7e7cb10e3d96 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (c) 2019 Jernej Skrabec + */ + +/dts-v1/; + +#include "sun50i-h6.dtsi" + +#include + +/ { + model = "Tanix TX6"; + compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&r_ir { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usb2otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; -- cgit v1.2.3 From 94f68f3a4b2ae71ef4cd4a4be94d76c98df9625b Mon Sep 17 00:00:00 2001 From: Sunil Mohan Adapa Date: Wed, 21 Aug 2019 12:52:17 -0700 Subject: arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC) A64 OLinuXino board from Olimex has three variants with onboard eMMC: A64-OLinuXino-1Ge16GW, A64-OLinuXino-1Ge4GW and A64-OLinuXino-2Ge8G-IND. In addition, there are two variants without eMMC. One without eMMC and one with SPI flash. This suggests the need for separate device tree for the three eMMC variants. This patch has been tested on A64-OLinuXino-1Ge16GW with Linux 5.0 from Debain. Basic benchmarks using Flexible IO Tester show reasonable performance from the eMMC. eMMC - Random Write: 21.3MiB/s eMMC - Sequential Write: 68.2MiB/s SD Card - Random Write: 1690KiB/s SD Card - Sequential Write: 11.0MiB/s Changes: v3: Separate dts for eMMC variants v2: Fix descriptions for VCC and VCCQ Link: https://github.com/armbian/build/commit/174953de1eb09e6aa1ef7075066b573dba625398 Signed-off-by: Martin Ayotte [sunil@medhas.org Fix descriptions for VCC and VCCQ, separate dts for eMMC] Signed-off-by: Sunil Mohan Adapa Tested-by: Sunil Mohan Adapa Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun50i-a64-olinuxino-emmc.dts | 23 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 395fe76f6819..d2418021768b 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-emmc.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts new file mode 100644 index 000000000000..96ab0227e82d --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Martin Ayotte + * Copyright (C) 2019 Sunil Mohan Adapa + */ + +#include "sun50i-a64-olinuxino.dts" + +/ { + model = "Olimex A64-Olinuxino-eMMC"; + compatible = "olimex,a64-olinuxino-emmc", "allwinner,sun50i-a64"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; -- cgit v1.2.3 From 4cdc12a3ef424361f81bb30a34a3148b03df640c Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Tue, 20 Aug 2019 17:19:34 +0200 Subject: arm64: dts: allwinner: h6: Add support for RTC and fix the clock tree This patch adds RTC node and fixes the clock properties and nodes to reflect the real clock tree. The device nodes for the internal oscillator and osc32k are removed, as these clocks are now provided by the RTC device. Clock references are fixed accordingly, too. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30 +++++++++++++++------------- 1 file changed, 16 insertions(+), 14 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 67b732e34091..67f920e0fc33 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -56,14 +56,6 @@ status = "disabled"; }; - iosc: internal-osc-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-accuracy = <300000000>; - clock-output-names = "iosc"; - }; - osc24M: osc24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -71,11 +63,11 @@ clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + ext_osc32k: ext_osc32k_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-output-names = "ext_osc32k"; }; psci { @@ -197,7 +189,7 @@ ccu: clock@3001000 { compatible = "allwinner,sun50i-h6-ccu"; reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&osc32k>, <&iosc>; + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; @@ -236,7 +228,7 @@ , , ; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -710,10 +702,20 @@ }; }; + rtc: rtc@7000000 { + compatible = "allwinner,sun50i-h6-rtc"; + reg = <0x07000000 0x400>; + interrupts = , + ; + clock-output-names = "osc32k", "osc32k-out", "iosc"; + clocks = <&ext_osc32k>; + #clock-cells = <1>; + }; + r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h6-r-ccu"; reg = <0x07010000 0x400>; - clocks = <&osc24M>, <&osc32k>, <&iosc>, + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -741,7 +743,7 @@ reg = <0x07022000 0x400>; interrupts = , ; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; -- cgit v1.2.3 From 9e1975f0bca9ef9fc5d76f056cab7240e25bca76 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Aug 2019 16:38:35 +0200 Subject: ARM: dts: sunxi: Add missing watchdog clocks The watchdog has a clock on all our SoCs, but it wasn't always listed. Add it to the devicetree where it's missing. Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 ++ 2 files changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index ddb6f11e89df..69128a6dfc46 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1169,6 +1169,7 @@ "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = ; + clocks = <&osc24M>; }; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 67f920e0fc33..4020a1aafa3e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -217,6 +217,7 @@ "allwinner,sun6i-a31-wdt"; reg = <0x030090a0 0x20>; interrupts = ; + clocks = <&osc24M>; /* Broken on some H6 boards */ status = "disabled"; }; @@ -727,6 +728,7 @@ "allwinner,sun6i-a31-wdt"; reg = <0x07020400 0x20>; interrupts = ; + clocks = <&osc24M>; }; r_intc: interrupt-controller@7021000 { -- cgit v1.2.3 From 15ede97054889c0bec09f1f9b71beffecf06fc67 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Fri, 23 Aug 2019 11:42:28 +0200 Subject: arm64: dts: allwinner: orange-pi-3: Enable WiFi Orange Pi 3 has AP6256 WiFi/BT module. WiFi part of the module is called bcm43356 and can be used with the brcmfmac driver. The module is powered by the two always on regulators (not AXP805). WiFi uses a PG port with 1.8V voltage level signals. SoC needs to be configured so that it sets up an 1.8V input bias on this port. This is done by the pio driver by reading the vcc-pg-supply voltage. You'll need a fw_bcm43456c5_ag.bin firmware file and nvram.txt configuration that can be found in the Xulongs's repository for H6: https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256 Mainline brcmfmac driver expects the firmware and nvram at the following paths relative to the firmware directory: brcm/brcmfmac43456-sdio.bin brcm/brcmfmac43456-sdio.txt Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index eda9d5f640b9..eb379cd402ac 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -56,6 +56,34 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + reg_vcc33_wifi: vcc33-wifi { + /* Always on 3.3V regulator for WiFi and BT */ + compatible = "regulator-fixed"; + regulator-name = "vcc33-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vcc5v>; + }; + + reg_vcc_wifi_io: vcc-wifi-io { + /* Always on 1.8V/300mA regulator for WiFi and BT IO */ + compatible = "regulator-fixed"; + regulator-name = "vcc-wifi-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <®_vcc33_wifi>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "ext_clock"; + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ + post-power-on-delay-ms = <200>; + }; }; &cpu0 { @@ -91,6 +119,23 @@ status = "okay"; }; +&mmc1 { + vmmc-supply = <®_vcc33_wifi>; + vqmmc-supply = <®_vcc_wifi_io>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcm: sdio-wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ + interrupt-names = "host-wake"; + }; +}; + &ohci0 { status = "okay"; }; @@ -102,6 +147,7 @@ &pio { vcc-pc-supply = <®_bldo2>; vcc-pd-supply = <®_cldo1>; + vcc-pg-supply = <®_vcc_wifi_io>; }; &r_i2c { -- cgit v1.2.3