From 30bd02bd634f4a483e965fb41a076e47ea9681ef Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 16 Jan 2020 23:11:46 +0000 Subject: arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, but with the added capability of 3-wire and 4-wire operation modes. For now the driver does not support those, but the SPI registers are fully backwards-compatible, just adding bits and registers which were formerly reserved. So we can use the existing driver in "legacy" SPI modes, for instance to access the SPI NOR flash soldered on the PineH64 board. We use an H6 specific compatible string in addition to the existing H3 string, so when the driver later gains QSPI support, it should work automatically without any DT changes. Tested by accessing the SPI flash on a Pine H64 board (SPI0), also connecting another SPI flash to the SPI1 header pins. Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 3329283e38ab..41b58ffa8596 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -338,6 +338,31 @@ bias-pull-up; }; + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC0", "PC2", "PC3"; + function = "spi0"; + }; + + /* pin shared with MMC2-CMD (eMMC) */ + /omit-if-no-ref/ + spi0_cs_pin: spi0-cs-pin { + pins = "PC5"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pins: spi1-pins { + pins = "PH4", "PH5", "PH6"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs_pin: spi1-cs-pin { + pins = "PH3"; + function = "spi1"; + }; + spdif_tx_pin: spdif-tx-pin { pins = "PH7"; function = "spdif"; @@ -504,6 +529,36 @@ #size-cells = <0>; }; + spi0: spi@5010000 { + compatible = "allwinner,sun50i-h6-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05010000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@5011000 { + compatible = "allwinner,sun50i-h6-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05011000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@5020000 { compatible = "allwinner,sun50i-h6-emac", "allwinner,sun50i-a64-emac"; -- cgit v1.2.3 From e757bdd01780d0ea3e6774247b735caf2d1a9e92 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 16 Jan 2020 23:11:47 +0000 Subject: arm64: dts: allwinner: h6: Pine H64: Add SPI flash node The Pine H64 board comes with SPI flash soldered on the board, connected to the SPI0 pins (so it can also boot from there). Add the required SPI flash DT node to describe this. Unfortunately the SPI CS0 pin collides with the eMMC CMD pin, so we can't use both eMMC and SPI flash at the same time (the first to claim the pin would win, the other's probe routine would then fail). To avoid losing the more useful eMMC device by chance, mark the SPI device as "disabled" for now. A user or some U-Boot code could fix this up if needed, for instance if no eMMC has been detected (it's socketed). Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index d1c2aa5b3a20..3c9dd0d69754 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -14,6 +14,7 @@ aliases { ethernet0 = &emac; serial0 = &uart0; + spi0 = &spi0; }; chosen { @@ -278,6 +279,24 @@ vcc-pm-supply = <®_aldo1>; }; +/* + * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI + * flash and eMMC at the same time, as one of them would fail probing. + * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can + * fix this up in no eMMC is connected. + */ +&spi0 { + pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>; + pinctrl-names = "default"; + status = "disabled"; + + flash@0 { + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; -- cgit v1.2.3 From 674ef1d0a7b23681699994a892a1ed508c7df122 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 16 Jan 2020 11:36:36 +0800 Subject: arm64: dts: allwinner: a64: add support for PineTab PineTab is a 10.1" tablet by Pine64 with Allwinner A64 inside. It includes the following peripherals: USB: - A microUSB Type-B port connected to the OTG-capable USB PHY of Allwinner A64. The ID pin is connected to a GPIO of the A64 SoC, and the Vbus is connected to the Vbus of AXP803 PMIC. These enables OTG functionality on this port. - A USB Type-A port is connected to the internal hub attached to the non-OTG USB PHY of Allwinner A64. - There are reserved pins for an external keyboard connected to the internal hub. Power: - The microUSB port has its Vbus connected to AXP803, mentioned above. - A DC jack (of a strange size, 2.5mm outer diameter) is connected to the ACIN of AXP803. - A Li-Polymer battery is connected to the battery pins of AXP803. Storage: - An tradition Pine64 eMMC slot is on the board, mounted with an eMMC module by factory. - An external microSD slot is hidden under a protect case. Display: - A MIPI-DSI LCD panel (800x1280) is connected to the DSI port of A64 SoC. - A mini HDMI port. Input: - A touch panel attached to a Goodix GT9271 touch controller. - Volume keys connected to the LRADC of the A64 SoC. Camera: - An OV5640 CMOS camera is at rear, connected to the CSI bus of A64 SoC. - A GC2145 CMOS camera is at front, shares the same CSI bus with OV5640. Audio: - A headphone jack is conencted to the SoC's internal codec. - A speaker connected is to the Line Out port of SoC's internal codec, via an amplifier. Misc: - Debug UART is muxed with the headphone jack, with the switch next to the microSD slot. - A bosch BMA223 accelerometer is connected to the I2C bus of A64 SoC. - Wi-Fi and Bluetooth are available via a RTL8723CS chip, similar to the one in Pinebook. This commit adds a basically usable device tree for it, implementing most of the features mentioned above. HDMI is not supported now because bad LCD-HDMI coexistence situation of mainline A64 display driver, the front camera currently lacks a driver and a facility to share the bus with the rear one, and the accelerometer currently lacks a DT binding. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../boot/dts/allwinner/sun50i-a64-pinetab.dts | 460 +++++++++++++++++++++ 2 files changed, 461 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index cf4f78617c3f..6dad63881cd3 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts new file mode 100644 index 000000000000..316e8a443913 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng + * + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" + +#include +#include +#include + +/ { + model = "PineTab"; + compatible = "pine64,pinetab", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + ethernet0 = &rtl8723cs; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>; + default-brightness-level = <15>; + enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ + power-supply = <&vdd_bl>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + i2c-csi { + compatible = "i2c-gpio"; + sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */ + scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */ + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + + /* Rear camera */ + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_mclk_pin>; + clocks = <&ccu CLK_CSI_MCLK>; + clock-names = "xclk"; + + AVDD-supply = <®_dldo3>; + DOVDD-supply = <®_aldo1>; + DVDD-supply = <®_eldo3>; + reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */ + powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ + + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; + }; + + speaker_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + sound-name-prefix = "Speaker Amp"; + }; + + vdd_bl: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "bl-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + post-power-on-delay-ms = <200>; + }; +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + hpvcc-supply = <®_eldo1>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&csi { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; + +&dai { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + vcc-dsi-supply = <®_dldo1>; + status = "okay"; + + panel@0 { + compatible = "feixin,k101-im2ba02"; + reg = <0>; + avdd-supply = <®_dc1sw>; + dvdd-supply = <®_dc1sw>; + cvdd-supply = <®_ldo_io1>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + backlight = <&backlight>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ + irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + AVDD28-supply = <®_ldo_io1>; + }; +}; + +&i2c0_pins { + bias-pull-up; +}; + +&i2c1 { + status = "okay"; + + /* TODO: add Bochs BMA223 accelerometer here */ +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button-200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <400000>; + }; +}; + +&mixer1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo4>; + vqmmc-supply = <®_eldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723cs: wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pwm { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp803.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "dovdd-csi"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi-dsi-sensor"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca-1v8"; +}; + +®_eldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-1v8-csi"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <3500000>; + regulator-name = "vcc-touchscreen"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&sound { + status = "okay"; + simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; + simple-audio-card,widgets = "Microphone", "Internal Microphone Left", + "Microphone", "Internal Microphone Right", + "Headphone", "Headphone Jack", + "Speaker", "Internal Speaker"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "Speaker Amp INL", "LINEOUT", + "Speaker Amp INR", "LINEOUT", + "Internal Speaker", "Speaker Amp OUTL", + "Internal Speaker", "Speaker Amp OUTR", + "Headphone Jack", "HP", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Internal Microphone Left", "MBIAS", + "MIC1", "Internal Microphone Left", + "Internal Microphone Right", "HBIAS", + "MIC2", "Internal Microphone Right"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_ldo_io0>; + status = "okay"; +}; -- cgit v1.2.3 From 787615ad874151af11017e95e29b7f1ef1c1590f Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 19 Jan 2020 10:30:56 -0600 Subject: arm64: dts: allwinner: Enable button wakeup on Orange Pi PC2 The Orange Pi PC2 features a GPIO button. As the button is connected to Port L (pin PL3), it can be used as a wakeup source. Enable this. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 70b5f0998421..c4f89c312f42 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -61,6 +61,7 @@ label = "sw4"; linux,code = ; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; -- cgit v1.2.3 From 9e556ec5731eb3a7df3ee27e832d74b17390499e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 19 Jan 2020 10:30:57 -0600 Subject: arm64: dts: allwinner: pinebook: Remove unused vcc3v3 regulator This fixed regulator has no consumers, GPIOs, or other connections. Remove it. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 3d894b208901..ff32ca1a495e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -63,13 +63,6 @@ }; }; - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -- cgit v1.2.3 From c0e79b069e4ff6e0881d82ba831424ca7362e828 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 19 Jan 2020 10:30:59 -0600 Subject: arm64: dts: allwinner: pinebook: Sort device tree nodes The r_i2c node should come before r_rsb, and in any case should not separate the axp803 node from its subnodes. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index ff32ca1a495e..77784f7b1da7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -172,6 +172,14 @@ status = "okay"; }; +/* The ANX6345 eDP-bridge is on r_i2c */ +&r_i2c { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pl89_pins>; + status = "okay"; +}; + &r_rsb { status = "okay"; @@ -183,14 +191,6 @@ }; }; -/* The ANX6345 eDP-bridge is on r_i2c */ -&r_i2c { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pl89_pins>; - status = "okay"; -}; - #include "axp803.dtsi" &ac_power_supply { -- cgit v1.2.3 From c3d22680df8da15c6ee2a6a157fcf3078915cc26 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 19 Jan 2020 10:31:00 -0600 Subject: arm64: dts: allwinner: pinebook: Make simplefb more consistent Boards generally reference the simplefb nodes from the SoC dtsi by label, not by full path. simplefb_hdmi is already like this in the Pinebook DTS. Update simplefb_lcd to match. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 77784f7b1da7..224bed65d008 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -41,12 +41,6 @@ chosen { stdout-path = "serial0:115200n8"; - - framebuffer-lcd { - panel-supply = <®_dc1sw>; - dvdd25-supply = <®_dldo2>; - dvdd12-supply = <®_fldo1>; - }; }; gpio_keys { @@ -316,6 +310,12 @@ regulator-name = "vcc-rtc"; }; +&simplefb_lcd { + panel-supply = <®_dc1sw>; + dvdd25-supply = <®_dldo2>; + dvdd12-supply = <®_fldo1>; +}; + &simplefb_hdmi { vcc-hdmi-supply = <®_dldo1>; }; -- cgit v1.2.3 From 412e19c34f501da68c19d8fdd7de4c535ea89d3b Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 19 Jan 2020 10:31:01 -0600 Subject: arm64: dts: allwinner: pinebook: Document MMC0 CD pin name Normally GPIO pin references are followed by a comment giving the pin name for searchability. Add the comment here where it was missing. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 224bed65d008..a1e15777d524 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -119,7 +119,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ disable-wp; bus-width = <4>; status = "okay"; -- cgit v1.2.3 From 9de2b6bf5ecb1f2149ffe19e4aefbdcbe68790f1 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 19 Jan 2020 10:31:02 -0600 Subject: arm64: dts: allwinner: pinebook: Add GPIO port regulators Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL. VCC-PC and VCC-PG are supplied by ELDO1 at 1.8v. VCC-PD is supplied by DCDC1 (VCC-IO) at 3.3v. VCC-PE is supplied by ALDO1, and is unused. VCC-PL creates a circular dependency, so it is omitted for now. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index a1e15777d524..1ec39120323f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -162,6 +162,13 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_eldo1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_aldo1>; + vcc-pg-supply = <®_eldo1>; +}; + &pwm { status = "okay"; }; @@ -174,6 +181,16 @@ status = "okay"; }; +&r_pio { + /* + * FIXME: We can't add that supply for now since it would + * create a circular dependency between pinctrl, the regulator + * and the RSB Bus. + * + * vcc-pl-supply = <®_aldo2>; + */ +}; + &r_rsb { status = "okay"; -- cgit v1.2.3 From 47ef030c3a796e07fec12c6981bbb46bcb258e2e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 19 Jan 2020 10:31:03 -0600 Subject: arm64: dts: allwinner: pinebook: Fix backlight regulator The output from the backlight regulator is labeled as "VBKLT" in the schematic. Using the equation and resistor values from the schematic, the output is approximately 18V, not 3.3V. Since the regulator in use (SS6640STR) is a boost regulator powered by PS (battery or AC input), which are both >3.3V, the output could not be 3.3V anyway. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- .../arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 1ec39120323f..313f4e6edc19 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -21,22 +21,13 @@ ethernet0 = &rtl8723cs; }; - vdd_bl: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "bl-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - enable-active-high; - }; - backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 50000 0>; brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; default-brightness-level = <2>; enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ - power-supply = <&vdd_bl>; + power-supply = <®_vbklt>; }; chosen { @@ -57,6 +48,15 @@ }; }; + reg_vbklt: vbklt { + compatible = "regulator-fixed"; + regulator-name = "vbklt"; + regulator-min-microvolt = <18000000>; + regulator-max-microvolt = <18000000>; + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -- cgit v1.2.3 From e95d8d03b5904a373895c14a44eb60264c7bc041 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 19 Jan 2020 10:31:04 -0600 Subject: arm64: dts: allwinner: pinebook: Fix 5v0 boost regulator Now that AXP803 GPIO support is available, we can properly model the hardware. Replace the use of GPIO0-LDO with a fixed regulator controlled by GPIO0. This boost regulator is used to power the (internal and external) USB ports, as well as the speakers. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-a64-pinebook.dts | 27 ++++++++++------------ 1 file changed, 12 insertions(+), 15 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 313f4e6edc19..c06c540e6c08 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -57,6 +57,15 @@ enable-active-high; }; + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ @@ -64,12 +73,7 @@ speaker_amp: audio-amplifier { compatible = "simple-audio-amplifier"; - /* - * TODO This is actually a fixed regulator controlled by - * the GPIO line on the PMIC. This should be corrected - * once GPIO support is added for this PMIC. - */ - VCC-supply = <®_ldo_io0>; + VCC-supply = <®_vcc5v0>; enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ sound-name-prefix = "Speaker Amp"; }; @@ -316,13 +320,6 @@ regulator-name = "vdd-cpus"; }; -®_ldo_io0 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb"; - status = "okay"; -}; - ®_rtc_ldo { regulator-name = "vcc-rtc"; }; @@ -371,7 +368,7 @@ }; &usbphy { - usb0_vbus-supply = <®_ldo_io0>; - usb1_vbus-supply = <®_ldo_io0>; + usb0_vbus-supply = <®_vcc5v0>; + usb1_vbus-supply = <®_vcc5v0>; status = "okay"; }; -- cgit v1.2.3 From 5a5e52161894ab70062e6989aa15f672664334f8 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Sat, 18 Jan 2020 16:24:59 +0100 Subject: arm64: dts: allwinner: a64: Add gpio bank supply for A64-Olinuxino Add the regulators for each bank on this boards. For VCC-PL only add a comment on what regulator is used. We cannot add the property without causing a circular dependency as the PL pins are used to talk to the PMIC. Signed-off-by: Emmanuel Vadot Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index 6dfafa1c879b..5fa9ca0191a8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -158,6 +158,17 @@ */ }; +&pio { + vcc-pa-supply = <®_dcdc1>; + vcc-pb-supply = <®_dcdc1>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_aldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo4>; + vcc-ph-supply = <®_dcdc1>; +}; + &r_rsb { status = "okay"; @@ -170,6 +181,12 @@ }; }; +/* VCC-PL is powered by aldo2 but we cannot add it as the RSB */ +/* interface used to talk to the PMIC in on the PL pins */ +/* &r_pio { */ +/* vcc-pl-supply = <®_aldo2>; */ +/* }; */ + #include "axp803.dtsi" &ac_power_supply { -- cgit v1.2.3 From fc7c2bfb08c36d26b9cad391636566fcdb75fef0 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 10 Feb 2020 18:06:54 +0100 Subject: arm64: dts: allwinner: a64: Add MBUS controller node A64 contains MBUS, which is the bus used by DMA devices to access system memory. MBUS controller is responsible for arbitration between channels based on set priority and can do some other things as well, like report bandwidth used. It also maps RAM region to different address than CPU. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 862b47dc9dc9..251c91724de1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1061,6 +1061,14 @@ status = "disabled"; }; + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>; + clocks = <&ccu 112>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + csi: csi@1cb0000 { compatible = "allwinner,sun50i-a64-csi"; reg = <0x01cb0000 0x1000>; -- cgit v1.2.3 From dd00d78d0f41ec1932d90f23741dbf79b8d8544e Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 10 Feb 2020 18:06:56 +0100 Subject: arm64: dts: allwinner: a64: Add deinterlace core node A64 contains deinterlace core, compatible to the one found in H3. It can be used in combination with VPU unit to decode and process interlaced videos. Add a node for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 251c91724de1..72b1b34879c6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1114,6 +1114,20 @@ #phy-cells = <0>; }; + deinterlace: deinterlace@1e00000 { + compatible = "allwinner,sun50i-a64-deinterlace", + "allwinner,sun8i-h3-deinterlace"; + reg = <0x01e00000 0x20000>; + clocks = <&ccu CLK_BUS_DEINTERLACE>, + <&ccu CLK_DEINTERLACE>, + <&ccu CLK_DRAM_DEINTERLACE>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_DEINTERLACE>; + interrupts = ; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; -- cgit v1.2.3 From 221a690420fdad808eb0b39eebb19d4eda95568c Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 10 Feb 2020 18:40:07 +0100 Subject: arm64: dts: allwinner: h6: orangepi-3: Add eMMC node OrangePi 3 can optionally have 8 GiB eMMC (soldered on board). Because those pins are dedicated to eMMC exclusively, node can be added for both variants (with and without eMMC). Kernel will then scan bus for presence of eMMC and act accordingly. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index c311eee52a35..1e0abd9d047f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -144,6 +144,15 @@ }; }; +&mmc2 { + vmmc-supply = <®_cldo1>; + vqmmc-supply = <®_bldo2>; + cap-mmc-hw-reset; + non-removable; + bus-width = <8>; + status = "okay"; +}; + &ohci0 { status = "okay"; }; -- cgit v1.2.3 From 6be021b1f00d11a420981d711adb2fa9b47c37b9 Mon Sep 17 00:00:00 2001 From: James Liao Date: Wed, 15 Jan 2020 13:42:35 +0800 Subject: arm64: dts: mt8183: Enable CPU idle-states Enable mcdi-cpu and mcdi-cluster on MT8183 CPUs. Signed-off-by: James Liao Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 124f9d3e09f5..504891d2b97b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -74,6 +74,7 @@ reg = <0x000>; enable-method = "psci"; capacity-dmips-mhz = <741>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu1: cpu@1 { @@ -82,6 +83,7 @@ reg = <0x001>; enable-method = "psci"; capacity-dmips-mhz = <741>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu2: cpu@2 { @@ -90,6 +92,7 @@ reg = <0x002>; enable-method = "psci"; capacity-dmips-mhz = <741>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu3: cpu@3 { @@ -98,6 +101,7 @@ reg = <0x003>; enable-method = "psci"; capacity-dmips-mhz = <741>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu4: cpu@100 { @@ -106,6 +110,7 @@ reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu5: cpu@101 { @@ -114,6 +119,7 @@ reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu6: cpu@102 { @@ -122,6 +128,7 @@ reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu7: cpu@103 { @@ -130,6 +137,29 @@ reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x00010001>; + entry-latency-us = <200>; + exit-latency-us = <200>; + min-residency-us = <800>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010001>; + entry-latency-us = <250>; + exit-latency-us = <400>; + min-residency-us = <1300>; + }; }; }; -- cgit v1.2.3 From 31a233a5a17b5405faa7c52700d15cd5b3ef7c52 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 21 Jan 2020 09:18:06 -0800 Subject: arm64: dts: qcom: sdm845: Disable pwrkey on Cheza We don't use the power key from the PMIC on Cheza. Disable this node so that we don't probe the driver for this device. Reviewed-by: Douglas Anderson Cc: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20200121171806.9933-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index dc2ce23cde05..67283d60e2ac 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -45,7 +45,7 @@ mode-bootloader = <0x2>; mode-recovery = <0x1>; - pwrkey { + pm8998_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 7b53b3c7ffe6..a8e9f639a2bb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -626,6 +626,10 @@ ap_ts_i2c: &i2c14 { status = "okay"; }; +&pm8998_pwrkey { + status = "disabled"; +}; + &qupv3_id_0 { status = "okay"; }; -- cgit v1.2.3 From 3d60d80a4162bf015f6efb97f6c17629e21530fe Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Fri, 10 Jan 2020 15:48:02 +0530 Subject: arm64: dts: qcom: sc7180: Add iommus property to QUP0 and QUP1 Define iommus property for QUP0 and QUP1 with the proper SID and mask. Below SMMU global faults are seen without this during boot and when using i2c touchscreen. QUP0: arm-smmu 15000000.iommu: Unexpected global fault, this could be serious arm-smmu 15000000.iommu: GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x00000043, GFSYNR2 0x00000000 QUP1: arm-smmu 15000000.iommu: Unexpected global fault, this could be serious arm-smmu 15000000.iommu: GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000004c3, GFSYNR2 0x00000000 Fixes: ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Tested-by: Stephen Boyd Tested-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/20200110101802.4491-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8011c5fe2a31..01e431f49c18 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -338,6 +338,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; + iommus = <&apps_smmu 0x43 0x0>; status = "disabled"; i2c0: i2c@880000 { @@ -546,6 +547,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; + iommus = <&apps_smmu 0x4c3 0x0>; status = "disabled"; i2c6: i2c@a80000 { -- cgit v1.2.3 From b418cf634cfd9f53d362f2f1be56405860947e31 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 29 Jan 2020 14:44:42 -0800 Subject: arm64: dts: sc7180: Add the sleep_clk to gcc-sc7180 node The bindings say that we're supposed to have this in the node. Who am I to argue with the bindings? Fixes: 90db71e48070 ("arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc") Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20200129144432.1.Ie36f0532f67b0221c1e48e7cf6863a2738716a54@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 01e431f49c18..cc5a94f1f1ba 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -310,8 +310,9 @@ compatible = "qcom,gcc-sc7180"; reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>; - clock-names = "bi_tcxo", "bi_tcxo_ao"; + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; -- cgit v1.2.3 From 8f4a7a00c1019df72cda3002643fb5823ef39183 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 31 Dec 2019 12:25:11 +0100 Subject: arm64: dts: qcom: msm8916-samsung-a2015: Reserve Samsung firmware memory At the moment, writing large amounts of data to the eMMC causes the device to freeze. The symptoms vary, sometimes the device reboots immediately, but usually it will just get stuck. It turns out that the issue is not actually related to the eMMC: Apparently, Samsung has made some modifications to the TrustZone firmware. These require additional memory which is reserved at 0x85500000-0x86000000. The downstream kernel describes this memory reservation as: /* Additionally Reserved 6MB for TIMA and Increased the TZ app size * by 2MB [total 8 MB ] */ This suggests that it is used for additional TZ apps, although the extra memory is actually 11 MB instead of the 8 MB mentioned in the comment. Writing to the protected memory causes the kernel to crash or freeze. In our case, writing to the eMMC causes the disk cache to fill the available RAM, until the kernel eventually crashes when attempting to use the reserved memory. Add the additional memory as reserved-memory to fix this problem. Fixes: 1329c1ab0730 ("arm64: dts: qcom: Add device tree for Samsung Galaxy A3U/A5U") Reported-by: Michael Srba Tested-by: Michael Srba # a3u Tested-by: Stephan Gerhold # a5u Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20191231112511.83342-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index bd1eb3eeca53..43c5e0f882f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -15,6 +15,14 @@ stdout-path = "serial0"; }; + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + soc { sdhci@7824000 { status = "okay"; -- cgit v1.2.3 From 92c2701ec1f5aa0eef4af44a2ac80c1c9d8aa112 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 15 Jan 2020 09:39:08 +0800 Subject: arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default Enable CONFIG_PINCTRL_IMX8MP by default to support i.MX8MP pinctrl driver. Signed-off-by: Anson Huang Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0f212889c931..1c744379c9c7 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -409,6 +409,7 @@ CONFIG_PINCTRL_S700=y CONFIG_PINCTRL_S900=y CONFIG_PINCTRL_IMX8MM=y CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IPQ8074=y -- cgit v1.2.3 From b568627307dfe1e4f6b0bd8c9a95550ac12351cd Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 12 Feb 2020 14:05:37 +0800 Subject: arm64: dts: mt8173: add arm,no-tick-in-suspend in timer Arch timer stops during system suspend. Add arm,no-tick-in-suspend property in timer. This is a follow up for d8ec7595a013 ("clocksource/drivers/arm_arch_timer: Don't assume clock runs in suspend") Signed-off-by: Hsin-Yi Wang Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 8b4e806d5119..1a9ad90bd7a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -331,6 +331,7 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + arm,no-tick-in-suspend; }; soc { -- cgit v1.2.3 From 6f7e1c1929e0ae0d088cc1f7b5174a8faa7bd711 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 7 Feb 2020 15:13:24 +0100 Subject: arm64: dts: rk3399: Remove extcon unit address and extcon-cells from Gru The cros-ec-extcon has no reg property so remove the unit address from the DT node to make DT compiler happy. While here, remove the inexistent extcon-cells property from the extcon nodes. Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20200207141324.3188898-1-enric.balletbo@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 4 +--- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 7cd6d470c1cb..1384dabbdf40 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -291,11 +291,9 @@ ap_i2c_tp: &i2c5 { #pwm-cells = <1>; }; - usbc_extcon1: extcon@1 { + usbc_extcon1: extcon1 { compatible = "google,extcon-usbc-cros-ec"; google,usb-port-id = <1>; - - #extcon-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index dd5624975c9b..2f3997740068 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -570,11 +570,9 @@ ap_i2c_audio: &i2c8 { #size-cells = <0>; }; - usbc_extcon0: extcon@0 { + usbc_extcon0: extcon0 { compatible = "google,extcon-usbc-cros-ec"; google,usb-port-id = <0>; - - #extcon-cells = <0>; }; }; }; -- cgit v1.2.3 From e5ab00edc3d5c4cf90aa0bc918bfe87ee47a6990 Mon Sep 17 00:00:00 2001 From: Alexis Ballier Date: Thu, 6 Feb 2020 16:10:24 +0100 Subject: arm64: dts: rockchip: Add ethernet phy to rk3399-orangepi Enables INTB. The wiring is the same as the nanopi4, so this is heavily based on: - [1a4e6203f0c] arm64: dts: rockchip: Add nanopi4 ethernet phy - [bc43cee88aa] arm64: dts: rockchip: Update nanopi4 phy reset properties by Robin Murphy. Signed-off-by: Alexis Ballier Cc: devicetree@vger.kernel.org Cc: Heiko Stuebner Cc: Robin Murphy Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/20200206151025.3813-1-aballier@gentoo.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 31 +++++++++++++++++++++--- 1 file changed, 27 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts index 9c659f3115c8..1767015e684c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts @@ -202,14 +202,27 @@ clock_in_out = "input"; phy-supply = <&vcc3v3_s3>; phy-mode = "rgmii"; + phy-handle = <&rtl8211e>; pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; + pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; tx_delay = <0x28>; rx_delay = <0x11>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; }; &gpu { @@ -537,6 +550,16 @@ }; }; + phy { + phy_intb: phy-intb { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = -- cgit v1.2.3 From dbb0a828e9ab5198bd0bb249f074d86910e123f6 Mon Sep 17 00:00:00 2001 From: Alexis Ballier Date: Thu, 6 Feb 2020 16:10:25 +0100 Subject: arm64: dts: rockchip: Explicitly pinmux the regulator configuration GPIOs on rk3399-orangepi Those GPIOs define which register is used by the GPU & CPUB regulators for sleep mode. The register is defined here, so better have the GPIOs explicitly set too. Signed-off-by: Alexis Ballier Cc: devicetree@vger.kernel.org Cc: Heiko Stuebner Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/20200206151025.3813-2-aballier@gentoo.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts index 1767015e684c..f9f7246d4d2f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts @@ -432,6 +432,8 @@ compatible = "silergy,syr827"; reg = <0x40>; fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -449,6 +451,8 @@ compatible = "silergy,syr828"; reg = <0x41>; fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -561,6 +565,14 @@ }; pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -- cgit v1.2.3 From 42ef961b247f340f365b096e25983b4ee256f3ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Horia=20Geant=C4=83?= Date: Thu, 16 Jan 2020 09:37:18 +0200 Subject: arm64: dts: imx8mn: add clock for snvs rtc node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initial commit adding imx8mn support: 6c3debcbae47 ("arm64: dts: freescale: Add i.MX8MN dtsi support") added the "clock-names" property for the snvs rtc node, however it missed adding the clock. Signed-off-by: Horia Geantă Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index a44b5438e842..d23347aaedda 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -358,6 +358,7 @@ offset = <0x34>; interrupts = , ; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; clock-names = "snvs-rtc"; }; -- cgit v1.2.3 From 815364d0424e72cde1d16f2ef3a75cd8e48411bf Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 10 Dec 2019 00:43:50 +0100 Subject: arm64: dts: freescale: add Kontron sl28 support Add device tree files for the Kontron SMARC-sAL28 board and its carriers. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../fsl-ls1028a-kontron-kbox-a-230-ls.dts | 27 ++++ .../fsl-ls1028a-kontron-sl28-var3-ads2.dts | 106 +++++++++++++ .../freescale/fsl-ls1028a-kontron-sl28-var4.dts | 50 ++++++ .../dts/freescale/fsl-ls1028a-kontron-sl28.dts | 174 +++++++++++++++++++++ 5 files changed, 361 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index bac293e6ee33..6088e3629151 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -4,6 +4,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts new file mode 100644 index 000000000000..aaf3c04771c3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree File for the Kontron KBox A-230-LS. + * + * This consists of a Kontron SMARC-sAL28 (Dual PHY) and a special + * carrier (s1914). + * + * Copyright (C) 2019 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28-var4.dts" + +/ { + model = "Kontron KBox A-230-LS"; + compatible = "kontron,kbox-a-230-ls", "kontron,sl28-var4", + "kontron,sl28", "fsl,ls1028a"; +}; + +&i2c4 { + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts new file mode 100644 index 000000000000..7de55f2aa7dc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0 + * carrier (ADS2). + * + * Copyright (C) 2019 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" + +/ { + model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier"; + compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3", + "kontron,sl28", "fsl,ls1028a"; + + sound { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-audio-card"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out Jack", + "Microphone", "Microphone Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "LINEOUTR", + "Line Out Jack", "LINEOUTL", + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "IN1L", "Line In Jack", + "IN1R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN2L", "Microphone Jack", + "IN2R", "Microphone Jack"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,dai-link@0 { + reg = <0>; + bitclock-master = <&dailink0_master>; + frame-master = <&dailink0_master>; + format = "i2s"; + + cpu { + sound-dai = <&sai6>; + }; + + dailink0_master: codec { + sound-dai = <&wm8904>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + bitclock-master = <&dailink1_master>; + frame-master = <&dailink1_master>; + format = "i2s"; + + cpu { + sound-dai = <&sai5>; + }; + + dailink1_master: codec { + sound-dai = <&wm8904>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + wm8904: audio-codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&mclk>; + clock-names = "mclk"; + assigned-clocks = <&mclk>; + assigned-clock-rates = <1250000>; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&sai5 { + status = "okay"; +}; + +&sai6 { + status = "okay"; +}; + +&soc { + mclk: clock-mclk@f130080 { + compatible = "fsl,vf610-sai-clock"; + reg = <0x0 0xf130080 0x0 0x80>; + clocks = <&clockgen 4 1>; + #clock-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts new file mode 100644 index 000000000000..f659e89face8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 4 which has two ethernet ports. It + * extends the base and provides one more port connected via RGMII. + * + * Copyright (C) 2019 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" +#include + +/ { + model = "Kontron SMARC-sAL28 (Dual PHY)"; + compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; +}; + +&enetc_port1 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = ; + + vddio-supply = <&vddh>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts new file mode 100644 index 000000000000..d221ed471cde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * Copyright (C) 2019 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a.dtsi" + +/ { + model = "Kontron SMARC-sAL28"; + compatible = "kontron,sl28", "fsl,ls1028a"; + + aliases { + crypto = &crypto; + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&enetc_port0 { + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@5 { + reg = <0x5>; + eee-broken-1000t; + eee-broken-100tx; + }; + }; +}; + +&esdhc { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; + status = "okay"; +}; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + m25p,fast-read; + spi-max-frequency = <133000000>; + reg = <0>; + /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ + spi-tx-bus-width = <1>; /* 1 SPI Tx line */ + + partition@0 { + reg = <0x000000 0x010000>; + label = "rcw"; + read-only; + }; + + partition@10000 { + reg = <0x010000 0x0f0000>; + label = "failsafe bootloader"; + read-only; + }; + + partition@100000 { + reg = <0x100000 0x040000>; + label = "failsafe DP firmware"; + read-only; + }; + + partition@140000 { + reg = <0x140000 0x0a0000>; + label = "failsafe trusted firmware"; + read-only; + }; + + partition@1e0000 { + reg = <0x1e0000 0x020000>; + label = "reserved"; + read-only; + }; + + partition@200000 { + reg = <0x200000 0x010000>; + label = "configuration store"; + }; + + partition@210000 { + reg = <0x210000 0x0f0000>; + label = "bootloader"; + }; + + partition@300000 { + reg = <0x300000 0x040000>; + label = "DP firmware"; + }; + + partition@340000 { + reg = <0x340000 0x0a0000>; + label = "trusted firmware"; + }; + + partition@3e0000 { + reg = <0x3e0000 0x020000>; + label = "bootloader environment"; + }; + }; +}; + +&gpio1 { + gpio-line-name