From 88affa2f891bcbe39fc773e61bf6c90b78756bdc Mon Sep 17 00:00:00 2001 From: Kalyani Akula Date: Mon, 17 Feb 2020 15:56:44 +0530 Subject: arm64: zynqmp: Add Xilinx AES node This patch adds a AES DT node for Xilinx ZynqMP SoC. Signed-off-by: Kalyani Akula Acked-by: Michal Simek Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 26d926eb1431..de4c694ee7af 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -158,6 +158,10 @@ zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; + + xlnx_aes: zynqmp-aes { + compatible = "xlnx,zynqmp-aes"; + }; }; }; -- cgit v1.2.3 From 31888c8be1486daf2c34ba6c58129635e49d564a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 11 Nov 2019 03:00:26 +0100 Subject: arm64: dts: realtek: rtd129x: Fix GIC CPU masks for RTD1293 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert from GIC_CPU_MASK_RAW() to GIC_CPU_MASK_SIMPLE(). In case of RTD1293 adjust the arch timer and VGIC interrupts' CPU masks to its smaller number of CPUs. Fixes: cf976f660ee8 ("arm64: dts: realtek: Add RTD1293 and Synology DS418j") Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd1293.dtsi | 12 ++++++++---- arch/arm64/boot/dts/realtek/rtd1295.dtsi | 8 ++++---- arch/arm64/boot/dts/realtek/rtd1296.dtsi | 8 ++++---- 3 files changed, 16 insertions(+), 12 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi index bd4e22723f7b..2d92b56ac94d 100644 --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi @@ -36,16 +36,20 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; &arm_pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; + +&gic { + interrupts = ; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 93f0e1d97721..34f6cc6f16fe 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -61,13 +61,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi index 0f9e59cac086..fb864a139c97 100644 --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi @@ -50,13 +50,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; -- cgit v1.2.3 From 690677c22d5fa5dfdaa609a1739b75fdfb1c4a24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 10 Nov 2019 07:02:43 +0100 Subject: arm64: dts: realtek: rtd129x: Use reserved-memory for RPC regions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move /reserved-memory node from RTD1295 to RTD129x DT. Convert RPC /memreserve/s into /reserved-memory nodes. Fixes: 72a7786c0a0d ("ARM64: dts: Add Realtek RTD1295 and Zidoo X9S") Fixes: f8b3436dad5c ("arm64: dts: realtek: Factor out common RTD129x parts") Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd1295.dtsi | 13 +------------ arch/arm64/boot/dts/realtek/rtd129x.dtsi | 23 ++++++++++++++++++++--- 2 files changed, 21 insertions(+), 15 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 34f6cc6f16fe..1402abe80ea1 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -2,7 +2,7 @@ /* * Realtek RTD1295 SoC * - * Copyright (c) 2016-2017 Andreas Färber + * Copyright (c) 2016-2019 Andreas Färber */ #include "rtd129x.dtsi" @@ -47,17 +47,6 @@ }; }; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tee@10100000 { - reg = <0x10100000 0xf00000>; - no-map; - }; - }; - timer { compatible = "arm,armv8-timer"; interrupts = #include @@ -19,6 +17,25 @@ #address-cells = <1>; #size-cells = <1>; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@1f000 { + reg = <0x1f000 0x1000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x1ffe000 0x4000>; + }; + + tee: tee@10100000 { + reg = <0x10100000 0xf00000>; + no-map; + }; + }; + arm_pmu: arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; -- cgit v1.2.3 From 6d2fdb241005807735a445f96dbcd2b5fefeb1ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 10 Nov 2019 01:17:29 +0100 Subject: arm64: dts: realtek: rtd129x: Introduce r-bus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Model Realtek's register bus in DT. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd129x.dtsi | 136 ++++++++++++++++--------------- 1 file changed, 72 insertions(+), 64 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 8d80cca945bc..5e755dda7abb 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -55,70 +55,78 @@ /* Exclude up to 2 GiB of RAM */ ranges = <0x80000000 0x80000000 0x80000000>; - reset1: reset-controller@98000000 { - compatible = "snps,dw-low-reset"; - reg = <0x98000000 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@98000004 { - compatible = "snps,dw-low-reset"; - reg = <0x98000004 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@98000008 { - compatible = "snps,dw-low-reset"; - reg = <0x98000008 0x4>; - #reset-cells = <1>; - }; - - reset4: reset-controller@98000050 { - compatible = "snps,dw-low-reset"; - reg = <0x98000050 0x4>; - #reset-cells = <1>; - }; - - iso_reset: reset-controller@98007088 { - compatible = "snps,dw-low-reset"; - reg = <0x98007088 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@98007680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x98007680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@98007800 { - compatible = "snps,dw-apb-uart"; - reg = <0x98007800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; - }; - - uart1: serial@9801b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; - }; - - uart2: serial@9801b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b400 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; + rbus: bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; + + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; + + iso_reset: reset-controller@7088 { + compatible = "snps,dw-low-reset"; + reg = <0x7088 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@7680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x7680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; + + uart1: serial@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@1b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; }; gic: interrupt-controller@ff011000 { -- cgit v1.2.3 From 3040e132beda2aee56e6ea9be8db69889bcb2e7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 30 Nov 2019 19:20:53 +0100 Subject: arm64: dts: realtek: rtd129x: Carve out boot ROM from memory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update DS418j, MeLE V9, PROBOX2 AVA, Zidoo X9S and DS418 /memory nodes to exclude 0..0x1efff from reg entry and update unit address to match. Add this region to /soc ranges and for now just update the /memreserve/s. Suggested-by: Rob Herring Fixes: 72a7786c0a0d ("ARM64: dts: Add Realtek RTD1295 and Zidoo X9S") Fixes: d938a964a966 ("arm64: dts: realtek: Add ProBox2 Ava") Fixes: a9ce6f854581 ("arm64: dts: realtek: Add MeLE V9") Fixes: cf976f660ee8 ("arm64: dts: realtek: Add RTD1293 and Synology DS418j") Fixes: 5133636e41a2 ("arm64: dts: realtek: Add RTD1296 and Synology DS418") Cc: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts | 6 +++--- arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts | 6 +++--- arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts | 6 +++--- arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts | 4 ++-- arch/arm64/boot/dts/realtek/rtd1296-ds418.dts | 4 ++-- arch/arm64/boot/dts/realtek/rtd129x.dtsi | 9 +++++---- 6 files changed, 18 insertions(+), 17 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts b/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts index b2dd583146b4..b2e44c6c2d22 100644 --- a/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts +++ b/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) /* - * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2017-2019 Andreas Färber */ /dts-v1/; @@ -11,9 +11,9 @@ compatible = "synology,ds418j", "realtek,rtd1293"; model = "Synology DiskStation DS418j"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x40000000>; + reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB */ }; aliases { diff --git a/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts b/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts index bd584e99fff9..cf4a57c012a8 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts +++ b/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2017-2019 Andreas Färber * * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ @@ -12,9 +12,9 @@ compatible = "mele,v9", "realtek,rtd1295"; model = "MeLE V9"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ }; aliases { diff --git a/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts b/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts index 8e2b0e75298a..14161c3f304d 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts +++ b/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2017-2019 Andreas Färber * * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ @@ -12,9 +12,9 @@ compatible = "probox2,ava", "realtek,rtd1295"; model = "PROBOX2 AVA"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ }; aliases { diff --git a/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts b/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts index e98e508b9514..4beb37bb9522 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts +++ b/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts @@ -11,9 +11,9 @@ compatible = "zidoo,x9s", "realtek,rtd1295"; model = "Zidoo X9S"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ }; aliases { diff --git a/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts b/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts index 5a051a52bf88..cc706d13da8b 100644 --- a/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts +++ b/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts @@ -11,9 +11,9 @@ compatible = "synology,ds418", "realtek,rtd1296"; model = "Synology DiskStation DS418"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ }; aliases { diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 5e755dda7abb..0de9e675be16 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -5,8 +5,8 @@ * Copyright (c) 2016-2019 Andreas Färber */ -/memreserve/ 0x0000000000000000 0x0000000000030000; -/memreserve/ 0x0000000000030000 0x00000000000d0000; +/memreserve/ 0x0000000000000000 0x000000000001f000; +/memreserve/ 0x000000000001f000 0x00000000000e1000; /memreserve/ 0x0000000001b00000 0x00000000004be000; #include @@ -52,8 +52,9 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - /* Exclude up to 2 GiB of RAM */ - ranges = <0x80000000 0x80000000 0x80000000>; + ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ + /* Exclude up to 2 GiB of RAM */ + <0x80000000 0x80000000 0x80000000>; rbus: bus@98000000 { compatible = "simple-bus"; -- cgit v1.2.3 From 769c00a2f10b4f43fe764077a48d9a594010686b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 7 Nov 2019 07:34:22 +0100 Subject: arm64: dts: realtek: Add RTD1395 and BPi-M4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Device Trees for Realtek RTD1395 SoC and Banana Pi BPi-M4 SBC. For now reuse RTD1295 reset constants. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/Makefile | 2 + arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts | 30 ++++++ arch/arm64/boot/dts/realtek/rtd1395.dtsi | 65 +++++++++++ arch/arm64/boot/dts/realtek/rtd139x.dtsi | 142 +++++++++++++++++++++++++ 4 files changed, 239 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1395.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd139x.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index 555638ada721..edc85ee8c4bf 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -7,3 +7,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb + +dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts b/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts new file mode 100644 index 000000000000..9891967d1315 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1395.dtsi" + +/ { + compatible = "bananapi,bpi-m4", "realtek,rtd1395"; + model = "Banana Pi BPI-M4"; + + memory@2f000 { + device_type = "memory"; + reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi new file mode 100644 index 000000000000..05c9216a87ee --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1395 SoC + * + * Copyright (c) 2019 Andreas Färber + */ + +#include "rtd139x.dtsi" + +/ { + compatible = "realtek,rtd1395"; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi new file mode 100644 index 000000000000..c11a505e43e2 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1395 SoC family + * + * Copyright (c) 2019 Andreas Färber + */ + +/memreserve/ 0x0000000000000000 0x000000000002f000; +/memreserve/ 0x000000000002f000 0x00000000000d1000; + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@2f000 { + reg = <0x2f000 0x1000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x1ffe000 0x4000>; + }; + + tee: tee@10100000 { + reg = <0x10100000 0xf00000>; + no-map; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + clock-output-names = "osc27M"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ + <0x98000000 0x98000000 0x68000000>; + + rbus: bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; + + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; + + iso_reset: reset-controller@7088 { + compatible = "snps,dw-low-reset"; + reg = <0x7088 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@7680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x7680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; + + uart1: serial@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@1b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff011000 { + compatible = "arm,gic-400"; + reg = <0xff011000 0x1000>, + <0xff012000 0x2000>, + <0xff014000 0x2000>, + <0xff016000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; -- cgit v1.2.3 From 50a87ad8cd6aa963211c8f526dce1fa9ab0a9288 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 26 Nov 2019 04:21:53 +0100 Subject: arm64: dts: realtek: rtd1395: Add Realtek Lion Skin EVB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a Device Tree for Realtek RTD1395 SoC Lion Skin evaluation board. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/Makefile | 1 + arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts | 36 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index edc85ee8c4bf..55690b14b98a 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -9,3 +9,4 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb +dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts b/arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts new file mode 100644 index 000000000000..83f9b536cdea --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1395.dtsi" + +/ { + compatible = "realtek,lion-skin", "realtek,rtd1395"; + model = "Realtek Lion Skin EVB"; + + memory@2f000 { + device_type = "memory"; + reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* debug console (J1) */ +&uart0 { + status = "okay"; +}; + +/* M.2 slot (CON1) */ +&uart1 { + status = "disabled"; +}; -- cgit v1.2.3 From d8a6c3b3427618dc7441ec9eb180405ec30f3413 Mon Sep 17 00:00:00 2001 From: James Tai Date: Tue, 12 Nov 2019 15:45:22 +0000 Subject: arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Device Trees for Realtek RTD1619 SoC family, RTD1619 SoC and Realtek Mjolnir EVB. Signed-off-by: James Tai [AF: Renamed r-bus node, modified UART comments, style cleanups] Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/Makefile | 2 + arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts | 43 +++++++ arch/arm64/boot/dts/realtek/rtd1619.dtsi | 12 ++ arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 159 ++++++++++++++++++++++++ 4 files changed, 216 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1619.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd16xx.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index 55690b14b98a..54bd02d11c02 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -10,3 +10,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb + +dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts new file mode 100644 index 000000000000..44dd67e04335 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1619.dtsi" + +/ { + compatible = "realtek,mjolnir", "realtek,rtd1619"; + model = "Realtek Mjolnir EVB"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; +}; + +/* debug console (J1) */ +&uart0 { + status = "okay"; +}; + +/* M.2 slot (CON4) */ +&uart1 { + status = "disabled"; +}; + +/* GPIO connector (T1) */ +&uart2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1619.dtsi b/arch/arm64/boot/dts/realtek/rtd1619.dtsi new file mode 100644 index 000000000000..e52bf708b04e --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1619 SoC + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include "rtd16xx.dtsi" + +/ { + compatible = "realtek,rtd1619"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi new file mode 100644 index 000000000000..c7bbf2c7bb7c --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD16xx SoC family + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + l2: l2-cache { + compatible = "cache"; + next-level-cache = <&l3>; + + }; + + l3: l3-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + arm_pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, + <&cpu3>, <&cpu4>, <&cpu5>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "osc27M"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x68000000>; + + rbus: bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; + + uart0: serial0@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial1@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <432000000>; + status = "disabled"; + }; + + uart2: serial2@1b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b400 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <432000000>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + reg = <0xff100000 0x10000>, + <0xff140000 0xc0000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; -- cgit v1.2.3 From 44955042b512bd1ae748cc33bb45ecfe29c97967 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 30 Nov 2019 20:00:58 +0100 Subject: arm64: dts: realtek: rtd16xx: Carve out boot ROM from memory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update Mjolnir /memory node to exclude 0..0x2dfff from reg entry. Add this region to /soc ranges instead. Fixes: d8a6c3b34276 ("arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB") Suggested-by: Rob Herring Cc: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts | 5 +++-- arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 4 +++- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts index 44dd67e04335..90ed6681468f 100644 --- a/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts +++ b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) /* * Copyright (c) 2019 Realtek Semiconductor Corp. + * Copyright (c) 2019 Andreas Färber */ /dts-v1/; @@ -11,9 +12,9 @@ compatible = "realtek,mjolnir", "realtek,rtd1619"; model = "Realtek Mjolnir EVB"; - memory@0 { + memory@2e000 { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x2e000 0x7ffd2000>; /* boot ROM to 2 GiB */ }; chosen { diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index c7bbf2c7bb7c..69cc0d941c8d 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -3,6 +3,7 @@ * Realtek RTD16xx SoC family * * Copyright (c) 2019 Realtek Semiconductor Corp. + * Copyright (c) 2019 Andreas Färber */ #include @@ -107,7 +108,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x68000000>; + ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */ + <0x98000000 0x98000000 0x68000000>; rbus: bus@98000000 { compatible = "simple-bus"; -- cgit v1.2.3 From 0d874aad940d60e2763fa95a1d5cb352d5b60b7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sat, 23 Nov 2019 01:54:02 +0100 Subject: arm64: dts: realtek: rtd16xx: Add memory reservations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reserve memory regions for RPC and TEE. Fixes: d8a6c3b34276 ("arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB") Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index 69cc0d941c8d..47e65fe50df3 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -14,6 +14,25 @@ #address-cells = <1>; #size-cells = <1>; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@2f000 { + reg = <0x2f000 0x1000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x1ffe000 0x4000>; + }; + + tee: tee@10100000 { + reg = <0x10100000 0xf00000>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From e557f4b0ba860aa1d449ad543484a2306393d919 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 8 Dec 2019 15:54:36 +0100 Subject: arm64: dts: realtek: rtd1295: Add Xnano X5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Xnano X5 is an OTT TV Box. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/Makefile | 1 + arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts | 30 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index 54bd02d11c02..ef8d8fcbaa05 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb +dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts b/arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts new file mode 100644 index 000000000000..d7878ff942e6 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1295.dtsi" + +/ { + compatible = "xnano,x5", "realtek,rtd1295"; + model = "Xnano X5"; + + memory@1f000 { + device_type = "memory"; + reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB or 2 GiB */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From 9e7c2a1caf2517f8c8594aceaeba6e40c7906ab4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 24 Nov 2019 02:06:25 +0100 Subject: arm64: dts: realtek: rtd129x: Introduce CRT, iso and misc syscon MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group the non-iso reset controller nodes in a CRT syscon mfd node. Group reset controller, watchdog and UART0 in an Isolation syscon mfd node. Group UART1 and UART2 into a Miscellaneous syscon mfd node. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd129x.dtsi | 147 +++++++++++++++++++------------ 1 file changed, 90 insertions(+), 57 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 0de9e675be16..34dc09790d0b 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -63,70 +63,31 @@ #size-cells = <1>; ranges = <0x0 0x98000000 0x200000>; - reset1: reset-controller@0 { - compatible = "snps,dw-low-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@4 { - compatible = "snps,dw-low-reset"; - reg = <0x4 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@8 { - compatible = "snps,dw-low-reset"; - reg = <0x8 0x4>; - #reset-cells = <1>; - }; - - reset4: reset-controller@50 { - compatible = "snps,dw-low-reset"; - reg = <0x50 0x4>; - #reset-cells = <1>; - }; - - iso_reset: reset-controller@7088 { - compatible = "snps,dw-low-reset"; - reg = <0x7088 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@7680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x7680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@7800 { - compatible = "snps,dw-apb-uart"; - reg = <0x7800 0x400>; - reg-shift = <2>; + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1800>; reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1800>; }; - uart1: serial@1b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x1b200 0x100>; - reg-shift = <2>; + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; }; - uart2: serial@1b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x1b400 0x100>; - reg-shift = <2>; + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; }; }; @@ -142,3 +103,75 @@ }; }; }; + +&crt { + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; +}; + +&iso { + iso_reset: reset-controller@88 { + compatible = "snps,dw-low-reset"; + reg = <0x88 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@400 { + compatible = "snps,dw-apb-uart"; + reg = <0x400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; +}; -- cgit v1.2.3 From a5360a35772f4a621afc2c9b19eb99950a3e207b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 24 Nov 2019 02:23:09 +0100 Subject: arm64: dts: realtek: rtd139x: Introduce CRT, iso and misc syscon MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group the non-iso reset controller nodes into a CRT syscon mfd node. Group reset controller, watchdog and UART0 into an Isolation mfd node. Group UART1 and UART2 into a Miscellaneous syscon mfd node. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd139x.dtsi | 147 +++++++++++++++++++------------ 1 file changed, 90 insertions(+), 57 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi index c11a505e43e2..3a571f3b7e38 100644 --- a/arch/arm64/boot/dts/realtek/rtd139x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi @@ -61,70 +61,31 @@ #size-cells = <1>; ranges = <0x0 0x98000000 0x200000>; - reset1: reset-controller@0 { - compatible = "snps,dw-low-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@4 { - compatible = "snps,dw-low-reset"; - reg = <0x4 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@8 { - compatible = "snps,dw-low-reset"; - reg = <0x8 0x4>; - #reset-cells = <1>; - }; - - reset4: reset-controller@50 { - compatible = "snps,dw-low-reset"; - reg = <0x50 0x4>; - #reset-cells = <1>; - }; - - iso_reset: reset-controller@7088 { - compatible = "snps,dw-low-reset"; - reg = <0x7088 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@7680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x7680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@7800 { - compatible = "snps,dw-apb-uart"; - reg = <0x7800 0x400>; - reg-shift = <2>; + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1000>; reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; }; - uart1: serial@1b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x1b200 0x100>; - reg-shift = <2>; + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; }; - uart2: serial@1b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x1b400 0x100>; - reg-shift = <2>; + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; }; }; @@ -140,3 +101,75 @@ }; }; }; + +&crt { + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; +}; + +&iso { + iso_reset: reset-controller@88 { + compatible = "snps,dw-low-reset"; + reg = <0x88 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@400 { + compatible = "snps,dw-apb-uart"; + reg = <0x400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; +}; -- cgit v1.2.3 From cc022ebcaf747fdff15a6e25e1e164d4069cd37c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 26 Nov 2019 07:11:18 +0100 Subject: arm64: dts: realtek: rtd16xx: Introduce iso and misc syscon MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group UART0 into an Isolation syscon mfd node. Group UART1 and UART2 into a Miscellaneous syscon mfd node. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 70 +++++++++++++++++++++----------- 1 file changed, 46 insertions(+), 24 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index 47e65fe50df3..5d81dbff3ca9 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -137,34 +137,22 @@ #size-cells = <1>; ranges = <0x0 0x98000000 0x200000>; - uart0: serial0@7800 { - compatible = "snps,dw-apb-uart"; - reg = <0x7800 0x400>; - reg-shift = <2>; + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; reg-io-width = <4>; - interrupts = ; - clock-frequency = <27000000>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; }; - uart1: serial1@1b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x1b200 0x400>; - reg-shift = <2>; + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; reg-io-width = <4>; - interrupts = ; - clock-frequency = <432000000>; - status = "disabled"; - }; - - uart2: serial2@1b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x1b400 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <432000000>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; }; }; @@ -178,3 +166,37 @@ }; }; }; + +&iso { + uart0: serial0@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial1@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <432000000>; + status = "disabled"; + }; + + uart2: serial2@400 { + compatible = "snps,dw-apb-uart"; + reg = <0x400 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <432000000>; + status = "disabled"; + }; +}; -- cgit v1.2.3 From 4b1b26deeb58b2d16eb7b2f8f5ce25345761f6da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 24 Nov 2019 02:29:27 +0100 Subject: arm64: dts: realtek: rtd16xx: Add CRT syscon node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prepare a CRT syscon mfd node. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index 5d81dbff3ca9..7b13496ba3ca 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -137,6 +137,15 @@ #size-cells = <1>; ranges = <0x0 0x98000000 0x200000>; + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + iso: syscon@7000 { compatible = "syscon", "simple-mfd"; reg = <0x7000 0x1000>; -- cgit v1.2.3 From 6de1aced8bd6e2f8b75da7533299a281fbb1783c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 25 Nov 2019 07:40:34 +0100 Subject: arm64: dts: realtek: rtd129x: Add SB2 and SCPU Wrapper syscon nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add syscon mfd nodes for SB2 and SCPU Wrapper to RTD129x DT. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd129x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 34dc09790d0b..39aefe66a794 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -81,6 +81,15 @@ ranges = <0x0 0x7000 0x1000>; }; + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + misc: syscon@1b000 { compatible = "syscon", "simple-mfd"; reg = <0x1b000 0x1000>; @@ -89,6 +98,15 @@ #size-cells = <1>; ranges = <0x0 0x1b000 0x1000>; }; + + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x2000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x2000>; + }; }; gic: interrupt-controller@ff011000 { -- cgit v1.2.3 From dd473726dc799a1a62d687fb2a6aa5c55815f061 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 25 Nov 2019 07:42:57 +0100 Subject: arm64: dts: realtek: rtd139x: Add SB2 and SCPU Wrapper syscon nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add syscon mfd nodes for SB2 and SCPU Wrapper to RTD139x DT. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd139x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi index 3a571f3b7e38..a3c10ceeb586 100644 --- a/arch/arm64/boot/dts/realtek/rtd139x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi @@ -79,6 +79,15 @@ ranges = <0x0 0x7000 0x1000>; }; + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + misc: syscon@1b000 { compatible = "syscon", "simple-mfd"; reg = <0x1b000 0x1000>; @@ -87,6 +96,15 @@ #size-cells = <1>; ranges = <0x0 0x1b000 0x1000>; }; + + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x2000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x2000>; + }; }; gic: interrupt-controller@ff011000 { -- cgit v1.2.3 From e624119013bf4f10df233d2534c91eab9642911d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 25 Nov 2019 07:45:43 +0100 Subject: arm64: dts: realtek: rtd16xx: Add SB2 and SCPU Wrapper syscon nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add syscon mfd nodes for SB2 and SCPU Wrapper to RTD16xx DT. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index 7b13496ba3ca..afba5f04c8ec 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -155,6 +155,15 @@ ranges = <0x0 0x7000 0x1000>; }; + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + misc: syscon@1b000 { compatible = "syscon", "simple-mfd"; reg = <0x1b000 0x1000>; @@ -163,6 +172,15 @@ #size-cells = <1>; ranges = <0x0 0x1b000 0x1000>; }; + + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x1000>; + }; }; gic: interrupt-controller@ff100000 { -- cgit v1.2.3 From 1ba2ed77210ab9d4d0995cce0d2ef2cae742bd09 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Mon, 30 Mar 2020 06:53:40 +0800 Subject: arm64: dts: mt7622: add built-in Wi-Fi device nodes This enables built-in 802.11n Wi-Fi support. It's 2.4GHz only. Signed-off-by: Ryder Lee Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 11 +++++++++++ 3 files changed, 19 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 83e10591e0e5..d174ad214857 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -543,3 +543,7 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; + +&wmac { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 3f783348c66a..0b4de627f96e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -506,3 +506,7 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; + +&wmac { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 339dc9f88f43..1a39e0ef776b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -699,6 +699,17 @@ status = "disabled"; }; + wmac: wmac@18000000 { + compatible = "mediatek,mt7622-wmac"; + reg = <0 0x18000000 0 0x100000>; + interrupts = ; + + mediatek,infracfg = <&infracfg>; + status = "disabled"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; + }; + ssusbsys: ssusbsys@1a000000 { compatible = "mediatek,mt7622-ssusbsys", "syscon"; -- cgit v1.2.3 From eb4a01afedf64bf0f44f0dbd9fee87d917eb4a13 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Thu, 9 Apr 2020 13:50:12 +0800 Subject: arm64: dts: mt8173: Add gce setting in mmsys and display node In order to use GCE function, we need add some informations into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events). Signed-off-by: Hsin-Yi Wang Tested-by: Enric Balletbo i Serra Reviewed-by: Bibby Hsieh Reviewed-by: Chun-Kuang Hu Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index ccb8e88a60c5..8337ba42845d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -549,7 +549,7 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; - #mbox-cells = <3>; + #mbox-cells = <2>; }; mipi_tx0: mipi-dphy@10215000 { @@ -916,6 +916,9 @@ assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; assigned-clock-rates = <400000000>; #clock-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; mdp_rdma0: rdma@14001000 { @@ -996,6 +999,7 @@ clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; ovl1: ovl@1400d000 { @@ -1006,6 +1010,7 @@ clocks = <&mmsys CLK_MM_DISP_OVL1>; iommus = <&iommu M4U_PORT_DISP_OVL1>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; rdma0: rdma@1400e000 { @@ -1016,6 +1021,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; rdma1: rdma@1400f000 { @@ -1026,6 +1032,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; rdma2: rdma@14010000 { @@ -1036,6 +1043,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA2>; iommus = <&iommu M4U_PORT_DISP_RDMA2>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; wdma0: wdma@14011000 { @@ -1046,6 +1054,7 @@ clocks = <&mmsys CLK_MM_DISP_WDMA0>; iommus = <&iommu M4U_PORT_DISP_WDMA0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; wdma1: wdma@14012000 { @@ -1056,6 +1065,7 @@ clocks = <&mmsys CLK_MM_DISP_WDMA1>; iommus = <&iommu M4U_PORT_DISP_WDMA1>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; color0: color@14013000 { @@ -1064,6 +1074,7 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; }; color1: color@14014000 { @@ -1072,6 +1083,7 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; }; aal@14015000 { @@ -1080,6 +1092,7 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_AAL>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; }; gamma@14016000 { @@ -1088,6 +1101,7 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_GAMMA>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; }; merge@14017000 { @@ -1193,6 +1207,8 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_MUTEX_32K>; + mediatek,gce-events = , + ; }; larb0: larb@14021000 { -- cgit v1.2.3 From 6b55297581eaf4f1850b4d25b29dd55a239272cc Mon Sep 17 00:00:00 2001 From: Ikjoon Jang Date: Tue, 25 Feb 2020 16:07:53 +0800 Subject: arm64: dts: mt8183: adjust cpuidle target residency Split a cluster level cpuidle state into two, so mt8183 variant boards can adjust parameters for each cluster, and reduce cluster0's default target residency to 1000us as power measurements showed that its minimum residency is slightly less than cluster1's 1300us. Signed-off-by: Ikjoon Jang Link: https://lore.kernel.org/r/20200225080752.200952-1-ikjn@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 97863adb7bc0..d946c1466c12 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -74,7 +74,7 @@ reg = <0x000>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -85,7 +85,7 @@ reg = <0x001>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>