From 912f9a6d0b75cbdbb0c86a4b011f571f7dc3a257 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Thu, 26 Mar 2020 11:39:31 +0100 Subject: arm64: dts: qcom: msm8916: Conform to the domain-idle-state binding As the domain-idle-state DT binding got converted to the json-schema, a few minor changes were introduced. For example, the states needs to be specified within a separate node, named domain-idle-states. Let's conform to the updated binding. This also silence the below errors for msm8916 from of 'make dtbs_check': idle-states: cluster-retention:compatible:0: 'arm,idle-state' was expected idle-states: cluster-gdhs:compatible:0: 'arm,idle-state' was expected Signed-off-by: Ulf Hansson Link: https://lore.kernel.org/r/20200326103932.5809-2-ulf.hansson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index a88a15f2352b..e7ff8701eed3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -165,6 +165,9 @@ min-residency-us = <2000>; local-timer-stop; }; + }; + + domain-idle-states { CLUSTER_RET: cluster-retention { compatible = "domain-idle-state"; -- cgit v1.2.3 From 31abcc91ef397c3e61659e1f69b38f8031d51b90 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Thu, 26 Mar 2020 11:39:32 +0100 Subject: arm64: dts: qcom: msm8916: Conform to the nodename pattern PSCI subnodes Subnodes for PSCI should start with "power-domain-", so let's adopt to this. Signed-off-by: Ulf Hansson Link: https://lore.kernel.org/r/20200326103932.5809-3-ulf.hansson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e7ff8701eed3..2fdc6aa61b83 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -191,31 +191,31 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu-pd0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CPU_PD1: cpu-pd1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CPU_PD2: cpu-pd2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CPU_PD3: cpu-pd3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CLUSTER_PD: cluster-pd { + CLUSTER_PD: power-domain-cluster { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; }; -- cgit v1.2.3 From f97d414d7fee8c3de0a6f4788f77b65f82b9a693 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Wed, 18 Mar 2020 14:38:17 +0530 Subject: arm64: dts: qcom: sc7180: Fix cpu compatible "arm,armv8" compatible should only be used for software models. Replace it with the real cpu type. Reviewed-by: Stephen Boyd Reviewed-by: Rajendra Nayak Signed-off-by: Amit Kucheria Link: https://lore.kernel.org/r/2526d2b2907116d1bb6f7edd194226eb7e24c333.1584516925.git.amit.kucheria@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 998f101ad623..270833e341d2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -91,7 +91,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; @@ -110,7 +110,7 @@ CPU1: cpu@100 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; @@ -126,7 +126,7 @@ CPU2: cpu@200 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; @@ -142,7 +142,7 @@ CPU3: cpu@300 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; @@ -158,7 +158,7 @@ CPU4: cpu@400 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1024>; @@ -174,7 +174,7 @@ CPU5: cpu@500 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1024>; @@ -190,7 +190,7 @@ CPU6: cpu@600 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; @@ -206,7 +206,7 @@ CPU7: cpu@700 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; -- cgit v1.2.3 From 9375e7d719b3fd933991382ddef2eb6572601273 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 11 Mar 2020 19:15:12 +0000 Subject: arm64: dts: qcom: qcs404: Add USB devices and PHYs QCS404 sports HS and SS USB controllers based on dwc3 block with two HS PHYs and one SS PHY. Add nodes for these devices and enable them for EVB board. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20200311191517.8221-2-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 100 +++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index f149a538c1cc..c685a1664810 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -323,6 +323,48 @@ reg = <0x00060000 0x6000>; }; + usb3_phy: phy@78000 { + compatible = "qcom,usb-ss-28nm-phy"; + reg = <0x00078000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "ahb", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + status = "disabled"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0007a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0007c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + qfprom: qfprom@a4000 { compatible = "qcom,qfprom"; reg = <0x000a4000 0x1000>; @@ -486,6 +528,64 @@ }; }; + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x07678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + status = "disabled"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x07580000 0xcd00>; + interrupts = ; + phys = <&usb2_phy_sec>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "otg"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x079b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + status = "disabled"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x078c0000 0xcc00>; + interrupts = ; + phys = <&usb2_phy_prim>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "peripheral"; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, -- cgit v1.2.3 From 70a8c5abc59873d74bf9b38db28187e89ca04cef Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 11 Mar 2020 19:15:13 +0000 Subject: arm64: dts: qcom: qcs404-evb: Define VBUS pins Defines VBUS detect and VBUS boost for the QCS404 EVB. Detect: VBUS present/absent is presented to the SoC via a GPIO on the EVB. Define the pin mapping for later use by gpio-usb-conn. Boost: An external regulator is used to trigger VBUS on/off via GPIO. This patch defines the relevant GPIO in the EVB dts. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20200311191517.8221-3-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index afe69e8f3114..f8780280700b 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -4,6 +4,8 @@ #include #include "qcs404.dtsi" #include "pms405.dtsi" +#include +#include / { aliases { @@ -272,6 +274,26 @@ }; }; +&pms405_gpios { + usb_vbus_boost_pin: usb-vbus-boost-pin { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = <1>; + }; + }; + usb3_vbus_pin: usb3-vbus-pin { + pinconf { + pins = "gpio12"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + power-source = <1>; + }; + }; +}; + &wifi { status = "okay"; vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>; -- cgit v1.2.3 From 599a0f340aa995d669c6f66fa775d5e764baa0e2 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 11 Mar 2020 19:15:14 +0000 Subject: arm64: dts: qcom: qcs404-evb: Define USB ID pin The USB ID pin is used to tell if a system is a Host or a Device. For our purposes we will bind this pin into gpio-usb-conn later. For now define the pin with its pinmux. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20200311191517.8221-4-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index f8780280700b..2d4e9db00afb 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -272,6 +272,20 @@ bias-pull-down; }; }; + + usb3_id_pin: usb3-id-pin { + pinmux { + pins = "gpio116"; + function = "gpio"; + }; + + pinconf { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; }; &pms405_gpios { -- cgit v1.2.3 From 2c0b742d2f183b4a51c753f75094d862a8bf8389 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 11 Mar 2020 19:15:15 +0000 Subject: arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator VBUS is supplied by an external regulator controlled by a GPIO pin. This patch models the regulator as regulator-usb3-vbus. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20200311191517.8221-5-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 2d4e9db00afb..11e2867f60d4 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -33,6 +33,18 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + usb3_vbus_reg: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_BOOST_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_vbus_boost_pin>; + vin-supply = <&vph_pwr>; + enable-active-high; + }; }; &blsp1_uart3 { -- cgit v1.2.3 From 3d439b2a48bccd00f0daca6d635d6050d2567deb Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 11 Mar 2020 19:15:16 +0000 Subject: arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage Rather than set the minimum microvolt for this regulator in the USB SS PHY driver, set it in the DTS. Suggested-by: Bjorn Andersson Cc: Andy Gross Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20200311191517.8221-6-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 11e2867f60d4..6020dbc88026 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -200,7 +200,7 @@ }; vreg_l12_3p3: l12 { - regulator-min-microvolt = <2968000>; + regulator-min-microvolt = <3050000>; regulator-max-microvolt = <3300000>; }; -- cgit v1.2.3 From 75e85d53fad2a072fcb12359b9f3952839e73576 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 11 Mar 2020 19:15:17 +0000 Subject: arm64: dts: qcom: qcs404-evb: Enable USB controllers This patch enables the primary and secondary USB controllers on the qcs404-evb. Primary: The primary USB controller has - One USB3 SS PHY using gpio-usb-conn - One USB2 HS PHY in device mode only and no connector driver associated. Secondary: The second DWC3 controller which has one USB Hi-Speed PHY attached to it. Cc: Andy Gross Cc: Bjorn Andersson Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20200311191517.8221-7-bryan.odonoghue@linaro.org [bjorn: Dropped usb3 role switching and enabled vbus] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 6020dbc88026..6422cf9d5855 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -44,6 +44,9 @@ pinctrl-0 = <&usb_vbus_boost_pin>; vin-supply = <&vph_pwr>; enable-active-high; + + /* TODO: Drop this when introducing role switching */ + regulator-always-on; }; }; @@ -320,6 +323,38 @@ }; }; +&usb2 { + status = "okay"; +}; + +&usb2_phy_sec { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + +&usb3 { + status = "okay"; + + dwc3@7580000 { + dr_mode = "host"; + }; +}; + +&usb2_phy_prim { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + +&usb3_phy { + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + status = "okay"; +}; + &wifi { status = "okay"; vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>; -- cgit v1.2.3 From 1c51a4aba5916a0624cda69e10a02a21f76345c3 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 24 Mar 2020 16:58:37 +0100 Subject: arm64: dts: qcom: msm8916: Add i2c-qcom-cci node The msm8916 CCI controller provides one CCI/I2C bus. Signed-off-by: Loic Poulain Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200324155843.10719-2-robert.foss@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 2fdc6aa61b83..0eba168f0a5c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1604,6 +1604,33 @@ #size-cells = <0>; }; }; + + cci: cci@1b0c000 { + compatible = "qcom,msm8916-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1b0c000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", "cci_ahb", + "cci", "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <19200000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; smd { -- cgit v1.2.3 From 39e0ce6cd1bf97e8076d55250ae05d4e965c0aac Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 24 Mar 2020 16:58:38 +0100 Subject: arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes Add cci device to msm8916.dtsi. Add default 96boards camera node for db410c (apq8016-sbc). Signed-off-by: Loic Poulain Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200324155843.10719-3-robert.foss@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 76 +++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 06aab44d798c..14982762088d 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -51,6 +51,30 @@ stdout-path = "serial0"; }; + camera_vdddo_1v8: camera_vdddo_1v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera_vdda_2v8: camera_vdda_2v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + camera_vddd_1v5: camera_vddd_1v5 { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + reserved-memory { ramoops@bff00000{ compatible = "ramoops"; @@ -538,6 +562,58 @@ }; }; +&camss { + status = "ok"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csiphy0_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&ov5640_ep>; + status = "okay"; + }; + }; + }; +}; + +&cci { + status = "ok"; +}; + +&cci_i2c0 { + camera_rear@3b { + compatible = "ovti,ov5640"; + reg = <0x3b>; + + enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>; + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "xclk"; + clock-frequency = <23880000>; + + vdddo-supply = <&camera_vdddo_1v8>; + vdda-supply = <&camera_vdda_2v8>; + vddd-supply = <&camera_vddd_1v5>; + + /* No camera mezzanine by default */ + status = "disabled"; + + port { + ov5640_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; + &spmi_bus { pm8916_0: pm8916@0 { pon@800 { -- cgit v1.2.3 From 07484de372bd57e6f8b28daca01bdf676015fa81 Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Tue, 24 Mar 2020 16:58:39 +0100 Subject: arm64: dts: qcom: sdm845: Add i2c-qcom-cci node The sdm845 SOC ships with a CCI controller, which has two CCI/I2C buses. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200324155843.10719-4-robert.foss@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 92 ++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index a2e05926b429..8644a2f6095a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -866,3 +866,7 @@ bias-pull-up; }; }; + +&cci { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8f926b5234d4..f3eb1dc11ac6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -1813,6 +1814,42 @@ gpio-ranges = <&tlmm 0 0 150>; wakeup-parent = <&pdc_intc>; + cci0_default: cci0-default { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci0_sleep: cci0-sleep { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + cci1_default: cci1-default { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_sleep: cci1-sleep { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + qspi_clk: qspi-clk { pinmux { pins = "gpio95"; @@ -3194,6 +3231,61 @@ #reset-cells = <1>; }; + cci: cci@ac4a000 { + compatible = "qcom,sdm845-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = ; + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + clock_camcc: clock-controller@ad00000 { + compatible = "qcom,sdm845-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; -- cgit v1.2.3 From 68fc0facce113f7bf587298bca80ffbbeb6a7485 Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Tue, 24 Mar 2020 16:58:40 +0100 Subject: arm64: dts: qcom: sdm845-db845c: Add pm_8998 gpio names Add pm_8998 GPIO trace names. These names are defined in the 96boards db845c mezzanine schematic. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200324155843.10719-5-robert.foss@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 8644a2f6095a..5cd06ab97b9a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -412,6 +412,34 @@ }; &pm8998_gpio { + gpio-line-names = + "NC", + "NC", + "WLAN_SW_CTRL", + "NC", + "PM_GPIO5_BLUE_BT_LED", + "VOL_UP_N", + "NC", + "ADC_IN1", + "PM_GPIO9_YEL_WIFI_LED", + "CAM0_AVDD_EN", + "NC", + "CAM0_DVDD_EN", + "PM_GPIO13_GREEN_U4_LED", + "DIV_CLK2", + "NC", + "NC", + "NC", + "SMB_STAT", + "NC", + "NC", + "ADC_IN2", + "OPTION1", + "WCSS_PWR_REQ", + "PM845_GPIO24", + "OPTION2", + "PM845_SLB"; + vol_up_pin_a: vol-up-active { pins = "gpio6"; function = "normal"; -- cgit v1.2.3 From d4919a44564b1d196a4211f59250735af737031e Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Tue, 24 Mar 2020 16:58:41 +0100 Subject: arm64: dts: qcom: sdm845-db845c: Add ov8856 & ov7251 camera nodes Enable the ov8856 main camera and the ov7251 b/w tracking camera used on the Qualcomm RB3 kit. Currently the camera nodes have not yet been attached to an to a CSI2 endpoint, since no driver currently supports the ISP that the the SDM845/db845c ships with. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200324155843.10719-6-robert.foss@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 178 +++++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 5cd06ab97b9a..6072ca38cef7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -112,6 +112,40 @@ // enable-active-high; }; + cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_DVDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + enable-active-high; + gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_dvdd_1v2_en_default>; + vin-supply = <&vbat>; + }; + + cam0_avdd_2v8: reg_cam0_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_avdd_2v8_en_default>; + vin-supply = <&vbat>; + }; + + /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ + cam3_avdd_2v8: reg_cam3_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM3_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vbat>; + }; + pcie0_3p3v_dual: vldo-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "VLDO_3V3"; @@ -440,6 +474,24 @@ "OPTION2", "PM845_SLB"; + cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en { + pins = "gpio12"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = ; + }; + + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en { + pins = "gpio10"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = ; + }; + vol_up_pin_a: vol-up-active { pins = "gpio6"; function = "normal"; @@ -601,6 +653,42 @@ }; &tlmm { + cam0_default: cam0_default { + rst { + pins = "gpio9"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + mclk0 { + pins = "gpio13"; + function = "cam_mclk"; + + drive-strength = <16>; + bias-disable; + }; + }; + + cam3_default: cam3_default { + rst { + function = "gpio"; + pins = "gpio21"; + + drive-strength = <16>; + bias-disable; + }; + + mclk3 { + function = "cam_mclk"; + pins = "gpio16"; + + drive-strength = <16>; + bias-disable; + }; + }; + pcie0_default_state: pcie0-default { clkreq { pins = "gpio36"; @@ -895,6 +983,96 @@ }; }; +&pm8998_gpio { + +}; + &cci { status = "ok"; }; + +&cci_i2c0 { + camera@10 { + compatible = "ovti,ov8856"; + reg = <0x10>; + + // CAM0_RST_N + reset-gpios = <&tlmm 9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_default>; + gpios = <&tlmm 13 0>, + <&tlmm 9 0>; + + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "xvclk"; + clock-frequency = <19200000>; + + /* The &vreg_s4a_1p8 trace is powered on as a, + * so it is represented by a fixed regulator. + * + * The 2.8V vdda-supply and 1.2V vddd-supply regulators + * both have to be enabled through the power management + * gpios. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + dovdd-supply = <&vreg_lvs1a_1p8>; + avdd-supply = <&cam0_avdd_2v8>; + dvdd-supply = <&cam0_dvdd_1v2>; + + status = "disable"; + + port { + ov8856_ep: endpoint { + clock-lanes = <1>; + link-frequencies = /bits/ 64 + <360000000 180000000>; + data-lanes = <1 2 3 4>; +// remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; + +&cci_i2c1 { + camera@60 { + compatible = "ovti,ov7251"; + + // I2C address as per ov7251.txt linux documentation + reg = <0x60>; + + // CAM3_RST_N + enable-gpios = <&tlmm 21 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam3_default>; + gpios = <&tlmm 16 0>, + <&tlmm 21 0>; + + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "xclk"; + clock-frequency = <24000000>; + + /* The &vreg_s4a_1p8 trace always powered on. + * + * The 2.8V vdda-supply regulator is enabled when the + * vreg_s4a_1p8 trace is pulled high. + * It too is represented by a fixed regulator. + * + * No 1.2V vddd-supply regulator is used. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + vdddo-supply = <&vreg_lvs1a_1p8>; + vdda-supply = <&cam3_avdd_2v8>; + + status = "disable"; + + port { + ov7251_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 1>; +// remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; -- cgit v1.2.3 From a0fa17f1ff74df618021704af98683a09f1fa837 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Tue, 10 Mar 2020 16:16:29 -0700 Subject: arm64: dts: qcom: sc7180: Include interconnect definitions Re-introduce the include of the sc7180 interconnect node name definitions. Though this was part of v5 of the interconnect provider series [1], it was dropped because the DT changes went through a different tree than the header. Re-add that now. Interconnect clients being introduced can reference this patch as a dependency, rather than racing each other to add the include. [1] https://patchwork.kernel.org/patch/11417989/ Signed-off-by: Evan Green Link: https://lore.kernel.org/r/20200310161502.1.Ia2884ed3c8826f52fbd5dcfa7a376a2fac4f31e6@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 270833e341d2..86e868af74d6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From eccdac07ae300bbe31ab4230a5ac522c1044d0e1 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 20 Mar 2020 18:41:04 +0530 Subject: arm64: dts: qcom: sc7180: modify assigned clocks for sc7180 target Add DISP_CC_MDSS_ROT_CLK and DISP_CC_MDSS_AHB_CLK in the assigned clocks list as these are display specific clocks and needs to be initialized from the client side. Adding the default rate of 19.2 mhz for these clocks for sc7180 target. Signed-off-by: Krishna Manikandan Link: https://lore.kernel.org/r/1584709864-5587-1-git-send-email-mkrishn@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 86e868af74d6..be5cb4a71675 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1545,8 +1545,12 @@ clock-names = "iface", "rot", "lut", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, <19200000>; interrupt-parent = <&mdss>; -- cgit v1.2.3 From fe2aff0c574d206f34f1864d5a0b093694c27142 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Mon, 30 Mar 2020 15:36:26 +0530 Subject: arm64: dts: qcom: msm8916: remove unit name for thermal trip points The thermal trip points have unit name but no reg property, so we can remove them. It also fixes the following warnings from 'make dtbs_check' after adding the thermal yaml bindings. arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: thermal-zones: gpu-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: thermal-zones: camera-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: thermal-zones: modem-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-zones: gpu-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-zones: camera-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8916-mtp.dt.yaml: thermal-zones: modem-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' Signed-off-by: Amit Kucheria Link: https://lore.kernel.org/r/2d3d045c18a2fb85b28cf304aa11ae6e6538d75e.1585562459.git.amit.kucheria@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0eba168f0a5c..569639fe8081 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -264,7 +264,7 @@ thermal-sensors = <&tsens 4>; trips { - cpu2_3_alert0: trip-point@0 { + cpu2_3_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -294,7 +294,7 @@ thermal-sensors = <&tsens 2>; trips { - gpu_alert0: trip-point@0 { + gpu_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -314,7 +314,7 @@ thermal-sensors = <&tsens 1>; trips { - cam_alert0: trip-point@0 { + cam_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "hot"; @@ -329,7 +329,7 @@ thermal-sensors = <&tsens 0>; trips { - modem_alert0: trip-point@0 { + modem_alert0: trip-point0 { temperature = <85000>; hysteresis = <2000>; type = "hot"; -- cgit v1.2.3 From 971b289d8749819040c203fccc2ccfbfd92e9442 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Mon, 30 Mar 2020 15:36:27 +0530 Subject: arm64: dts: qcom: msm8996: remove unit name for thermal trip points The thermal trip points have unit name but no reg property, so we can remove them. It also fixes the following warnings from 'make dtbs_check' after adding the thermal yaml bindings. arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: cpu0-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: cpu1-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: cpu2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: cpu3-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: m4m-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: l3-or-venus-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: cluster0-l2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: cluster1-l2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: camera-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: q6-dsp-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: mem-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-ifc6640.dt.yaml: thermal-zones: modemtx-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: cpu0-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: cpu1-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: cpu2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: cpu3-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: m4m-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: l3-or-venus-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: cluster0-l2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: cluster1-l2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: camera-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: q6-dsp-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: mem-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/apq8096-db820c.dt.yaml: thermal-zones: modemtx-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' Signed-off-by: Amit Kucheria Link: https://lore.kernel.org/r/2c0aa5357c96c3caff8554f9ef3ab9c5a2b8d2f8.1585562459.git.amit.kucheria@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 14827adebd94..895202d07a8b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2178,7 +2178,7 @@ thermal-sensors = <&tsens0 3>; trips { - cpu0_alert0: trip-point@0 { + cpu0_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2199,7 +2199,7 @@ thermal-sensors = <&tsens0 5>; trips { - cpu1_alert0: trip-point@0 { + cpu1_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2220,7 +2220,7 @@ thermal-sensors = <&tsens0 8>; trips { - cpu2_alert0: trip-point@0 { + cpu2_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2241,7 +2241,7 @@ thermal-sensors = <&tsens0 10>; trips { - cpu3_alert0: trip-point@0 { + cpu3_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2262,7 +2262,7 @@ thermal-sensors = <&tsens1 6>; trips { - gpu1_alert0: trip-point@0 { + gpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2277,7 +2277,7 @@ thermal-sensors = <&tsens1 7>; trips { - gpu2_alert0: trip-point@0 { + gpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2292,7 +2292,7 @@ thermal-sensors = <&tsens0 1>; trips { - m4m_alert0: trip-point@0 { + m4m_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2307,7 +2307,7 @@ thermal-sensors = <&tsens0 2>; trips { - l3_or_venus_alert0: trip-point@0 { + l3_or_venus_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2322,7 +2322,7 @@ thermal-sensors = <&tsens0 7>; trips { - cluster0_l2_alert0: trip-point@0 { + cluster0_l2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2337,7 +2337,7 @@ thermal-sensors = <&tsens0 12>; trips { - cluster1_l2_alert0: trip-point@0 { + cluster1_l2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2352,7 +2352,7 @@ thermal-sensors = <&tsens1 1>; trips { - camera_alert0: trip-point@0 { + camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2367,7 +2367,7 @@ thermal-sensors = <&tsens1 2>; trips { - q6_dsp_alert0: trip-point@0 { + q6_dsp_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2382,7 +2382,7 @@ thermal-sensors = <&tsens1 3>; trips { - mem_alert0: trip-point@0 { + mem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2397,7 +2397,7 @@ thermal-sensors = <&tsens1 4>; trips { - modemtx_alert0: trip-point@0 { + modemtx_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; -- cgit v1.2.3 From 285aa631e353e14efa8c153d6a4ab9bc7bcd3403 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Mon, 30 Mar 2020 15:36:28 +0530 Subject: arm64: dts: qcom: msm8998: remove unit name for thermal trip points The thermal trip points have unit name but no reg property, so we can remove them. It also fixes the following warnings from 'make dtbs_check' after adding the thermal yaml bindings. arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: cpu0-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: cpu1-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: cpu2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: cpu3-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: cpu4-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: cpu5-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: cpu6-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: cpu7-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: clust0-mhm-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: clust1-mhm-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: cluster1-l2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: modem-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: mem-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: wlan-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: q6-dsp-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: camera-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml: thermal-zones: multimedia-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: cpu0-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: cpu1-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: cpu2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: cpu3-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: cpu4-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: cpu5-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: cpu6-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: cpu7-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: clust0-mhm-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: clust1-mhm-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: cluster1-l2-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: modem-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: mem-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: wlan-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: q6-dsp-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: camera-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml: thermal-zones: multimedia-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' Signed-off-by: Amit Kucheria Link: https://lore.kernel.org/r/cd6f0c7298437d35642b35c9ede9064c247d6090.1585562459.git.amit.kucheria@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 38 +++++++++++++++++------------------ 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index c07fee6fd7eb..c45870600909 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -500,7 +500,7 @@ thermal-sensors = <&tsens0 1>; trips { - cpu0_alert0: trip-point@0 { + cpu0_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -521,7 +521,7 @@ thermal-sensors = <&tsens0 2>; trips { - cpu1_alert0: trip-point@0 { + cpu1_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -542,7 +542,7 @@ thermal-sensors = <&tsens0 3>; trips { - cpu2_alert0: trip-point@0 { + cpu2_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -563,7 +563,7 @@ thermal-sensors = <&tsens0 4>; trips { - cpu3_alert0: trip-point@0 { + cpu3_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -584,7 +584,7 @@ thermal-sensors = <&tsens0 7>; trips { - cpu4_alert0: trip-point@0 { + cpu4_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -605,7 +605,7 @@ thermal-sensors = <&tsens0 8>; trips { - cpu5_alert0: trip-point@0 { + cpu5_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -626,7 +626,7 @@ thermal-sensors = <&tsens0 9>; trips { - cpu6_alert0: trip-point@0 { + cpu6_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -647,7 +647,7 @@ thermal-sensors = <&tsens0 10>; trips { - cpu7_alert0: trip-point@0 { + cpu7_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -668,7 +668,7 @@ thermal-sensors = <&tsens0 12>; trips { - gpu1_alert0: trip-point@0 { + gpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -683,7 +683,7 @@ thermal-sensors = <&tsens0 13>; trips { - gpu2_alert0: trip-point@0 { + gpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -698,7 +698,7 @@ thermal-sensors = <&tsens0 5>; trips { - cluster0_mhm_alert0: trip-point@0 { + cluster0_mhm_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -713,7 +713,7 @@ thermal-sensors = <&tsens0 6>; trips { - cluster1_mhm_alert0: trip-point@0 { + cluster1_mhm_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -728,7 +728,7 @@ thermal-sensors = <&tsens0 11>; trips { - cluster1_l2_alert0: trip-point@0 { + cluster1_l2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -743,7 +743,7 @@ thermal-sensors = <&tsens1 1>; trips { - modem_alert0: trip-point@0 { + modem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -758,7 +758,7 @@ thermal-sensors = <&tsens1 2>; trips { - mem_alert0: trip-point@0 { + mem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -773,7 +773,7 @@ thermal-sensors = <&tsens1 3>; trips { - wlan_alert0: trip-point@0 { + wlan_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -788,7 +788,7 @@ thermal-sensors = <&tsens1 4>; trips { - q6_dsp_alert0: trip-point@0 { + q6_dsp_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -803,7 +803,7 @@ thermal-sensors = <&tsens1 5>; trips { - camera_alert0: trip-point@0 { + camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -818,7 +818,7 @@ thermal-sensors = <&tsens1 6>; trips { - multimedia_alert0: trip-point@0 { + multimedia_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; -- cgit v1.2.3 From a0e5aea1482bcbba2664723a88357fbe630ddb3c Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 31 Mar 2020 09:29:00 -0700 Subject: arm64: dts: qcom: sc7180: Swap order of gpucc and sdhc_2 Devices are supposed to be sorted by unit address. These two got swapped when they landed. Fix. Reviewed-by: Matthias Kaehlcke Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20200331092832.1.Ic361058ca22d7439164ffea11421740462e14272@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index be5cb4a71675..62faac453755 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1295,6 +1295,20 @@ }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -1313,20 +1327,6 @@ status = "disabled"; }; - gpucc: clock-controller@5090000 { - compatible = "qcom,sc7180-gpucc"; - reg = <0 0x05090000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; -- cgit v1.2.3 From 22337b91022d8c9c8a56324c9b1ae58e7ab5768d Mon Sep 17 00:00:00 2001 From: Rajeshwari Date: Tue, 7 Apr 2020 13:01:16 +0530 Subject: arm64: dts: qcom: sc7180: Changed polling mode in Thermal-zones node Changed polling-delay and polling-delay-passive to zero to disable polling mode of the framework as interrupts for tsens are already configured. Signed-off-by: Rajeshwari Reviewed-by: Amit Kucheria Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/1586244677-14399-1-git-send-email-rkambl@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 100 +++++++++++++++++------------------ 1 file changed, 50 insertions(+), 50 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 62faac453755..92a8296ae795 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2016,8 +2016,8 @@ thermal-zones { cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -2064,8 +2064,8 @@ }; cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + pollin