From 5bb01a991897d74295ff8de548d350400d7370a9 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 9 Nov 2011 15:29:31 -0800 Subject: ARM: OMAP: Fix map_io for Amstrad E3 Commit 7b88e62f5d219a86d81bdf4388012c97dc42e8f8 (ARM: OMAP1: Use generic map_io, init_early and init_irq) changed omap1 to use generic map_io. Looks like I missed one board though. Fix this by adding a custom map_io for Amstrad E3. Reported-by: Aaro Koskinen Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-ams-delta.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-omap1') diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 51bae31cf361..b0f15d234a12 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -302,8 +302,6 @@ static void __init ams_delta_init(void) omap_cfg_reg(J19_1610_CAM_D6); omap_cfg_reg(J18_1610_CAM_D7); - iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc)); - omap_board_config = ams_delta_config; omap_board_config_size = ARRAY_SIZE(ams_delta_config); omap_serial_init(); @@ -373,10 +371,16 @@ static int __init ams_delta_modem_init(void) } arch_initcall(ams_delta_modem_init); +static void __init ams_delta_map_io(void) +{ + omap15xx_map_io(); + iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc)); +} + MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)") /* Maintainer: Jonathan McDowell */ .atag_offset = 0x100, - .map_io = omap15xx_map_io, + .map_io = ams_delta_map_io, .init_early = omap1_init_early, .reserve = omap_reserve, .init_irq = omap1_init_irq, -- cgit v1.2.3 From e9b7086b80c4d9e354f4edc9e280ae85a60df408 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 11 Nov 2011 10:15:11 -0800 Subject: ARM: OMAP: Fix reprogramming of dpll1 rate Commit a66cb3454f220f49f900646ebdc76cb943319eb7 (ARM: OMAP: Map SRAM later on with ioremap_exec()) moved the SRAM init to happen later to remove a dependency to early SoC detection for map_io. This broke booting on some boards not using Kconfig option for OMAP_CLOCKS_SET_BY_BOOTLOADER as the dpll1 reprogramming would cause the following error: kernel BUG at arch/arm/plat-omap/sram.c:226! Internal error: Oops - undefined instruction: 0 [#1] PREEMPT Modules linked in: CPU: 0 Not tainted (3.2.0-rc1-e3 #9) PC is at omap_sram_reprogram_clock+0x28/0x30 LR is at omap1_select_table_rate+0x88/0xb4 pc : [] lr : [] psr: 600000d3 sp : c035bf10 ip : c035bf20 fp : c035bf1c r10: c035bfd4 r9 : 54029252 r8 : c03f8120 r7 : c0362b50 r6 : 00b71b00 r5 : c03873cc r4 : c0362b40 r3 : 00000000 r2 : c0362b40 r1 : 0000010a r0 : 00002cb0 Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel Control: 0000317f Table: 10004000 DAC: 00000017 Process swapper (pid: 0, stack limit = 0xc035a270) Stack: (0xc035bf10 to 0xc035c000) bf00: c035bf3c c035bf20 c0019f54 c001b0ac bf20: 00001000 00002cb3 00000004 c035ed4c c035bf74 c035bf40 c033ea24 c0019edc bf40: c02f526c 00000002 00000015 bc058c9b 93111a16 c035335c 02000000 c035ed4c bf60: c035ed4c c03f8120 c035bf84 c035bf78 c00194c4 c033e8ec c035bfc4 c035bf88 bf80: c033bc24 c00194a0 c035bf90 c035bf98 00000000 00000000 00000000 00000000 bfa0: 00000001 00000000 c0354678 c035ece4 10004000 103532f4 c035bff4 c035bfc8 bfc0: c0338574 c033b598 00000000 00000000 00000000 c035467c 0000317d c035c03c bfe0: c0354678 c035ece4 00000000 c035bff8 10008040 c0338508 00000000 00000000 Backtrace: [] (omap_sram_reprogram_clock+0x0/0x30) from [] (omap1_select_table_rate+0x88/0xb4) [] (omap1_select_table_rate+0x0/0xb4) from [] (omap1_clk_init+0x148/0x334) r7:c035ed4c r6:00000004 r5:00002cb3 r4:00001000 [] (omap1_clk_init+0x0/0x334) from [] (omap1_init_early+0x34/0x48) r8:c03f8120 r7:c035ed4c r6:c035ed4c r5:02000000 r4:c035335c [] (omap1_init_early+0x0/0x48) from [] (setup_arch+0x69c/0x79c) [] (setup_arch+0x0/0x79c) from [] (start_kernel+0x7c/0x2f4) [] (start_kernel+0x0/0x2f4) from [<10008040>] (0x10008040) r7:c035ece4 r6:c0354678 r5:c035c03c r4:0000317d Code: 0a000002 e1a0e00f e12fff13 e89da800 (e7f001f2) Fix this by adding omap1_clk_late_init() that only reprograms dpll1 if the bootloader rate is less than 60MHz. This also allows removing of the OMAP_CLOCKS_SET_BY_BOOTLOADER option. Reported-by: Aaro Koskinen Tested-by: Aaro Koskinen Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/Kconfig | 8 ------ arch/arm/mach-omap1/clock.h | 3 ++- arch/arm/mach-omap1/clock_data.c | 53 ++++++++++++++++++++++++++-------------- arch/arm/mach-omap1/devices.c | 3 +++ 4 files changed, 39 insertions(+), 28 deletions(-) (limited to 'arch/arm/mach-omap1') diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index e0a028161dde..73f287d6429b 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -171,14 +171,6 @@ config MACH_OMAP_GENERIC comment "OMAP CPU Speed" depends on ARCH_OMAP1 -config OMAP_CLOCKS_SET_BY_BOOTLOADER - bool "OMAP clocks set by bootloader" - depends on ARCH_OMAP1 - help - Enable this option to prevent the kernel from overriding the clock - frequencies programmed by bootloader for MPU, DSP, MMUs, TC, - internal LCD controller and MPU peripherals. - config OMAP_ARM_216MHZ bool "OMAP ARM 216 MHz CPU (1710 only)" depends on ARCH_OMAP1 && ARCH_OMAP16XX diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index eaf09efb91ca..16b1423b454a 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -17,7 +17,8 @@ #include -extern int __init omap1_clk_init(void); +int omap1_clk_init(void); +void omap1_clk_late_init(void); extern int omap1_clk_enable(struct clk *clk); extern void omap1_clk_disable(struct clk *clk); extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 92400b9eb69f..1297bb58869c 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -767,6 +767,15 @@ static struct clk_functions omap1_clk_functions = { .clk_disable_unused = omap1_clk_disable_unused, }; +static void __init omap1_show_rates(void) +{ + pr_notice("Clocking rate (xtal/DPLL1/MPU): " + "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", + ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, + ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, + arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); +} + int __init omap1_clk_init(void) { struct omap_clk *c; @@ -835,9 +844,12 @@ int __init omap1_clk_init(void) /* We want to be in syncronous scalable mode */ omap_writew(0x1000, ARM_SYSST); -#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER - /* Use values set by bootloader. Determine PLL rate and recalculate - * dependent clocks as if kernel had changed PLL or divisors. + + /* + * Initially use the values set by bootloader. Determine PLL rate and + * recalculate dependent clocks as if kernel had changed PLL or + * divisors. See also omap1_clk_late_init() that can reprogram dpll1 + * after the SRAM is initialized. */ { unsigned pll_ctl_val = omap_readw(DPLL_CTL); @@ -862,25 +874,10 @@ int __init omap1_clk_init(void) } } } -#else - /* Find the highest supported frequency and enable it */ - if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { - printk(KERN_ERR "System frequencies not set. Check your config.\n"); - /* Guess sane values (60MHz) */ - omap_writew(0x2290, DPLL_CTL); - omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); - ck_dpll1.rate = 60000000; - } -#endif propagate_rate(&ck_dpll1); /* Cache rates for clocks connected to ck_ref (not dpll1) */ propagate_rate(&ck_ref); - printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " - "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", - ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, - ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, - arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); - + omap1_show_rates(); if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { /* Select slicer output as OMAP input clock */ omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, @@ -925,3 +922,21 @@ int __init omap1_clk_init(void) return 0; } + +#define OMAP1_DPLL1_SANE_VALUE 60000000 + +void __init omap1_clk_late_init(void) +{ + if (ck_dpll1.rate >= OMAP1_DPLL1_SANE_VALUE) + return; + + /* Find the highest supported frequency and enable it */ + if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { + pr_err("System frequencies not set, using default. Check your config.\n"); + omap_writew(0x2290, DPLL_CTL); + omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); + ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; + } + propagate_rate(&ck_dpll1); + omap1_show_rates(); +} diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 48ef9888e820..475cb2f50d87 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -30,6 +30,8 @@ #include #include +#include "clock.h" + /*-------------------------------------------------------------------------*/ #if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE) @@ -293,6 +295,7 @@ static int __init omap1_init_devices(void) return -ENODEV; omap_sram_init(); + omap1_clk_late_init(); /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. -- cgit v1.2.3 From 650f7a72b8cc235ffe4a0e3eff37954349026721 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 1 Dec 2011 17:47:06 -0800 Subject: ARM: OMAP1: Fix reprogramming of DPLL1 for systems that boot at rates below 60MHz Commit e9b7086b80c4d9e354f4edc9e280ae85a60df408 (ARM: OMAP: Fix reprogramming of dpll1 rate) fixed a regression for systems that did not rely on bootloader set rates. However, it also introduced a new problem where the rates selected in .config would not take affect as omap1_select_table_rate currently refuses to reprogram DPLL1 if it's already initialized. This was not a problem earlier, as the reprogramming was done earlier with ck_dpll1_p->rate uninitialized. Fix this by forcing the reprogramming on systems booting at rates below 60MHz. Note that the long term fix is to make the rates SoC specific later on. Thanks for Janusz Krzysztofik for figuring this one out. Reported-by: Janusz Krzysztofik Acked-by: Janusz Krzysztofik Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/clock_data.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-omap1') diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 1297bb58869c..3f305610efa0 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -930,6 +930,9 @@ void __init omap1_clk_late_init(void) if (ck_dpll1.rate >= OMAP1_DPLL1_SANE_VALUE) return; + /* System booting at unusable rate, force reprogramming of DPLL1 */ + ck_dpll1_p->rate = 0; + /* Find the highest supported frequency and enable it */ if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { pr_err("System frequencies not set, using default. Check your config.\n"); -- cgit v1.2.3 From c2cb211116192690605eaa70d39deb04241003e2 Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Thu, 1 Dec 2011 21:13:01 +0100 Subject: ARM: OMAP1: Fix ckctl value used for dpll1 defualt rate Use the exact value found in omap1_rate_table, otherwise I have been experiencing issues with correct timekeeping on my Amstrad Delta. Signed-off-by: Janusz Krzysztofik [tony@atomide.com: removed comment referencing a development branch] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/clock_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-omap1') diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 3f305610efa0..86b2dec11788 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -937,7 +937,7 @@ void __init omap1_clk_late_init(void) if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { pr_err("System frequencies not set, using default. Check your config.\n"); omap_writew(0x2290, DPLL_CTL); - omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); + omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL); ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; } propagate_rate(&ck_dpll1); -- cgit v1.2.3 From 6560ee07dc946e94f7cc2cd8e3b5a5f5ee7340c1 Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Thu, 1 Dec 2011 21:13:02 +0100 Subject: ARM: OMAP1: recalculate loops per jiffy after dpll1 reprogram Otherwise timing is inaccurate, resulting in devices which depend on it, like omap-keypad, broken. Tested on Amstrad Delta. Signed-off-by: Janusz Krzysztofik [tony@atomide.com: removed comment referencing a development branch] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/clock_data.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap1') diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 86b2dec11788..9ff90a744a21 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -16,6 +16,8 @@ #include #include +#include +#include #include #include /* for machine_is_* */ @@ -927,7 +929,9 @@ int __init omap1_clk_init(void) void __init omap1_clk_late_init(void) { - if (ck_dpll1.rate >= OMAP1_DPLL1_SANE_VALUE) + unsigned long rate = ck_dpll1.rate; + + if (rate >= OMAP1_DPLL1_SANE_VALUE) return; /* System booting at unusable rate, force reprogramming of DPLL1 */ @@ -942,4 +946,5 @@ void __init omap1_clk_late_init(void) } propagate_rate(&ck_dpll1); omap1_show_rates(); + loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate); } -- cgit v1.2.3