From 4b8f7a11c9fb680895e5079788653a59d6bdde16 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 22 Feb 2014 20:14:52 +0100 Subject: ARM: MM: Add DT binding for Feroceon L2 cache Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn Tested-by: Jason Gunthorpe Signed-off-by: Jason Cooper --- arch/arm/include/asm/hardware/cache-feroceon-l2.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include/asm/hardware') diff --git a/arch/arm/include/asm/hardware/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h index 8edd330aabf6..12e1588dc4f1 100644 --- a/arch/arm/include/asm/hardware/cache-feroceon-l2.h +++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h @@ -9,3 +9,5 @@ */ extern void __init feroceon_l2_init(int l2_wt_override); +extern int __init feroceon_of_init(void); + -- cgit v1.2.3