From 3eca037f2dfce07a31da0a837ac35d6d846614b0 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 6 Nov 2019 19:47:02 +1030 Subject: ARM: dts: aspeed-g6: Add timer description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The AST2600 has 8 32-bit timers on the APB bus. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index c800e4cf866d..5f6142d99eeb 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -330,6 +330,21 @@ status = "disabled"; }; + timer: timer@1e782000 { + compatible = "aspeed,ast2600-timer"; + reg = <0x1e782000 0x90>; + interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_APB1>; + clock-names = "PCLK"; + }; + uart1: serial@1e783000 { compatible = "ns16550a"; reg = <0x1e783000 0x20>; -- cgit v1.2.3