From b3d6aba8bd92c20b7748ccd82b6fab8ea5081066 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Fri, 1 Jan 2016 18:48:40 +0530 Subject: ARC: [dts] Add clk feeding into timers to DTs This allows us to introduce timers in DT in next commit The core clk frequency hack in AXS103 platform is also extended, where the core clk feeding into timers is updated in-place in FDT. Cc: Daniel Lezcano Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Vineet Gupta --- arch/arc/plat-axs10x/axs10x.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arc/plat-axs10x') diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c index 8e7f50a8b857..f90fac271d16 100644 --- a/arch/arc/plat-axs10x/axs10x.c +++ b/arch/arc/plat-axs10x/axs10x.c @@ -14,7 +14,9 @@ * */ +#include #include +#include #include #include @@ -389,7 +391,12 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od) static void __init axs103_early_init(void) { - u32 freq = arc_get_core_freq(), orig = freq; + int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk"); + const struct fdt_property *prop = fdt_get_property(initial_boot_params, + offset, + "clock-frequency", + NULL); + u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq; /* * AXS103 configurations for SMP/QUAD configurations share device tree @@ -438,8 +445,13 @@ static void __init axs103_early_init(void) } pr_info("Freq is %dMHz\n", freq); + + /* Patching .dtb in-place with new core clock value */ if (freq != orig ) { arc_set_core_freq(freq * 1000000); + freq = cpu_to_be32(freq * 1000000); + fdt_setprop_inplace(initial_boot_params, offset, + "clock-frequency", &freq, sizeof(freq)); } /* Memory maps already config in pre-bootloader */ -- cgit v1.2.3