From cd6720ba022bae39e0b37ec12a3fc810643a779c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 30 Oct 2020 19:36:55 +0100 Subject: dt-bindings: microchip: atmel,at91rm9200-tcb: Add atmel,tcb-pwm Move the TCB pwm nodes under their parent. This removes the need for the tc-block property as there is now a child-parent relationship between the TC channel and the TC block. Move the documentation to the main file. Signed-off-by: Alexandre Belloni Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/pwm/atmel-tcb-pwm.txt | 16 ---------- .../soc/microchip/atmel,at91rm9200-tcb.yaml | 34 +++++++++++++++++++++- 2 files changed, 33 insertions(+), 17 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt deleted file mode 100644 index 985fcc65f8c4..000000000000 --- a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt +++ /dev/null @@ -1,16 +0,0 @@ -Atmel TCB PWM controller - -Required properties: -- compatible: should be "atmel,tcb-pwm" -- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of - the cells format. The only third cell flag supported by this binding is - PWM_POLARITY_INVERTED. -- tc-block: The Timer Counter block to use as a PWM chip. - -Example: - -pwm { - compatible = "atmel,tcb-pwm"; - #pwm-cells = <3>; - tc-block = <1>; -}; diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml index 55fffae05dcf..597d67fba92f 100644 --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -59,6 +59,7 @@ patternProperties: items: - enum: - atmel,tcb-timer + - atmel,tcb-pwm - microchip,tcb-capture reg: description: @@ -68,10 +69,35 @@ patternProperties: minItems: 1 maxItems: 3 + required: + - compatible + - reg + + "^pwm@[0-2]$": + description: The timer block channels that are used as PWMs. + $ref: ../../pwm/pwm.yaml# + type: object + properties: + compatible: + const: atmel,tcb-pwm + reg: + description: + TCB channel to use for this PWM. + enum: [ 0, 1, 2 ] + + "#pwm-cells": + description: + The only third cell flag supported by this binding is + PWM_POLARITY_INVERTED. + const: 3 required: - compatible - reg + - "#pwm-cells" + + additionalProperties: false + allOf: - if: @@ -158,7 +184,13 @@ examples: compatible = "atmel,tcb-timer"; reg = <1>; }; - }; + + pwm@2 { + compatible = "atmel,tcb-pwm"; + reg = <2>; + #pwm-cells = <3>; + }; + }; /* TCB0 Capture with QDEC: */ timer@f800c000 { compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; -- cgit v1.2.3 From cb55d17ea2ecb7698bc37e5658b4642eef45a327 Mon Sep 17 00:00:00 2001 From: Vijayakannan Ayyathurai Date: Thu, 22 Oct 2020 15:14:47 +0800 Subject: dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add PWM Device Tree bindings documentation for the Intel Keem Bay SoC. Signed-off-by: Vineetha G. Jaya Kumaran Reviewed-by: Rob Herring Acked-by: Uwe Kleine-König Signed-off-by: Vijayakannan Ayyathurai Signed-off-by: Thierry Reding --- .../devicetree/bindings/pwm/intel,keembay-pwm.yaml | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml new file mode 100644 index 000000000000..ff6880a02ce6 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay PWM Device Tree Bindings + +maintainers: + - Vijayakannan Ayyathurai + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - intel,keembay-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - '#pwm-cells' + +additionalProperties: false + +examples: + - | + #define KEEM_BAY_A53_GPIO + + pwm@203200a0 { + compatible = "intel,keembay-pwm"; + reg = <0x203200a0 0xe8>; + clocks = <&scmi_clk KEEM_BAY_A53_GPIO>; + #pwm-cells = <2>; + }; -- cgit v1.2.3 From ad5a228b9bad44e2a652e45fd9ac767d8880f480 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 19 Oct 2020 16:07:01 +0200 Subject: dt-bindings: pwm: pwm-mediatek: Add documentation for MT8183 SoC Add binding documentation for the MT8183 SoC. Signed-off-by: Fabien Parent Reviewed-by: Matthias Brugger Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 29adff59c479..25ed214473d7 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -7,6 +7,7 @@ Required properties: - "mediatek,mt7623-pwm": found on mt7623 SoC. - "mediatek,mt7628-pwm": found on mt7628 SoC. - "mediatek,mt7629-pwm": found on mt7629 SoC. + - "mediatek,mt8183-pwm": found on mt8183 SoC. - "mediatek,mt8516-pwm": found on mt8516 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of -- cgit v1.2.3 From 554b3b31e9229b498dc17f9bc0f14b42c586f0e9 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 16 Oct 2020 20:50:15 +0200 Subject: dt-bindings: pwm: mtk-disp: add MT8167 SoC binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add binding for MT8167 SoC. The IP is compatible with MT8173. Signed-off-by: Fabien Parent Acked-by: Uwe Kleine-König Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt index 0521957c253f..902b271891ae 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt @@ -4,6 +4,7 @@ Required properties: - compatible: should be "mediatek,-disp-pwm": - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. + - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC. - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of -- cgit v1.2.3 From 7c0e4f2ef782a4da2126a9399316b689d4fbc013 Mon Sep 17 00:00:00 2001 From: Rahul Tanwar Date: Thu, 5 Nov 2020 13:49:39 +0800 Subject: Add DT bindings YAML schema for PWM fan controller of LGM SoC Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller which is only used to control the fan attached to the system. This PWM controller does not have any other consumer other than fan. Add DT bindings documentation for this PWM fan controller. Signed-off-by: Rahul Tanwar Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/pwm/intel,lgm-pwm.yaml | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml new file mode 100644 index 000000000000..11a606536169 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/intel,lgm-pwm.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LGM SoC PWM fan controller + +maintainers: + - Rahul Tanwar + +properties: + compatible: + const: intel,lgm-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 2 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + pwm: pwm@e0d00000 { + compatible = "intel,lgm-pwm"; + reg = <0xe0d00000 0x30>; + #pwm-cells = <2>; + clocks = <&cgu0 126>; + resets = <&rcu0 0x30 21>; + }; -- cgit v1.2.3