From 07c2ae9cc6a49bf6403a5a156f897dcb30b5ccf4 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Fri, 5 Jul 2013 13:48:01 +0530 Subject: of/documentation: Fix a typo in exynos5250-clock.txt The clocks should be numbered sequentially as they are represented as enum values in the clock driver. Typo introduced by commit 17d4caccef ("clk: exynos5250: register display block gate clocks to common clock framework") Signed-off-by: Sachin Kamat Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 781a6276adf7..1a05761de4bd 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -154,7 +154,7 @@ clock which they consume. dsim0 341 dp 342 mixer 343 - hdmi 345 + hdmi 344 Example 1: An example of a clock controller node is listed below. -- cgit v1.2.3 From 406c5989276967db8721d057ed4b4f51bf9c71c6 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Fri, 5 Jul 2013 14:12:27 +0530 Subject: clk: exynos5250: Add G2D gate clock Adds gate clock for G2D IP for Exynos5250 SoC. Signed-off-by: Sachin Kamat Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 1a05761de4bd..7e882429add9 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -155,6 +155,7 @@ clock which they consume. dp 342 mixer 343 hdmi 344 + g2d 345 Example 1: An example of a clock controller node is listed below. -- cgit v1.2.3 From 93b10d1b94341afc87f1bd0efe9b516b9d0fe00f Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Thu, 25 Jul 2013 10:37:33 +0530 Subject: Documentation: exynos5250-clock: Add div_i2s1 and div_i2s2 commit 79d743c177f9 ("clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2") added two new clock entries. Add the clock entry enum numbers to documentation. Signed-off-by: Tushar Behera Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 7e882429add9..2d4a7151180b 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -59,6 +59,8 @@ clock which they consume. sclk_spi0 154 sclk_spi1 155 sclk_spi2 156 + div_i2s1 157 + div_i2s2 158 [Peripheral Clock Gates] -- cgit v1.2.3 From 4a453314883d9d0a500107b508500ffffdca2f6d Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Thu, 25 Jul 2013 10:37:34 +0530 Subject: clk/exynos5250: add mout_hdmi mux clock for hdmi hdmi driver needs to change the parent of hdmi clock frequently between pixel clock and hdmiphy clock. hdmiphy is not stable after power on and for a short interval while changing the phy configuration. For this duration pixel clock is used to clock hdmi. This patch is exposing the mux for changing parent. Signed-off-by: Rahul Sharma Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 2d4a7151180b..76b97c92870c 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -159,6 +159,14 @@ clock which they consume. hdmi 344 g2d 345 + + [Clock Muxes] + + Clock ID + ---------------------------- + mout_hdmi 1024 + + Example 1: An example of a clock controller node is listed below. clock: clock-controller@0x10010000 { -- cgit v1.2.3 From b38a5040a66dc4337ed9a06cc7495a42dd684028 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Thu, 25 Jul 2013 10:37:35 +0530 Subject: clk/exynos5250: add sclk_hdmiphy in the list of special clocks hdmi driver needs hdmiphy clock which is one of the parent for hdmi mux clock. This is required while changing the parent of mux clock. Signed-off-by: Rahul Sharma Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 76b97c92870c..24765c146e31 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -61,6 +61,7 @@ clock which they consume. sclk_spi2 156 div_i2s1 157 div_i2s2 158 + sclk_hdmiphy 159 [Peripheral Clock Gates] -- cgit v1.2.3 From 9f271369f5cf0a1f58709e6c753a6fa4d8c355d3 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Wed, 24 Jul 2013 15:39:15 +0530 Subject: clk: exynos4: Add clock entries for TMU Added clock entries for thermal management unit (TMU) for Exynos4 SoCs. Signed-off-by: Sachin Kamat Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos4-clock.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index 14d5c2af26f4..c6bf8a6c8f52 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -236,6 +236,7 @@ Exynos4 SoC and this is specified where applicable. spi0_isp_sclk 380 Exynos4x12 spi1_isp_sclk 381 Exynos4x12 uart_isp_sclk 382 Exynos4x12 + tmu_apbif 383 [Mux Clocks] -- cgit v1.2.3 From 8f9a5b52bc72143a0bdc304f2cc273295581f722 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Tue, 9 Jul 2013 11:59:15 +0530 Subject: of/documentation: Update G2D documentation Exynos5250 G2D IP requires only the gate clock. Update the binding documentation accordingly. Signed-off-by: Sachin Kamat Cc: Inki Dae Reviewed-by: Tomasz Figa Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/gpu/samsung-g2d.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt index 3f454ffc654a..c4f358dafdaa 100644 --- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt +++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt @@ -11,8 +11,11 @@ Required properties: - interrupts : G2D interrupt number to the CPU. - clocks : from common clock binding: handle to G2D clocks. - - clock-names : from common clock binding: must contain "sclk_fimg2d" and - "fimg2d", corresponding to entries in the clocks property. + - clock-names : names of clocks listed in clocks property, in the same + order, depending on SoC type: + - for S5PV210 and Exynos4 based SoCs: "fimg2d" and + "sclk_fimg2d" + - for Exynos5250 SoC: "fimg2d". Example: g2d@12800000 { -- cgit v1.2.3 From 06dda9d770063c5fefc0b41c7bfcc1321e2649dd Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 24 Jul 2013 01:55:15 +0200 Subject: clk: samsung: Add clock driver for S3C64xx SoCs This patch adds new, Common Clock Framework-based clock driver for Samsung S3C64xx SoCs. The driver is just added, without actually letting the platforms use it yet, since this requires more intermediate steps. Signed-off-by: Tomasz Figa Signed-off-by: Mike Turquette --- .../bindings/clock/samsung,s3c64xx-clock.txt | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt new file mode 100644 index 000000000000..fa171dc4bd3c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt @@ -0,0 +1,77 @@ +* Samsung S3C64xx Clock Controller + +The S3C64xx clock controller generates and supplies clock to various controllers +within the SoC. The clock binding described here is applicable to all SoCs in +the S3C64xx family. + +Required Properties: + +- compatible: should be one of the following. + - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC. + - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. Some of the clocks are available only +on a particular S3C64xx SoC and this is specified where applicable. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device +tree sources. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "fin_pll" - PLL input clock (xtal/extclk) - required, + - "xusbxti" - USB xtal - required, + - "iiscdclk0" - I2S0 codec clock - optional, + - "iiscdclk1" - I2S1 codec clock - optional, + - "iiscdclk2" - I2S2 codec clock - optional, + - "pcmcdclk0" - PCM0 codec clock - optional, + - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410. + +Example: Clock controller node: + + clock: clock-controller@7e00f000 { + compatible = "samsung,s3c6410-clock"; + reg = <0x7e00f000 0x1000>; + #clock-cells = <1>; + }; + +Example: Required external clocks: + + fin_pll: clock-fin-pll { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + clock-frequency = <12000000>; + #clock-cells = <0>; + }; + + xusbxti: clock-xusbxti { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller (refer to the standard clock bindings for information about + "clocks" and "clock-names" properties): + + uart0: serial@7f005000 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <5>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>, + <&clock SCLK_UART>; + status = "disabled"; + }; -- cgit v1.2.3 From 6f9a4894c435bc9919dab31d90f69167d4638997 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Fri, 12 Jul 2013 08:53:43 +0530 Subject: Documentation: clk: Fix a trivial typo in audss Fixes a trivial typo. Signed-off-by: Sachin Kamat Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/clk-exynos-audss.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index a1201802f90d..75e2e1999f87 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -2,7 +2,7 @@ The Samsung Audio Subsystem clock controller generates and supplies clocks to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock -binding described here is applicable to all SoC's in Exynos family. +binding described here is applicable to all SoCs in Exynos family. Required Properties: -- cgit v1.2.3 From 71472c0c06cf9a3d1540762ea205654c584e3bc4 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Mon, 29 Jul 2013 12:25:00 +0100 Subject: clk: add support for clock reparent on set_rate Add core support to allow clock implementations to select the best parent clock when rounding a rate, e.g. the one which can provide the closest clock rate to that requested. This is by way of adding a new clock op, determine_rate(), which is like round_rate() but has an extra parameter to allow the clock implementation to optionally select a different parent clock. The core then takes care of reparenting the clock when setting the rate. The parent change takes place with the help of some new private data members. struct clk::new_parent specifies a clock's new parent (NULL indicates no change), and struct clk::new_child specifies a clock's new child (whose new_parent member points back to it). The purpose of these are to allow correct walking of the future tree for notifications prior to actually reparenting any clocks, specifically to skip child clocks who are being reparented to another clock (they will be notified via the new parent), and to include any new child clock. These pointers are set by clk_calc_subtree(), and the new_child pointer gets cleared when a child is actually reparented to avoid duplicate POST_RATE_CHANGE notifications. Each place where round_rate() is called, determine_rate() is checked first and called in preference. This restructures a few of the call sites to simplify the logic into if/else blocks. Signed-off-by: James Hogan Reviewed-by: Stephen Boyd Cc: Mike Turquette Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette --- Documentation/clk.txt | 46 ++++++++++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 20 deletions(-) (limited to 'Documentation') diff --git a/Documentation/clk.txt b/Documentation/clk.txt index 6f68ba0d1e01..3aeb5c440442 100644 --- a/Documentation/clk.txt +++ b/Documentation/clk.txt @@ -70,6 +70,10 @@ the operations defined in clk.h: unsigned long parent_rate); long (*round_rate)(struct clk_hw *hw, unsigned long, unsigned long *); + long (*determine_rate)(struct clk_hw *hw, + unsigned long rate, + unsigned long *best_parent_rate, + struct clk **best_parent_clk); int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long); @@ -179,26 +183,28 @@ mandatory, a cell marked as "n" implies that either including that callback is invalid or otherwise unnecessary. Empty cells are either optional or must be evaluated on a case-by-case basis. - clock hardware characteristics - ----------------------------------------------------------- - | gate | change rate | single parent | multiplexer | root | - |------|-------------|---------------|-------------|------| -.prepare | | | | | | -.unprepare | | | | | | - | | | | | | -.enable | y | | | | | -.disable | y | | | | | -.is_enabled | y | | | | | - | | | | | | -.recalc_rate | | y | | | | -.round_rate | | y | | | | -.set_rate | | y | | | | - | | | | | | -.set_parent | | | n | y | n | -.get_parent | | | n | y | n | - | | | | | | -.init | | | | | | - ----------------------------------------------------------- + clock hardware characteristics + ----------------------------------------------------------- + | gate | change rate | single parent | multiplexer | root | + |------|-------------|---------------|-------------|------| +.prepare | | | | | | +.unprepare | | | | | | + | | | | | | +.enable | y | | | | | +.disable | y | | | | | +.is_enabled | y | | | | | + | | | | | | +.recalc_rate | | y | | | | +.round_rate | | y [1] | | | | +.determine_rate | | y [1] | | | | +.set_rate | | y | | | | + | | | | | | +.set_parent | | | n | y | n | +.get_parent | | | n | y | n | + | | | | | | +.init | | | | | | + ----------------------------------------------------------- +[1] either one of round_rate or determine_rate is required. Finally, register your clock at run-time with a hardware-specific registration function. This function simply populates struct clk_foo's -- cgit v1.2.3 From 2371dd88b80fc847a451d5eff018e165501f560a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Jul 2013 11:21:59 +0200 Subject: clk: sunxi: Add A10s gates MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Allwinner A10s has a slightly different gates set than the A10 and A13, so add these gates to the clk driver. Signed-off-by: Maxime Ripard Tested-by: Emilio López Reviewed-by: Emilio López --- Documentation/devicetree/bindings/clock/sunxi.txt | 3 + .../bindings/clock/sunxi/sun5i-a10s-gates.txt | 75 ++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index d495521a79d2..b24de1003947 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -14,13 +14,16 @@ Required properties: "allwinner,sun4i-ahb-clk" - for the AHB clock "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 + "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s "allwinner,sun4i-apb0-clk" - for the APB0 clock "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 + "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s "allwinner,sun4i-apb1-clk" - for the APB1 clock "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 + "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s Required properties for all clocks: - reg : shall be the control register address for the clock. diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt new file mode 100644 index 000000000000..d24279fe1429 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt @@ -0,0 +1,75 @@ +Gate clock outputs +------------------ + + * AXI gates ("allwinner,sun4i-axi-gates-clk") + + DRAM 0 + + * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk") + + USB0 0 + EHCI0 1 + OHCI0 2 + + SS 5 + DMA 6 + BIST 7 + MMC0 8 + MMC1 9 + MMC2 10 + + NAND 13 + SDRAM 14 + + EMAC 17 + TS 18 + + SPI0 20 + SPI1 21 + SPI2 22 + + GPS 26 + + HSTIMER 28 + + VE 32 + + TVE 34 + + LCD 36 + + CSI 40 + + HDMI 43 + DE_BE 44 + + DE_FE 46 + + IEP 51 + MALI400 52 + + * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk") + + CODEC 0 + + IIS 3 + + PIO 5 + IR 6 + + KEYPAD 10 + + * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk") + + I2C0 0 + I2C1 1 + I2C2 2 + + UART0 16 + UART1 17 + UART2 18 + UART3 19 + +Notation: + [*]: The datasheet didn't mention these, but they are present on AW code + [**]: The datasheet had this marked as "NC" but they are used on AW code -- cgit v1.2.3 From 6a721db180a22d8e2d59d864446309bc7a09c26f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 23 Jul 2013 23:34:10 +0200 Subject: clk: sunxi: Add A31 clocks support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The A31 has a mostly different clock set compared to the other older SoCs currently supported in the Allwinner clock driver. Add support for the basic useful clocks. The other ones will come in eventually. Signed-off-by: Maxime Ripard Reviewed-by: Emilio López --- Documentation/devicetree/bindings/clock/sunxi.txt | 6 ++ .../bindings/clock/sunxi/sun6i-a31-gates.txt | 83 ++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index b24de1003947..c383d1259e5c 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -8,6 +8,7 @@ Required properties: - compatible : shall be one of the following: "allwinner,sun4i-osc-clk" - for a gatable oscillator "allwinner,sun4i-pll1-clk" - for the main PLL clock + "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock "allwinner,sun4i-axi-clk" - for the AXI clock "allwinner,sun4i-axi-gates-clk" - for the AXI gates @@ -15,6 +16,8 @@ Required properties: "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s + "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 + "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 "allwinner,sun4i-apb0-clk" - for the APB0 clock "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 @@ -24,6 +27,9 @@ Required properties: "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s + "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 + "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 + "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 Required properties for all clocks: - reg : shall be the control register address for the clock. diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt new file mode 100644 index 000000000000..fe44932b5c6b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt @@ -0,0 +1,83 @@ +Gate clock outputs +------------------ + + * AHB1 gates ("allwinner,sun6i-a31-ahb1-gates-clk") + + MIPI DSI 1 + + SS 5 + DMA 6 + + MMC0 8 + MMC1 9 + MMC2 10 + MMC3 11 + + NAND1 12 + NAND0 13 + SDRAM 14 + + GMAC 17 + TS 18 + HSTIMER 19 + SPI0 20 + SPI1 21 + SPI2 22 + SPI3 23 + USB_OTG 24 + + EHCI0 26 + EHCI1 27 + + OHCI0 29 + OHCI1 30 + OHCI2 31 + VE 32 + + LCD0 36 + LCD1 37 + + CSI 40 + + HDMI 43 + DE_BE0 44 + DE_BE1 45 + DE_FE1 46 + DE_FE1 47 + + MP 50 + + GPU 52 + + DEU0 55 + DEU1 56 + DRC0 57 + DRC1 58 + + * APB1 gates ("allwinner,sun6i-a31-apb1-gates-clk") + + CODEC 0 + + DIGITAL MIC 4 + PIO 5 + + DAUDIO0 12 + DAUDIO1 13 + + * APB2 gates ("allwinner,sun6i-a31-apb2-gates-clk") + + I2C0 0 + I2C1 1 + I2C2 2 + I2C3 3 + + UART0 16 + UART1 17 + UART2 18 + UART3 19 + UART4 20 + UART5 21 + +Notation: + [*]: The datasheet didn't mention these, but they are present on AW code + [**]: The datasheet had this marked as "NC" but they are used on AW code -- cgit v1.2.3 From 1fb2e4aab8b31b15e6be5debacb4203333360fd2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 25 Jul 2013 21:06:56 +0200 Subject: clk: sunxi: Add Allwinner A20 gates MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Allwinner A20 is almost identical to the earlier A10 SoC from Allwinner on many aspects, including the clocks tree. However, since the A20 has some additionnal IPs compared to the A10, the clock tree isn't exactly the same, especially when it comes to the gated clocks available. We thus need to register different clock gates for the A20. Signed-off-by: Maxime Ripard Reviewed-by: Emilio López --- Documentation/devicetree/bindings/clock/sunxi.txt | 3 + .../bindings/clock/sunxi/sun7i-a20-gates.txt | 98 ++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index c383d1259e5c..00a5c26454eb 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -16,18 +16,21 @@ Required properties: "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s + "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 "allwinner,sun4i-apb0-clk" - for the APB0 clock "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s + "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 "allwinner,sun4i-apb1-clk" - for the APB1 clock "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 + "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt new file mode 100644 index 000000000000..357f4fdc02ef --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt @@ -0,0 +1,98 @@ +Gate clock outputs +------------------ + + * AXI gates ("allwinner,sun4i-axi-gates-clk") + + DRAM 0 + + * AHB gates ("allwinner,sun7i-a20-ahb-gates-clk") + + USB0 0 + EHCI0 1 + OHCI0 2 + EHCI1 3 + OHCI1 4 + SS 5 + DMA 6 + BIST 7 + MMC0 8 + MMC1 9 + MMC2 10 + MMC3 11 + MS 12 + NAND 13 + SDRAM 14 + + ACE 16 + EMAC 17 + TS 18 + + SPI0 20 + SPI1 21 + SPI2 22 + SPI3 23 + + SATA 25 + + HSTIMER 28 + + VE 32 + TVD 33 + TVE0 34 + TVE1 35 + LCD0 36 + LCD1 37 + + CSI0 40 + CSI1 41 + + HDMI1 42 + HDMI0 43 + DE_BE0 44 + DE_BE1 45 + DE_FE1 46 + DE_FE1 47 + + GMAC 49 + MP 50 + + MALI400 52 + + * APB0 gates ("allwinner,sun7i-a20-apb0-gates-clk") + + CODEC 0 + SPDIF 1 + AC97 2 + IIS0 3 + IIS1 4 + PIO 5 + IR0 6 + IR1 7 + IIS2 8 + + KEYPAD 10 + + * APB1 gates ("allwinner,sun7i-a20-apb1-gates-clk") + + I2C0 0 + I2C1 1 + I2C2 2 + I2C3 3 + CAN 4 + SCR 5 + PS20 6 + PS21 7 + + I2C4 15 + UART0 16 + UART1 17 + UART2 18 + UART3 19 + UART4 20 + UART5 21 + UART6 22 + UART7 23 + +Notation: + [*]: The datasheet didn't mention these, but they are present on AW code + [**]: The datasheet had this marked as "NC" but they are used on AW code -- cgit v1.2.3 From c9f3f0815909386c2dba1cdb803af5cef34ec796 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Thu, 29 Aug 2013 11:07:05 +0530 Subject: clk/exynos5420: add sclk_hdmiphy to the list of special clocks Add sclk_hdmiphy to the list of exposed clocks. This is required by hdmi driver to change the parent of hdmi clock. Signed-off-by: Rahul Sharma Acked-by: Tomasz Figa Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 9bcc4b1bff51..596a36868a56 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -59,6 +59,7 @@ clock which they consume. sclk_pwm 155 sclk_gscl_wa 156 sclk_gscl_wb 157 + sclk_hdmiphy 158 [Peripheral Clock Gates] -- cgit v1.2.3 From 9b229d8b04b4050938257e1f2a12860670e52e80 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Thu, 29 Aug 2013 11:07:06 +0530 Subject: clk/exynos5420: add gate clock for mixer sysmmu Adding sysmmu clock for mixer for exynos5420. Signed-off-by: Rahul Sharma Acked-by: Tomasz Figa Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 596a36868a56..5758a690d789 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -180,6 +180,7 @@ clock which they consume. fimc_lite3 495 aclk_g3d 500 g3d 501 + smmu_mixer 502 Example 1: An example of a clock controller node is listed below. -- cgit v1.2.3 From 4625f1b5d44c7f38801c0553fa90b33577307843 Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Thu, 29 Aug 2013 11:07:08 +0530 Subject: clk/exynos5420: add hdmi mux to change parents in hdmi driver hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent. Signed-off-by: Rahul Sharma Acked-by: Tomasz Figa Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 5758a690d789..343430bd5573 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -182,6 +182,11 @@ clock which they consume. g3d 501 smmu_mixer 502 + Mux ID + ---------------------------- + + mout_hdmi 640 + Example 1: An example of a clock controller node is listed below. clock: clock-controller@0x10010000 { -- cgit v1.2.3 From 0044cbcd667520fedbd96d07c20cfe5b7473f71a Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Thu, 29 Aug 2013 11:07:09 +0530 Subject: clk/exynos5420: assign dout_pixel id to pixel clock divider dout_pixel is a new ID allocated for pixel clock divider. It is queried in the driver to pass as the parent to hdmi clock while switching between parents. Signed-off-by: Rahul Sharma Acked-by: Tomasz Figa Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 343430bd5573..32aa34ecad36 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -187,6 +187,11 @@ clock which they consume. mout_hdmi 640 + Divider ID + ---------------------------- + + dout_pixel 768 + Example 1: An example of a clock controller node is listed below. clock: clock-controller@0x10010000 { -- cgit v1.2.3 From f51a87a9fbd00d4081874dd24271071a1b491daa Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Mon, 26 Aug 2013 19:08:56 +0200 Subject: pwm: samsung: Update DT bindings documentation to cover clocks PWM driver consumes at least one and up to three clocks, which need to be specified in device tree when used. This patch updates bindings documentation to add information about clocks. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Acked-by: Stephen Warren Reviewed-by: Sylwester Nawrocki Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/pwm/pwm-samsung.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt index ac67c687a327..39f0ca7008ba 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt @@ -19,6 +19,16 @@ Required properties: - reg: base address and size of register area - interrupts: list of timer interrupts (one interrupt per timer, starting at timer 0) +- clock-names: should contain all following required clock names: + - "timers" - PWM base clock used to generate PWM signals, + and any subset of following optional clock names: + - "pwm-tclk0" - first external PWM clock source, + - "pwm-tclk1" - second external PWM clock source. + Note that not all IP variants allow using all external clock sources. + Refer to SoC documentation to learn which clock source configurations + are available. +- clocks: should contain clock specifiers of all clocks, which input names + have been specified in clock-names property, in same order. - #pwm-cells: number of cells used for PWM specifier - must be 3 the specifier format is as follows: - phandle to PWM controller node @@ -38,6 +48,8 @@ Example: reg = <0x7f006000 0x1000>; interrupt-parent = <&vic0>; interrupts = <23>, <24>, <25>, <27>, <28>; + clocks = <&clock 67>; + clock-names = "timers"; samsung,pwm-outputs = <0>, <1>; #pwm-cells = <3>; } -- cgit v1.2.3