From 38581ddc48b761936fc65948d0a0f6fe0db1aa31 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 11 Dec 2018 10:07:06 -0800 Subject: clk: Collapse gpio clk kerneldoc We have two kernel-docs for gpio clks, but there is only one gpio clk structure. Collapse the two so we have proper kerneldoc for this basic clk type. Signed-off-by: Stephen Boyd --- include/linux/clk-provider.h | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index e443fa9fa859..b65b48cc31f1 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -712,16 +712,19 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, unsigned long flags); void clk_hw_unregister_composite(struct clk_hw *hw); -/*** - * struct clk_gpio_gate - gpio gated clock +/** + * struct clk_gpio - gpio gated clock * * @hw: handle between common and hardware-specific interfaces * @gpiod: gpio descriptor * - * Clock with a gpio control for enabling and disabling the parent clock. - * Implements .enable, .disable and .is_enabled + * Clock with a gpio control for enabling and disabling the parent clock + * or switching between two parents by asserting or deasserting the gpio. + * + * Implements .enable, .disable and .is_enabled or + * .get_parent, .set_parent and .determine_rate depending on which clk_ops + * is used. */ - struct clk_gpio { struct clk_hw hw; struct gpio_desc *gpiod; @@ -738,16 +741,6 @@ struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, unsigned long flags); void clk_hw_unregister_gpio_gate(struct clk_hw *hw); -/** - * struct clk_gpio_mux - gpio controlled clock multiplexer - * - * @hw: see struct clk_gpio - * @gpiod: gpio descriptor to select the parent of this clock multiplexer - * - * Clock with a gpio control for selecting the parent clock. - * Implements .get_parent, .set_parent and .determine_rate - */ - extern const struct clk_ops clk_gpio_mux_ops; struct clk *clk_register_gpio_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, -- cgit v1.2.3 From 9fe9b7ab4d050eaf646728752b320043c59dc214 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 11 Dec 2018 10:49:40 -0800 Subject: clk: Document deprecated things We don't want driver authors to use the struct clk based registration and provider APIs. Instead, they should use the clk_hw based APIs. Add some notes in the kerneldoc to this effect. Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 15 ++++++++++----- include/linux/clk-provider.h | 2 +- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 75d13c0eff12..592e315f7cfd 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -3240,8 +3240,10 @@ void __clk_free_clk(struct clk *clk) * @dev: device that is registering this clock * @hw: link to hardware-specific clock data * - * clk_register is the primary interface for populating the clock tree with new - * clock nodes. It returns a pointer to the newly allocated struct clk which + * clk_register is the *deprecated* interface for populating the clock tree with + * new clock nodes. Use clk_hw_register() instead. + * + * Returns: a pointer to the newly allocated struct clk which * cannot be dereferenced by driver code but may be used in conjunction with the * rest of the clock API. In the event of an error clk_register will return an * error code; drivers must test for an error code after calling clk_register. @@ -3486,9 +3488,10 @@ static void devm_clk_hw_release(struct device *dev, void *res) * @dev: device that is registering this clock * @hw: link to hardware-specific clock data * - * Managed clk_register(). Clocks returned from this function are - * automatically clk_unregister()ed on driver detach. See clk_register() for - * more information. + * Managed clk_register(). This function is *deprecated*, use devm_clk_hw_register() instead. + * + * Clocks returned from this function are automatically clk_unregister()ed on + * driver detach. See clk_register() for more information. */ struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw) { @@ -3820,6 +3823,8 @@ EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get); * @np: Device node pointer associated with clock provider * @clk_src_get: callback for decoding clock * @data: context pointer for @clk_src_get callback. + * + * This function is *deprecated*. Use of_clk_add_hw_provider() instead. */ int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *clkspec, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index b65b48cc31f1..adb8a58e213c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -24,7 +24,7 @@ #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ /* unused */ -#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ +#define CLK_IS_BASIC BIT(5) /* deprecated, don't use */ #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ -- cgit v1.2.3 From 31f6e8700fa25b3b9534da9a1d787661b8adad87 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 11 Dec 2018 10:58:33 -0800 Subject: clk: Document CLK_MUX_READ_ONLY mux flag This flag isn't documented. Document it. Signed-off-by: Stephen Boyd --- include/linux/clk-provider.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index adb8a58e213c..edff3c5883bc 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -499,6 +499,8 @@ void clk_hw_unregister_divider(struct clk_hw *hw); * register, and mask of mux bits are in higher 16-bit of this register. * While setting the mux bits, higher 16-bit should also be updated to * indicate changing mux bits. + * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the + * .get_parent clk_op. * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired * frequency. */ -- cgit v1.2.3 From 777c1a40a34f183640b33ff142c5ab3ef1748974 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 11 Dec 2018 13:24:50 -0800 Subject: clk: Document __clk_mux_determine_rate() It had some documentation, but not kerneldoc style so it wasn't getting picked up. Add some docs so scripts can pick this function out. Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 592e315f7cfd..c9860074899b 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -519,9 +519,15 @@ void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, EXPORT_SYMBOL_GPL(clk_hw_set_rate_range); /* + * __clk_mux_determine_rate - clk_ops::determine_rate implementation for a mux type clk + * @hw: mux type clk to determine rate on + * @req: rate request, also used to return preferred parent and frequencies + * * Helper for finding best parent to provide a given frequency. This can be used * directly as a determine_rate callback (e.g. for a mux), or from a more * complex clock that may combine a mux with other operations. + * + * Returns: 0 on success, -EERROR value on error */ int __clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) -- cgit v1.2.3 From 7150e182c80ab289b8ce0eeaae62098bf3921124 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 14 Dec 2018 09:18:41 -0800 Subject: clk: nxp: Drop 'flags' on fixed_rate clk macro The flags argument here is always 0, and we want to get rid of the flags member of the clk_fixed_rate struct. So remove this here and just pass 0 when it's used. Signed-off-by: Stephen Boyd --- drivers/clk/nxp/clk-lpc32xx.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index 5eeecee17b69..7524d19fe60b 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -1085,13 +1085,12 @@ struct clk_hw_proto { }; }; -#define LPC32XX_DEFINE_FIXED(_idx, _rate, _flags) \ +#define LPC32XX_DEFINE_FIXED(_idx, _rate) \ [CLK_PREFIX(_idx)] = { \ .type = CLK_FIXED, \ { \ .f = { \ .fixed_rate = (_rate), \ - .flags = (_flags), \ }, \ }, \ } @@ -1225,7 +1224,7 @@ struct clk_hw_proto { } static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = { - LPC32XX_DEFINE_FIXED(RTC, 32768, 0), + LPC32XX_DEFINE_FIXED(RTC, 32768), LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)), LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE), LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE), @@ -1468,7 +1467,7 @@ static struct clk * __init lpc32xx_clk_register(u32 id) struct clk_fixed_rate *fixed = &clk_hw->f; clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name, - parents[0], fixed->flags, fixed->fixed_rate); + parents[0], 0, fixed->fixed_rate); break; } default: -- cgit v1.2.3 From 7374faa92edce7af6d69d0a2968198e9b919a281 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 11 Dec 2018 10:58:54 -0800 Subject: clk: Remove 'flags' member of struct clk_fixed_rate This member is never used nor documented in the kerneldoc. Remove it. Signed-off-by: Stephen Boyd --- include/linux/clk-provider.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index edff3c5883bc..a1705a0f08c7 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -307,7 +307,6 @@ struct clk_fixed_rate { struct clk_hw hw; unsigned long fixed_rate; unsigned long fixed_accuracy; - u8 flags; }; #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) -- cgit v1.2.3 From 73d4f945f6eacc8f4fadd61020faea3c6dc602dc Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 1 Feb 2019 15:39:50 -0800 Subject: clk: Document and simplify clk_core_get_rate_nolock() This function uses a few gotos and doesn't explain why parents and numbers of parents are being checked before returning different values for the clk's rate. Document and simplify this function somewhat to make this better. Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index c9860074899b..79d0466cd180 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -345,23 +345,18 @@ unsigned int __clk_get_enable_count(struct clk *clk) static unsigned long clk_core_get_rate_nolock(struct clk_core *core) { - unsigned long ret; - - if (!core) { - ret = 0; - goto out; - } - - ret = core->rate; - - if (!core->num_parents) - goto out; + if (!core) + return 0; - if (!core->parent) - ret = 0; + if (!core->num_parents || core->parent) + return core->rate; -out: - return ret; + /* + * Clk must have a parent because num_parents > 0 but the parent isn't + * known yet. Best to return 0 as the rate of this clk until we can + * properly recalc the rate based on the parent's rate. + */ + return 0; } unsigned long clk_hw_get_rate(const struct clk_hw *hw) -- cgit v1.2.3 From 043f44aba9a871da521fe6ebecd5c63e406256ff Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 6 Mar 2019 14:13:41 -0800 Subject: clk: highbank: Convert to CLK_IS_CRITICAL This code is hand-rolling the CLK_IS_CRITICAL flag to keep a clk on once it's registered. Just mark it as CLK_IS_CRITICAL instead so that the framework can handle keeping the clk prepared and enabled for all eternity. Cc: Rob Herring Signed-off-by: Stephen Boyd --- drivers/clk/clk-highbank.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 727ed8e1bb72..bc095382cf43 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -272,7 +271,7 @@ static const struct clk_ops periclk_ops = { .set_rate = clk_periclk_set_rate, }; -static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops) +static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops, unsigned long clkflags) { u32 reg; struct hb_clk *hb_clk; @@ -284,11 +283,11 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk rc = of_property_read_u32(node, "reg", ®); if (WARN_ON(rc)) - return NULL; + return; hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL); if (WARN_ON(!hb_clk)) - return NULL; + return; /* Map system registers */ srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); @@ -300,7 +299,7 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk init.name = clk_name; init.ops = ops; - init.flags = 0; + init.flags = clkflags; parent_name = of_clk_get_parent_name(node, 0); init.parent_names = &parent_name; init.num_parents = 1; @@ -310,33 +309,31 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk rc = clk_hw_register(NULL, &hb_clk->hw); if (WARN_ON(rc)) { kfree(hb_clk); - return NULL; + return; } - rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw); - return hb_clk->hw.clk; + of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw); } static void __init hb_pll_init(struct device_node *node) { - hb_clk_init(node, &clk_pll_ops); + hb_clk_init(node, &clk_pll_ops, 0); } CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init); static void __init hb_a9periph_init(struct device_node *node) { - hb_clk_init(node, &a9periphclk_ops); + hb_clk_init(node, &a9periphclk_ops, 0); } CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init); static void __init hb_a9bus_init(struct device_node *node) { - struct clk *clk = hb_clk_init(node, &a9bclk_ops); - clk_prepare_enable(clk); + hb_clk_init(node, &a9bclk_ops, CLK_IS_CRITICAL); } CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init); static void __init hb_emmc_init(struct device_node *node) { - hb_clk_init(node, &periclk_ops); + hb_clk_init(node, &periclk_ops, 0); } CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init); -- cgit v1.2.3 From 58b5c8acba12fdf375dd30074c07730e67b97c3f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 4 Mar 2019 14:11:28 +0100 Subject: clk: meson-g12a: add cpu clock bindings Add Amlogic G12A Family CPU clocks bindings, only export CPU_CLK since it should be the only ID used. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190304131129.7762-2-narmstrong@baylibre.com --- include/dt-bindings/clock/g12a-clkc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 83b657038d1e..d7bf0830c87d 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -131,5 +131,6 @@ #define CLKID_MALI_1 174 #define CLKID_MALI 175 #define CLKID_MPLL_5OM 177 +#define CLKID_CPU_CLK 187 #endif /* __G12A_CLKC_H */ -- cgit v1.2.3 From dc6276f57617344c9e78332c682ea1e982527e09 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 4 Mar 2019 11:53:58 +0100 Subject: clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id When submitted v2 of the G12A AO-CLK IDs, the SAR_ADC_SEL ID was moved to the internal non-exported bindings, but this clock is necessary and mandatory for the SAR ADC bindings. Export it back to the public bindings. Fixes: be3d960b0aeb ("dt-bindings: clk: add G12A AO Clock and Reset Bindings") Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190304105358.4987-1-narmstrong@baylibre.com --- drivers/clk/meson/g12a-aoclk.h | 1 - include/dt-bindings/clock/g12a-aoclkc.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a-aoclk.h b/drivers/clk/meson/g12a-aoclk.h index 04b0d5506641..666b4493822c 100644 --- a/drivers/clk/meson/g12a-aoclk.h +++ b/drivers/clk/meson/g12a-aoclk.h @@ -16,7 +16,6 @@ * to expose, such as the internal muxes and dividers of composite clocks, * will remain defined here. */ -#define CLKID_AO_SAR_ADC_SEL 16 #define CLKID_AO_SAR_ADC_DIV 17 #define CLKID_AO_CTS_OSCIN 19 #define CLKID_AO_32K_PRE 20 diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h index 8db01ffbeb06..5ac66a2eee0f 100644 --- a/include/dt-bindings/clock/g12a-aoclkc.h +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -26,6 +26,7 @@ #define CLKID_AO_M4_FCLK 13 #define CLKID_AO_M4_HCLK 14 #define CLKID_AO_CLK81 15 +#define CLKID_AO_SAR_ADC_SEL 16 #define CLKID_AO_SAR_ADC_CLK 18 #define CLKID_AO_32K 23 #define CLKID_AO_CEC 27 -- cgit v1.2.3 From 17750f5218764a06172a294b23275a950e2adce9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 7 Mar 2019 15:14:54 +0100 Subject: dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID Add a clock ID for the reference clock feeding the USB3+PCIe Combo PHY. Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190307141455.23879-3-narmstrong@baylibre.com --- include/dt-bindings/clock/g12a-clkc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index d7bf0830c87d..30303728fe09 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -132,5 +132,6 @@ #define CLKID_MALI 175 #define CLKID_MPLL_5OM 177 #define CLKID_CPU_CLK 187 +#define CLKID_PCIE_PLL 201 #endif /* __G12A_CLKC_H */ -- cgit v1.2.3 From e4c1e95facf9ddf70bb1a737f8ab1c7d38acd234 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 13 Feb 2019 10:58:35 +0100 Subject: dt-bindings: clock: axg-audio: unexpose controller inputs Remove the bindings ID of the clock input of the controller. These clocks are purely internal to the controller, exposing them was a mistake. Actually, these should not even be in the provider and have IDs to begin with. Unexpose these IDs before: * someone starts using them (even if there no valid reason to do so) * the actual clocks are removed. The fact that they exist is just the result of an ugly hack. This will be resolved in CCF when we can reference DT directly in parent table. Signed-off-by: Jerome Brunet Acked-by: Maxime Jourdan Reviewed-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190213095835.17448-1-jbrunet@baylibre.com --- drivers/clk/meson/axg-audio.h | 20 ++++++++++++++++++++ include/dt-bindings/clock/axg-audio-clkc.h | 20 -------------------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h index 7191b39c9d65..644f0b0fddf2 100644 --- a/drivers/clk/meson/axg-audio.h +++ b/drivers/clk/meson/axg-audio.h @@ -60,6 +60,26 @@ #define AUD_CLKID_MST5 6 #define AUD_CLKID_MST6 7 #define AUD_CLKID_MST7 8 +#define AUD_CLKID_SLV_SCLK0 9 +#define AUD_CLKID_SLV_SCLK1 10 +#define AUD_CLKID_SLV_SCLK2 11 +#define AUD_CLKID_SLV_SCLK3 12 +#define AUD_CLKID_SLV_SCLK4 13 +#define AUD_CLKID_SLV_SCLK5 14 +#define AUD_CLKID_SLV_SCLK6 15 +#define AUD_CLKID_SLV_SCLK7 16 +#define AUD_CLKID_SLV_SCLK8 17 +#define AUD_CLKID_SLV_SCLK9 18 +#define AUD_CLKID_SLV_LRCLK0 19 +#define AUD_CLKID_SLV_LRCLK1 20 +#define AUD_CLKID_SLV_LRCLK2 21 +#define AUD_CLKID_SLV_LRCLK3 22 +#define AUD_CLKID_SLV_LRCLK4 23 +#define AUD_CLKID_SLV_LRCLK5 24 +#define AUD_CLKID_SLV_LRCLK6 25 +#define AUD_CLKID_SLV_LRCLK7 26 +#define AUD_CLKID_SLV_LRCLK8 27 +#define AUD_CLKID_SLV_LRCLK9 28 #define AUD_CLKID_MST_A_MCLK_SEL 59 #define AUD_CLKID_MST_B_MCLK_SEL 60 #define AUD_CLKID_MST_C_MCLK_SEL 61 diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h index fd9c362099d9..eafb0de8466b 100644 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -7,26 +7,6 @@ #ifndef __AXG_AUDIO_CLKC_BINDINGS_H #define __AXG_AUDIO_CLKC_BINDINGS_H -#define AUD_CLKID_SLV_SCLK0 9 -#define AUD_CLKID_SLV_SCLK1 10 -#define AUD_CLKID_SLV_SCLK2 11 -#define AUD_CLKID_SLV_SCLK3 12 -#define AUD_CLKID_SLV_SCLK4 13 -#define AUD_CLKID_SLV_SCLK5 14 -#define AUD_CLKID_SLV_SCLK6 15 -#define AUD_CLKID_SLV_SCLK7 16 -#define AUD_CLKID_SLV_SCLK8 17 -#define AUD_CLKID_SLV_SCLK9 18 -#define AUD_CLKID_SLV_LRCLK0 19 -#define AUD_CLKID_SLV_LRCLK1 20 -#define AUD_CLKID_SLV_LRCLK2 21 -#define AUD_CLKID_SLV_LRCLK3 22 -#define AUD_CLKID_SLV_LRCLK4 23 -#define AUD_CLKID_SLV_LRCLK5 24 -#define AUD_CLKID_SLV_LRCLK6 25 -#define AUD_CLKID_SLV_LRCLK7 26 -#define AUD_CLKID_SLV_LRCLK8 27 -#define AUD_CLKID_SLV_LRCLK9 28 #define AUD_CLKID_DDR_ARB 29 #define AUD_CLKID_PDM 30 #define AUD_CLKID_TDMIN_A 31 -- cgit v1.2.3 From 19478907951afef2249506acc8afec89c3133d9d Mon Sep 17 00:00:00 2001 From: Maxime Jourdan Date: Tue, 19 Mar 2019 11:11:37 +0100 Subject: dt-bindings: clk: g12a-clkc: add VDEC clock IDs Expose the three clocks related to the video decoder. Signed-off-by: Maxime Jourdan Reviewed-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190319101138.27520-2-mjourdan@baylibre.com --- include/dt-bindings/clock/g12a-clkc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 30303728fe09..82c9e0c020b2 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -133,5 +133,8 @@ #define CLKID_MPLL_5OM 177 #define CLKID_CPU_CLK 187 #define CLKID_PCIE_PLL 201 +#define CLKID_VDEC_1 204 +#define CLKID_VDEC_HEVC 207 +#define CLKID_VDEC_HEVCF 210 #endif /* __G12A_CLKC_H */ -- cgit v1.2.3 From 370294e2667fa1648eb05aab6c4657419634ff83 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 4 Mar 2019 14:11:29 +0100 Subject: clk: meson: g12a: add cpu clocks Add the Amlogic G12A Family CPU Clock tree in read/only for now. The CPU clock can either use the SYS_PLL for > 1GHz frequencies or use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch muxes. Proper DVFS support will come in a second time. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Acked-by: Jerome Brunet [narmstrong: fixed cpu clocks namings] Link: https://lkml.kernel.org/r/20190304131129.7762-3-narmstrong@baylibre.com --- drivers/clk/meson/g12a.c | 350 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 22 ++- 2 files changed, 371 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 0e1ce8c03259..10ba8bc4646d 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -150,6 +150,318 @@ static struct clk_regmap g12a_sys_pll = { }, }; +static struct clk_regmap g12a_sys_pll_div16_en = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "sys_pll_div16_en", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "sys_pll" }, + .num_parents = 1, + /* + * This clock is used to debug the sys_pll range + * Linux should not change it at runtime + */ + }, +}; + +static struct clk_fixed_factor g12a_sys_pll_div16 = { + .mult = 1, + .div = 16, + .hw.init = &(struct clk_init_data){ + .name = "sys_pll_div16", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "sys_pll_div16_en" }, + .num_parents = 1, + }, +}; + +/* Datasheet names this field as "premux0" */ +static struct clk_regmap g12a_cpu_clk_premux0 = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x3, + .shift = 0, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_dyn0_sel", + .ops = &clk_regmap_mux_ro_ops, + .parent_names = (const char *[]){ IN_PREFIX "xtal", + "fclk_div2", + "fclk_div3" }, + .num_parents = 3, + }, +}; + +/* Datasheet names this field as "mux0_divn_tcnt" */ +static struct clk_regmap g12a_cpu_clk_mux0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .shift = 4, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_dyn0_div", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" }, + .num_parents = 1, + }, +}; + +/* Datasheet names this field as "postmux0" */ +static struct clk_regmap g12a_cpu_clk_postmux0 = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x1, + .shift = 2, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_dyn0", + .ops = &clk_regmap_mux_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_dyn0_sel", + "cpu_clk_dyn0_div" }, + .num_parents = 2, + }, +}; + +/* Datasheet names this field as "premux1" */ +static struct clk_regmap g12a_cpu_clk_premux1 = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x3, + .shift = 16, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_dyn1_sel", + .ops = &clk_regmap_mux_ro_ops, + .parent_names = (const char *[]){ IN_PREFIX "xtal", + "fclk_div2", + "fclk_div3" }, + .num_parents = 3, + }, +}; + +/* Datasheet names this field as "Mux1_divn_tcnt" */ +static struct clk_regmap g12a_cpu_clk_mux1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .shift = 20, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_dyn1_div", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_dyn1_sel" }, + .num_parents = 1, + }, +}; + +/* Datasheet names this field as "postmux1" */ +static struct clk_regmap g12a_cpu_clk_postmux1 = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x1, + .shift = 18, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_dyn1", + .ops = &clk_regmap_mux_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_dyn1_sel", + "cpu_clk_dyn1_div" }, + .num_parents = 2, + }, +}; + +/* Datasheet names this field as "Final_dyn_mux_sel" */ +static struct clk_regmap g12a_cpu_clk_dyn = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x1, + .shift = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_dyn", + .ops = &clk_regmap_mux_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_dyn0", + "cpu_clk_dyn1" }, + .num_parents = 2, + }, +}; + +/* Datasheet names this field as "Final_mux_sel" */ +static struct clk_regmap g12a_cpu_clk = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x1, + .shift = 11, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk", + .ops = &clk_regmap_mux_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_dyn", + "sys_pll" }, + .num_parents = 2, + }, +}; + +static struct clk_regmap g12a_cpu_clk_div16_en = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 1, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_clk_div16_en", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + /* + * This clock is used to debug the cpu_clk range + * Linux should not change it at runtime + */ + }, +}; + +static struct clk_fixed_factor g12a_cpu_clk_div16 = { + .mult = 1, + .div = 16, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div16", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk_div16_en" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap g12a_cpu_clk_apb_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .shift = 3, + .width = 3, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_apb_div", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap g12a_cpu_clk_apb = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 1, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_clk_apb", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_apb_div" }, + .num_parents = 1, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ + }, +}; + +static struct clk_regmap g12a_cpu_clk_atb_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .shift = 6, + .width = 3, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_atb_div", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap g12a_cpu_clk_atb = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 17, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_clk_atb", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_atb_div" }, + .num_parents = 1, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ + }, +}; + +static struct clk_regmap g12a_cpu_clk_axi_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .shift = 9, + .width = 3, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_axi_div", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap g12a_cpu_clk_axi = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 18, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_clk_axi", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_axi_div" }, + .num_parents = 1, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ + }, +}; + +static struct clk_regmap g12a_cpu_clk_trace_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .shift = 20, + .width = 3, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_trace_div", + .ops = &clk_regmap_divider_ro_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap g12a_cpu_clk_trace = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 23, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_clk_trace", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "cpu_clk_trace_div" }, + .num_parents = 1, + /* + * This clock is set by the ROM monitor code, + * Linux should not change it at runtime + */ + }, +}; + static const struct pll_mult_range g12a_gp0_pll_mult_range = { .min = 55, .max = 255, @@ -2167,6 +2479,26 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_MALI] = &g12a_mali.hw, [CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw, [CLKID_MPLL_5OM] = &g12a_mpll_50m.hw, + [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, + [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, + [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, + [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, + [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, + [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, + [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, + [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, + [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, + [CLKID_CPU_CLK] = &g12a_cpu_clk.hw, + [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, + [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, + [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, + [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, + [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, + [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, + [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, + [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, + [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, + [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -2335,6 +2667,24 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &g12a_mali_1, &g12a_mali, &g12a_mpll_50m, + &g12a_sys_pll_div16_en, + &g12a_cpu_clk_premux0, + &g12a_cpu_clk_mux0_div, + &g12a_cpu_clk_postmux0, + &g12a_cpu_clk_premux1, + &g12a_cpu_clk_mux1_div, + &g12a_cpu_clk_postmux1, + &g12a_cpu_clk_dyn, + &g12a_cpu_clk, + &g12a_cpu_clk_div16_en, + &g12a_cpu_clk_apb_div, + &g12a_cpu_clk_apb, + &g12a_cpu_clk_atb_div, + &g12a_cpu_clk_atb, + &g12a_cpu_clk_axi_div, + &g12a_cpu_clk_axi, + &g12a_cpu_clk_trace_div, + &g12a_cpu_clk_trace, }; static const struct meson_eeclkc_data g12a_clkc_data = { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index f399dfe1401c..70aa469ca1cf 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -50,6 +50,7 @@ #define HHI_GCLK_MPEG2 0x148 #define HHI_GCLK_OTHER 0x150 #define HHI_GCLK_OTHER2 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c #define HHI_VID_CLK_DIV 0x164 #define HHI_MPEG_CLK_CNTL 0x174 #define HHI_AUD_CLK_CNTL 0x178 @@ -166,8 +167,27 @@ #define CLKID_MALI_0_DIV 170 #define CLKID_MALI_1_DIV 173 #define CLKID_MPLL_5OM_DIV 176 +#define CLKID_SYS_PLL_DIV16_EN 178 +#define CLKID_SYS_PLL_DIV16 179 +#define CLKID_CPU_CLK_DYN0_SEL 180 +#define CLKID_CPU_CLK_DYN0_DIV 181 +#define CLKID_CPU_CLK_DYN0 182 +#define CLKID_CPU_CLK_DYN1_SEL 183 +#define CLKID_CPU_CLK_DYN1_DIV 184 +#define CLKID_CPU_CLK_DYN1 185 +#define CLKID_CPU_CLK_DYN 186 +#define CLKID_CPU_CLK_DIV16_EN 188 +#define CLKID_CPU_CLK_DIV16 189 +#define CLKID_CPU_CLK_APB_DIV 190 +#define CLKID_CPU_CLK_APB 191 +#define CLKID_CPU_CLK_ATB_DIV 192 +#define CLKID_CPU_CLK_ATB 193 +#define CLKID_CPU_CLK_AXI_DIV 194 +#define CLKID_CPU_CLK_AXI 195 +#define CLKID_CPU_CLK_TRACE_DIV 196 +#define CLKID_CPU_CLK_TRACE 197 -#define NR_CLKS 178 +#define NR_CLKS 198 /* include the CLKIDs that have been made part of the DT binding */ #include -- cgit v1.2.3 From 23e9ae2826466f17d4733b80bf1cc98645e90ef2 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 19 Mar 2019 22:41:23 +0100 Subject: dt-bindings: clock: meson8b: drop the "ABP" clock definition Commit 8e1dd17c8b0e3f ("dt-bindings: clock: meson8b: export the CPU post dividers") added a new clock ID "CLKID_ABP" which contains a typo. This was fixed by adding a new (typo-free) #define CLKID_APB in commit 40d08f774c17ad ("dt-bindings: clock: meson8b: add APB clock definition"). Now that the new #define is used by the driver we can remove the old one (because the old one is not used anywhere). Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190319214123.27219-2-martin.blumenstingl@googlemail.com --- include/dt-bindings/clock/meson8b-clkc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 8067077a62ca..cd11628f50f8 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -103,7 +103,6 @@ #define CLKID_MPLL1 94 #define CLKID_MPLL2 95 #define CLKID_NAND_CLK 112 -#define CLKID_ABP 124 #define CLKID_APB 124 #define CLKID_PERIPH 126 #define CLKID_AXI 128 -- cgit v1.2.3 From 39b8500283b45252e2f9ad9d60992f2c0d3a1659 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 7 Mar 2019 15:14:53 +0100 Subject: clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL The Meson G12A PCIE PLL is fined tuned to deliver a very precise 100MHz reference clock for the PCIe Analog PHY, and thus requires a strict register sequence to enable the PLL. To simplify, use the _init() op to enable the PLL and keep the other ops except set_rate since the rate is fixed. Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190307141455.23879-2-narmstrong@baylibre.com --- drivers/clk/meson/clk-pll.c | 26 ++++++++++++++++++++++++++ drivers/clk/meson/clk-pll.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 41e16dd7272a..6a88dd75ccf0 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -303,6 +303,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) return 1; } +static int meson_clk_pcie_pll_enable(struct clk_hw *hw) +{ + meson_clk_pll_init(hw); + + if (meson_clk_pll_wait_lock(hw)) + return -EIO; + + return 0; +} + static int meson_clk_pll_enable(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); @@ -387,6 +397,22 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +/* + * The Meson G12A PCIE PLL is fined tuned to deliver a very precise + * 100MHz reference clock for the PCIe Analog PHY, and thus requires + * a strict register sequence to enable the PLL. + * To simplify, re-use the _init() op to enable the PLL and keep + * the other ops except set_rate since the rate is fixed. + */ +const struct clk_ops meson_clk_pcie_pll_ops = { + .recalc_rate = meson_clk_pll_recalc_rate, + .round_rate = meson_clk_pll_round_rate, + .is_enabled = meson_clk_pll_is_enabled, + .enable = meson_clk_pcie_pll_enable, + .disable = meson_clk_pll_disable +}; +EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops); + const struct clk_ops meson_clk_pll_ops = { .init = meson_clk_pll_init, .recalc_rate = meson_clk_pll_recalc_rate, diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 55af2e285b1b..367efd0f6410 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -45,5 +45,6 @@ struct meson_clk_pll_data { extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; +extern const struct clk_ops meson_clk_pcie_pll_ops; #endif /* __MESON_CLK_PLL_H */ -- cgit v1.2.3 From 133bb341b99d096d332108f412234d0cf641c15d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 21 Mar 2019 10:20:10 +0100 Subject: dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN When submitted v2 of the G12A AO-CLK IDs, the CLKID_AO_CTS_OSCIN was moved to the internal non-exported bindings, but this clock is necessary for the second AO-CEC-B module since it embeds the 32768Hz dual-divider clock generator unlike the AO-CEC-A module. Export it back to the public bindings. Fixes: be3d960b0aeb ("dt-bindings: clk: add G12A AO Clock and Reset Bindings") Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Link: https://lkml.kernel.org/r/20190321092010.14382-1-narmstrong@baylibre.com --- drivers/clk/meson/g12a-aoclk.h | 1 - include/dt-bindings/clock/g12a-aoclkc.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a-aoclk.h b/drivers/clk/meson/g12a-aoclk.h index 666b4493822c..a67c8a7cd7c4 100644 --- a/drivers/clk/meson/g12a-aoclk.h +++ b/drivers/clk/meson/g12a-aoclk.h @@ -17,7 +17,6 @@ * will remain defined here. */ #define CLKID_AO_SAR_ADC_DIV 17 -#define CLKID_AO_CTS_OSCIN 19 #define CLKID_AO_32K_PRE 20 #define CLKID_AO_32K_DIV 21 #define CLKID_AO_32K_SEL 22 diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h index 5ac66a2eee0f..e916e49ff288 100644 --- a/include/dt-bindings/clock/g12a-aoclkc.h +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -28,6 +28,7 @@ #define CLKID_AO_CLK81 15 #define CLKID_AO_SAR_ADC_SEL 16 #define CLKID_AO_SAR_ADC_CLK 18 +#define CLKID_AO_CTS_OSCIN 19 #define CLKID_AO_32K 23 #define CLKID_AO_CEC 27 #define CLKID_AO_CTS_RTC_OSCIN 28 -- cgit v1.2.3 From 34775209ba37bff3b4e60ddee0a2d69966146a5d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 7 Mar 2019 15:14:55 +0100 Subject: clk: meson-g12a: add PCIE PLL clocks Add the PCIe reference clock feeding the USB3 + PCIE combo PHY. This PLL needs a very precise register sequence to permit to be locked, thus using the specific clk-pll pcie ops. The PLL is then followed by : - a fixed /2 divider - a 5-bit 1-based divider - a final /2 divider This reference clock is fixed to 100MHz, thus only a single PLL setup is added. Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190307141455.23879-4-narmstrong@baylibre.com --- drivers/clk/meson/g12a.c | 118 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 5 +- 2 files changed, 122 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 10ba8bc4646d..a47435f91f2f 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -614,6 +614,118 @@ static struct clk_regmap g12a_hifi_pll = { }, }; +/* + * The Meson G12A PCIE PLL is fined tuned to deliver a very precise + * 100MHz reference clock for the PCIe Analog PHY, and thus requires + * a strict register sequence to enable the PLL. + */ +static const struct reg_sequence g12a_pcie_pll_init_regs[] = { + { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 }, + { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 }, + { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 }, + { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 }, + { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 }, + { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 }, + { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 }, + { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 }, + { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 }, + { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 }, + { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 }, + { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 }, +}; + +/* Keep a single entry table for recalc/round_rate() ops */ +static const struct pll_params_table g12a_pcie_pll_table[] = { + PLL_PARAMS(150, 1), + {0, 0}, +}; + +static struct clk_regmap g12a_pcie_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 10, + .width = 5, + }, + .frac = { + .reg_off = HHI_PCIE_PLL_CNTL1, + .shift = 0, + .width = 12, + }, + .l = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 29, + .width = 1, + }, + .table = g12a_pcie_pll_table, + .init_regs = g12a_pcie_pll_init_regs, + .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_dco", + .ops = &meson_clk_pcie_pll_ops, + .parent_names = (const char *[]){ IN_PREFIX "xtal" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_dco_div2", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "pcie_pll_dco" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_pcie_pll_od = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_PCIE_PLL_CNTL0, + .shift = 16, + .width = 5, + .flags = CLK_DIVIDER_ROUND_CLOSEST | + CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, + }, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_od", + .ops = &clk_regmap_divider_ops, + .parent_names = (const char *[]){ "pcie_pll_dco_div2" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor g12a_pcie_pll = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_pll", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "pcie_pll_od" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap g12a_hdmi_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { @@ -2499,6 +2611,10 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, + [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, + [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, + [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, + [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -2685,6 +2801,8 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &g12a_cpu_clk_axi, &g12a_cpu_clk_trace_div, &g12a_cpu_clk_trace, + &g12a_pcie_pll_od, + &g12a_pcie_pll_dco, }; static const struct meson_eeclkc_data g12a_clkc_data = { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 70aa469ca1cf..1393a09730a6 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -186,8 +186,11 @@ #define CLKID_CPU_CLK_AXI 195 #define CLKID_CPU_CLK_TRACE_DIV 196 #define CLKID_CPU_CLK_TRACE 197 +#define CLKID_PCIE_PLL_DCO 198 +#define CLKID_PCIE_PLL_DCO_DIV2 199 +#define CLKID_PCIE_PLL_OD 200 -#define NR_CLKS 198 +#define NR_CLKS 202 /* include the CLKIDs that have been made part of the DT binding */ #include -- cgit v1.2.3 From ba1ce88efa3af0c4b437c5d6aa3b1cae6bc42855 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 24 Mar 2019 16:11:01 +0100 Subject: dt-bindings: clock: meson8b: export the VPU clock The VPU clock is an input the the "VPU" (Video Processing Unit), which is one of the components of the display controller. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Acked-by: Jerome Brunet Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190324151104.18397-2-martin.blumenstingl@googlemail.com --- include/dt-bindings/clock/meson8b-clkc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index cd11628f50f8..2ac9469a1c27 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -107,5 +107,6 @@ #define CLKID_PERIPH 126 #define CLKID_AXI 128 #define CLKID_L2_DRAM 130 +#define CLKID_VPU 190 #endif /* __MESON8B_CLKC_H */ -- cgit v1.2.3 From 4b0f73055acaced436d5de909b26d001ea7f667c Mon Sep 17 00:00:00 2001 From: Maxime Jourdan Date: Tue, 19 Mar 2019 11:11:38 +0100 Subject: clk: meson-g12a: add video decoder clocks Add the necessary clock parts for: - VDEC_1: used to feed VDEC_1 - VDEC_HEVC: the "back" part of the VDEC_HEVC block - VDEC_HEVCF: the "front" part of the VDEC_HEVC block In previous SoC generations (GXL, GXBB), there was only one VDEC_HEVC clock, which got split in two parts for G12A. Signed-off-by: Maxime Jourdan Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190319101138.27520-2-mjourdan@baylibre.com --- drivers/clk/meson/g12a.c | 163 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 8 ++- 2 files changed, 170 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index a47435f91f2f..86a7c1b5bd42 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -1495,6 +1495,151 @@ static struct clk_regmap g12a_vpu = { }, }; +/* VDEC clocks */ + +static const char * const g12a_vdec_parent_names[] = { + "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7", + "hifi_pll", "gp0_pll", +}; + +static struct clk_regmap g12a_vdec_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VDEC_CLK_CNTL, + .mask = 0x7, + .shift = 9, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "vdec_1_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = g12a_vdec_parent_names, + .num_parents = ARRAY_SIZE(g12a_vdec_parent_names), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_vdec_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VDEC_CLK_CNTL, + .shift = 0, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "vdec_1_div", + .ops = &clk_regmap_divider_ops, + .parent_names = (const char *[]){ "vdec_1_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_vdec_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VDEC_CLK_CNTL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "vdec_1", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "vdec_1_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_vdec_hevcf_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VDEC2_CLK_CNTL, + .mask = 0x7, + .shift = 9, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "vdec_hevcf_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = g12a_vdec_parent_names, + .num_parents = ARRAY_SIZE(g12a_vdec_parent_names), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_vdec_hevcf_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VDEC2_CLK_CNTL, + .shift = 0, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "vdec_hevcf_div", + .ops = &clk_regmap_divider_ops, + .parent_names = (const char *[]){ "vdec_hevcf_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_vdec_hevcf = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VDEC2_CLK_CNTL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "vdec_hevcf", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "vdec_hevcf_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_vdec_hevc_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VDEC2_CLK_CNTL, + .mask = 0x7, + .shift = 25, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "vdec_hevc_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = g12a_vdec_parent_names, + .num_parents = ARRAY_SIZE(g12a_vdec_parent_names), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_vdec_hevc_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VDEC2_CLK_CNTL, + .shift = 16, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "vdec_hevc_div", + .ops = &clk_regmap_divider_ops, + .parent_names = (const char *[]){ "vdec_hevc_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_vdec_hevc = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VDEC2_CLK_CNTL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "vdec_hevc", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "vdec_hevc_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + /* VAPB Clock */ static const char * const g12a_vapb_parent_names[] = { @@ -2615,6 +2760,15 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, + [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, + [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, + [CLKID_VDEC_1] = &g12a_vdec_1.hw, + [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, + [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, + [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, + [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, + [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, + [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -2803,6 +2957,15 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &g12a_cpu_clk_trace, &g12a_pcie_pll_od, &g12a_pcie_pll_dco, + &g12a_vdec_1_sel, + &g12a_vdec_1_div, + &g12a_vdec_1, + &g12a_vdec_hevc_sel, + &g12a_vdec_hevc_div, + &g12a_vdec_hevc, + &g12a_vdec_hevcf_sel, + &g12a_vdec_hevcf_div, + &g12a_vdec_hevcf, }; static const struct meson_eeclkc_data g12a_clkc_data = { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 1393a09730a6..39c41af70804 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -189,8 +189,14 @@ #define CLKID_PCIE_PLL_DCO 198 #define CLKID_PCIE_PLL_DCO_DIV2 199 #define CLKID_PCIE_PLL_OD 200 +#define CLKID_VDEC_1_SEL 202 +#define CLKID_VDEC_1_DIV 203 +#define CLKID_VDEC_HEVC_SEL 205 +#define CLKID_VDEC_HEVC_DIV 206 +#define CLKID_VDEC_HEVCF_SEL 208 +#define CLKID_VDEC_HEVCF_DIV 209 -#define NR_CLKS 202 +#define NR_CLKS 211 /* include the CLKIDs that have been made part of the DT binding */ #include -- cgit v1.2.3 From 77a725ff7a640ab24ff9cf9450e6eae072c49f16 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 24 Mar 2019 16:14:22 +0100 Subject: dt-bindings: clock: meson8b: export the video decoder clocks Export the four video decoder clocks so they can be used by the video decoder driver: - VDEC_1 - VDEC_HCODEC - VDEC_2 - VDEC_HEVC Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet Reviewed-by: Rob Herring Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190324151423.19063-2-martin.blumenstingl@googlemail.com --- include/dt-bindings/clock/meson8b-clkc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 2ac9469a1c27..47556539f0ee 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -108,5 +108,9 @@ #define CLKID_AXI 128 #define CLKID_L2_DRAM 130 #define CLKID_VPU 190 +#define CLKID_VDEC_1 196 +#define CLKID_VDEC_HCODEC 199 +#define CLKID_VDEC_2 202 +#define CLKID_VDEC_HEVC 206 #endif /* __MESON8B_CLKC_H */ -- cgit v1.2.3 From 32cd198a1a505566f8e9d2c925bcfc8b889bbc23 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 24 Mar 2019 16:11:02 +0100 Subject: clk: meson: meson8b: use a separate clock table for Meson8m2 Meson8, Meson8b and Meson8m2 implement a similar clock controller. However, there are a few differences between the three actual IP blocks. One example where Meson8m2 differs from Meson8b is the VPU clock setup: - the VPU input mux can choose between "fclk_div4", "fclk_div3", "fclk_div5" and "fclk_div7" on Meson8b - however, on Meson8m2 it can choose between "fclk_div4", "fclk_div3", "fclk_div5" and "gp_pll" (GP_PLL only exists on Meson8m2, it's the predecessor of the GP0_PLL clock on GXBB/GXL/GXM)) Add a separate clk_hw_onecell_data table for Meson8m2 so these differences can be implemented in our clock controller driver. For now meson8m2_hw_onecell_data is a clone of our existing meson8b_hw_onecell_data. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Acked-by: Jerome Brunet Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190324151104.18397-3-martin.blumenstingl@googlemail.com --- drivers/clk/meson/meson8b.c | 193 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 192 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 576ad42252d0..c9e6ec67d649 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -2157,6 +2157,192 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { .num = CLK_NR_CLKS, }; +static struct clk_hw_onecell_data meson8m2_hw_onecell_data = { + .hws = { + [CLKID_XTAL] = &meson8b_xtal.hw, + [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, + [CLKID_PLL_VID] = &meson8b_vid_pll.hw, + [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, + [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, + [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, + [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, + [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, + [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, + [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, + [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, + [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, + [CLKID_CLK81] = &meson8b_clk81.hw, + [CLKID_DDR] = &meson8b_ddr.hw, + [CLKID_DOS] = &meson8b_dos.hw, + [CLKID_ISA] = &meson8b_isa.hw, + [CLKID_PL301] = &meson8b_pl301.hw, + [CLKID_PERIPHS] = &meson8b_periphs.hw, + [CLKID_SPICC] = &meson8b_spicc.hw, + [CLKID_I2C] = &meson8b_i2c.hw, + [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, + [CLKID_SMART_CARD] = &meson8b_smart_card.hw, + [CLKID_RNG0] = &meson8b_rng0.hw, + [CLKID_UART0] = &meson8b_uart0.hw, + [CLKID_SDHC] = &meson8b_sdhc.hw, + [CLKID_STREAM] = &meson8b_stream.hw, + [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, + [CLKID_SDIO] = &meson8b_sdio.hw, + [CLKID_ABUF] = &meson8b_abuf.hw, + [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, + [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, + [CLKID_SPI] = &meson8b_spi.hw, + [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, + [CLKID_ETH] = &meson8b_eth.hw, + [CLKID_DEMUX] = &meson8b_demux.hw, + [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, + [CLKID_IEC958] = &meson8b_iec958.hw, + [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, + [CLKID_AMCLK] = &meson8b_amclk.hw, + [CLKID_AIFIFO2] = &meson8b_aififo2.hw, + [CLKID_MIXER] = &meson8b_mixer.hw, + [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, + [CLKID_ADC] = &meson8b_adc.hw, + [CLKID_BLKMV] = &meson8b_blkmv.hw, + [CLKID_AIU] = &meson8b_aiu.hw, + [CLKID_UART1] = &meson8b_uart1.hw, + [CLKID_G2D] = &meson8b_g2d.hw, + [CLKID_USB0] = &meson8b_usb0.hw, + [CLKID_USB1] = &meson8b_usb1.hw, + [CLKID_RESET] = &meson8b_reset.hw, + [CLKID_NAND] = &meson8b_nand.hw, + [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, + [CLKID_USB] = &meson8b_usb.hw, + [CLKID_VDIN1] = &meson8b_vdin1.hw, + [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, + [CLKID_EFUSE] = &meson8b_efuse.hw, + [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, + [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, + [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, + [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, + [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, + [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, + [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, + [CLKID_DVIN] = &meson8b_dvin.hw, + [CLKID_UART2] = &meson8b_uart2.hw, + [CLKID_SANA] = &meson8b_sana.hw, + [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, + [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, + [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, + [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, + [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, + [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, + [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, + [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, + [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, + [CLKID_ENC480P] = &meson8b_enc480p.hw, + [CLKID_RNG1] = &meson8b_rng1.hw, + [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, + [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, + [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, + [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, + [CLKID_EDP] = &meson8b_edp.hw, + [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, + [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, + [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, + [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, + [CLKID_MPLL0] = &meson8b_mpll0.hw, + [CLKID_MPLL1] = &meson8b_mpll1.hw, + [CLKID_MPLL2] = &meson8b_mpll2.hw, + [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, + [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, + [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, + [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, + [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, + [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, + [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, + [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, + [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, + [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, + [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, + [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, + [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, + [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, + [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, + [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, + [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, + [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, + [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, + [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, + [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, + [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, + [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, + [CLKID_APB] = &meson8b_apb_clk_gate.hw, + [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, + [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, + [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, + [CLKID_AXI] = &meson8b_axi_clk_gate.hw, + [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, + [CLKID_L2_DRAM] = &meson