From d5c65159f2895379e11ca13f62feabe93278985d Mon Sep 17 00:00:00 2001 From: Kalle Valo Date: Sat, 23 Nov 2019 09:58:40 +0200 Subject: ath11k: driver for Qualcomm IEEE 802.11ax devices ath11k is a new driver for Qualcomm IEEE 802.11ax devices, first supporting only IPQ8074 SoC using the shared memory AHB bus. ath11k uses mac80211 and supports AP, Station and Mesh modes. Even though ath11k has some similar code as with ath10k (especially the WMI layer) it was concluded to be simpler to have a "clean start" for ath11k code base and not try to share the code with ath10k. This makes maintenance easier and avoids major changes in ath10k, which would have significantly increased the risk of regressions in existing setups. Even though the driver is very similar with ath10k but there are major differences as well. The datapath is completely different. ath11k supports multiple MACs, called "soc" in the firmware interface. And there's only one WMI interface to support. Currently ath11k supports only IEEE 802.11ac mode, but patches for 802.11ax are available and they will be submitted after ath11k is accepted to upstream. The firmware images are available from ath11k-firmware repository but they will be also submitted to linux-firmware: https://github.com/kvalo/ath11k-firmware This was tested with firmware version WLAN.HK.2.1.0.1-00629-QCAHKSWPL_SILICONZ-1. The driver has had multiple authors who are listed in alphabetical order below. Signed-off-by: Anilkumar Kolli Signed-off-by: Bhagavathi Perumal S Signed-off-by: Ganesh Sesetti Signed-off-by: Govindaraj Saminathan Signed-off-by: John Crispin Signed-off-by: Julia Lawall Signed-off-by: Kalle Valo Signed-off-by: Karthikeyan Periyasamy Signed-off-by: kbuild test robot Signed-off-by: Maharaja Kennadyrajan Signed-off-by: Manikanta Pubbisetty Signed-off-by: Miles Hu Signed-off-by: Muna Sinada Signed-off-by: Pradeep Kumar Chitrapu Signed-off-by: Rajkumar Manoharan Signed-off-by: Sathishkumar Muruganandam Signed-off-by: Shashidhar Lakkavalli Signed-off-by: Sriram R Signed-off-by: Sven Eckelmann Signed-off-by: Vasanthakumar Thiagarajan Signed-off-by: Venkateswara Naralasetty --- drivers/net/wireless/ath/Kconfig | 1 + drivers/net/wireless/ath/Makefile | 1 + drivers/net/wireless/ath/ath11k/Kconfig | 35 + drivers/net/wireless/ath/ath11k/Makefile | 26 + drivers/net/wireless/ath/ath11k/ahb.c | 1004 ++++ drivers/net/wireless/ath/ath11k/ahb.h | 35 + drivers/net/wireless/ath/ath11k/ce.c | 805 +++ drivers/net/wireless/ath/ath11k/ce.h | 178 + drivers/net/wireless/ath/ath11k/core.c | 772 +++ drivers/net/wireless/ath/ath11k/core.h | 823 +++ drivers/net/wireless/ath/ath11k/debug.c | 1060 ++++ drivers/net/wireless/ath/ath11k/debug.h | 278 + drivers/net/wireless/ath/ath11k/debug_htt_stats.c | 4432 ++++++++++++++++ drivers/net/wireless/ath/ath11k/debug_htt_stats.h | 1620 ++++++ drivers/net/wireless/ath/ath11k/debugfs_sta.c | 538 ++ drivers/net/wireless/ath/ath11k/dp.c | 898 ++++ drivers/net/wireless/ath/ath11k/dp.h | 1526 ++++++ drivers/net/wireless/ath/ath11k/dp_rx.c | 4143 +++++++++++++++ drivers/net/wireless/ath/ath11k/dp_rx.h | 84 + drivers/net/wireless/ath/ath11k/dp_tx.c | 943 ++++ drivers/net/wireless/ath/ath11k/dp_tx.h | 40 + drivers/net/wireless/ath/ath11k/hal.c | 1124 ++++ drivers/net/wireless/ath/ath11k/hal.h | 897 ++++ drivers/net/wireless/ath/ath11k/hal_desc.h | 2469 +++++++++ drivers/net/wireless/ath/ath11k/hal_rx.c | 1221 +++++ drivers/net/wireless/ath/ath11k/hal_rx.h | 352 ++ drivers/net/wireless/ath/ath11k/hal_tx.c | 226 + drivers/net/wireless/ath/ath11k/hal_tx.h | 80 + drivers/net/wireless/ath/ath11k/htc.c | 773 +++ drivers/net/wireless/ath/ath11k/htc.h | 313 ++ drivers/net/wireless/ath/ath11k/hw.h | 127 + drivers/net/wireless/ath/ath11k/mac.c | 5427 ++++++++++++++++++++ drivers/net/wireless/ath/ath11k/mac.h | 145 + drivers/net/wireless/ath/ath11k/peer.c | 236 + drivers/net/wireless/ath/ath11k/peer.h | 35 + drivers/net/wireless/ath/ath11k/qmi.c | 2435 +++++++++ drivers/net/wireless/ath/ath11k/qmi.h | 445 ++ drivers/net/wireless/ath/ath11k/reg.c | 701 +++ drivers/net/wireless/ath/ath11k/reg.h | 35 + drivers/net/wireless/ath/ath11k/rx_desc.h | 1212 +++++ drivers/net/wireless/ath/ath11k/testmode.c | 199 + drivers/net/wireless/ath/ath11k/testmode.h | 29 + drivers/net/wireless/ath/ath11k/testmode_i.h | 50 + drivers/net/wireless/ath/ath11k/trace.c | 9 + drivers/net/wireless/ath/ath11k/trace.h | 110 + drivers/net/wireless/ath/ath11k/wmi.c | 5632 +++++++++++++++++++++ drivers/net/wireless/ath/ath11k/wmi.h | 4664 +++++++++++++++++ 47 files changed, 48188 insertions(+) create mode 100644 drivers/net/wireless/ath/ath11k/Kconfig create mode 100644 drivers/net/wireless/ath/ath11k/Makefile create mode 100644 drivers/net/wireless/ath/ath11k/ahb.c create mode 100644 drivers/net/wireless/ath/ath11k/ahb.h create mode 100644 drivers/net/wireless/ath/ath11k/ce.c create mode 100644 drivers/net/wireless/ath/ath11k/ce.h create mode 100644 drivers/net/wireless/ath/ath11k/core.c create mode 100644 drivers/net/wireless/ath/ath11k/core.h create mode 100644 drivers/net/wireless/ath/ath11k/debug.c create mode 100644 drivers/net/wireless/ath/ath11k/debug.h create mode 100644 drivers/net/wireless/ath/ath11k/debug_htt_stats.c create mode 100644 drivers/net/wireless/ath/ath11k/debug_htt_stats.h create mode 100644 drivers/net/wireless/ath/ath11k/debugfs_sta.c create mode 100644 drivers/net/wireless/ath/ath11k/dp.c create mode 100644 drivers/net/wireless/ath/ath11k/dp.h create mode 100644 drivers/net/wireless/ath/ath11k/dp_rx.c create mode 100644 drivers/net/wireless/ath/ath11k/dp_rx.h create mode 100644 drivers/net/wireless/ath/ath11k/dp_tx.c create mode 100644 drivers/net/wireless/ath/ath11k/dp_tx.h create mode 100644 drivers/net/wireless/ath/ath11k/hal.c create mode 100644 drivers/net/wireless/ath/ath11k/hal.h create mode 100644 drivers/net/wireless/ath/ath11k/hal_desc.h create mode 100644 drivers/net/wireless/ath/ath11k/hal_rx.c create mode 100644 drivers/net/wireless/ath/ath11k/hal_rx.h create mode 100644 drivers/net/wireless/ath/ath11k/hal_tx.c create mode 100644 drivers/net/wireless/ath/ath11k/hal_tx.h create mode 100644 drivers/net/wireless/ath/ath11k/htc.c create mode 100644 drivers/net/wireless/ath/ath11k/htc.h create mode 100644 drivers/net/wireless/ath/ath11k/hw.h create mode 100644 drivers/net/wireless/ath/ath11k/mac.c create mode 100644 drivers/net/wireless/ath/ath11k/mac.h create mode 100644 drivers/net/wireless/ath/ath11k/peer.c create mode 100644 drivers/net/wireless/ath/ath11k/peer.h create mode 100644 drivers/net/wireless/ath/ath11k/qmi.c create mode 100644 drivers/net/wireless/ath/ath11k/qmi.h create mode 100644 drivers/net/wireless/ath/ath11k/reg.c create mode 100644 drivers/net/wireless/ath/ath11k/reg.h create mode 100644 drivers/net/wireless/ath/ath11k/rx_desc.h create mode 100644 drivers/net/wireless/ath/ath11k/testmode.c create mode 100644 drivers/net/wireless/ath/ath11k/testmode.h create mode 100644 drivers/net/wireless/ath/ath11k/testmode_i.h create mode 100644 drivers/net/wireless/ath/ath11k/trace.c create mode 100644 drivers/net/wireless/ath/ath11k/trace.h create mode 100644 drivers/net/wireless/ath/ath11k/wmi.c create mode 100644 drivers/net/wireless/ath/ath11k/wmi.h diff --git a/drivers/net/wireless/ath/Kconfig b/drivers/net/wireless/ath/Kconfig index 56616d988c96..d6df17d312cd 100644 --- a/drivers/net/wireless/ath/Kconfig +++ b/drivers/net/wireless/ath/Kconfig @@ -62,5 +62,6 @@ source "drivers/net/wireless/ath/ar5523/Kconfig" source "drivers/net/wireless/ath/wil6210/Kconfig" source "drivers/net/wireless/ath/ath10k/Kconfig" source "drivers/net/wireless/ath/wcn36xx/Kconfig" +source "drivers/net/wireless/ath/ath11k/Kconfig" endif diff --git a/drivers/net/wireless/ath/Makefile b/drivers/net/wireless/ath/Makefile index ee2b2431e5a3..8e4ae9de5ae4 100644 --- a/drivers/net/wireless/ath/Makefile +++ b/drivers/net/wireless/ath/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_AR5523) += ar5523/ obj-$(CONFIG_WIL6210) += wil6210/ obj-$(CONFIG_ATH10K) += ath10k/ obj-$(CONFIG_WCN36XX) += wcn36xx/ +obj-$(CONFIG_ATH11K) += ath11k/ obj-$(CONFIG_ATH_COMMON) += ath.o diff --git a/drivers/net/wireless/ath/ath11k/Kconfig b/drivers/net/wireless/ath/ath11k/Kconfig new file mode 100644 index 000000000000..cfab4fb86aef --- /dev/null +++ b/drivers/net/wireless/ath/ath11k/Kconfig @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause-Clear +config ATH11K + tristate "Qualcomm Technologies 802.11ax chipset support" + depends on MAC80211 && HAS_DMA + depends on REMOTEPROC + depends on ARCH_QCOM || COMPILE_TEST + select ATH_COMMON + select QCOM_QMI_HELPERS + ---help--- + This module adds support for Qualcomm Technologies 802.11ax family of + chipsets. + + If you choose to build a module, it'll be called ath11k. + +config ATH11K_DEBUG + bool "QCA ath11k debugging" + depends on ATH11K + ---help--- + Enables debug support + + If unsure, say Y to make it easier to debug problems. + +config ATH11K_DEBUGFS + bool "QCA ath11k debugfs support" + depends on ATH11K && DEBUG_FS + ---help--- + Enable ath11k debugfs support + + If unsure, say Y to make it easier to debug problems. + +config ATH11K_TRACING + bool "ath11k tracing support" + depends on ATH11K && EVENT_TRACING + ---help--- + Select this to use ath11k tracing infrastructure. diff --git a/drivers/net/wireless/ath/ath11k/Makefile b/drivers/net/wireless/ath/ath11k/Makefile new file mode 100644 index 000000000000..a91d75c1cfeb --- /dev/null +++ b/drivers/net/wireless/ath/ath11k/Makefile @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: BSD-3-Clause-Clear +obj-$(CONFIG_ATH11K) += ath11k.o +ath11k-y += core.o \ + hal.o \ + hal_tx.o \ + hal_rx.o \ + ahb.o \ + wmi.o \ + mac.o \ + reg.o \ + htc.o \ + qmi.o \ + dp.o \ + dp_tx.o \ + dp_rx.o \ + debug.o \ + ce.o \ + peer.o + +ath11k-$(CONFIG_ATH11K_DEBUGFS) += debug_htt_stats.o +ath11k-$(CONFIG_MAC80211_DEBUGFS) += debugfs_sta.o +ath11k-$(CONFIG_NL80211_TESTMODE) += testmode.o +ath11k-$(CONFIG_ATH11K_TRACING) += trace.o + +# for tracing framework to find trace.h +CFLAGS_trace.o := -I$(src) diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c new file mode 100644 index 000000000000..f80173b8afc6 --- /dev/null +++ b/drivers/net/wireless/ath/ath11k/ahb.c @@ -0,0 +1,1004 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "ahb.h" +#include "debug.h" +#include + +static const struct of_device_id ath11k_ahb_of_match[] = { + /* TODO: Should we change the compatible string to something similar + * to one that ath10k uses? + */ + { .compatible = "qcom,ipq8074-wifi", + .data = (void *)ATH11K_HW_IPQ8074, + }, + { } +}; + +MODULE_DEVICE_TABLE(of, ath11k_ahb_of_match); + +/* Target firmware's Copy Engine configuration. */ +static const struct ce_pipe_config target_ce_config_wlan[] = { + /* CE0: host->target HTC control and raw streams */ + { + .pipenum = __cpu_to_le32(0), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + + /* CE1: target->host HTT + HTC control */ + { + .pipenum = __cpu_to_le32(1), + .pipedir = __cpu_to_le32(PIPEDIR_IN), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + + /* CE2: target->host WMI */ + { + .pipenum = __cpu_to_le32(2), + .pipedir = __cpu_to_le32(PIPEDIR_IN), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + + /* CE3: host->target WMI */ + { + .pipenum = __cpu_to_le32(3), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + + /* CE4: host->target HTT */ + { + .pipenum = __cpu_to_le32(4), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), + .nentries = __cpu_to_le32(256), + .nbytes_max = __cpu_to_le32(256), + .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), + .reserved = __cpu_to_le32(0), + }, + + /* CE5: target->host Pktlog */ + { + .pipenum = __cpu_to_le32(5), + .pipedir = __cpu_to_le32(PIPEDIR_IN), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(0), + .reserved = __cpu_to_le32(0), + }, + + /* CE6: Reserved for target autonomous hif_memcpy */ + { + .pipenum = __cpu_to_le32(6), + .pipedir = __cpu_to_le32(PIPEDIR_INOUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(65535), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + + /* CE7 used only by Host */ + { + .pipenum = __cpu_to_le32(7), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + + /* CE8 target->host used only by IPA */ + { + .pipenum = __cpu_to_le32(8), + .pipedir = __cpu_to_le32(PIPEDIR_INOUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(65535), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + + /* CE9 host->target HTT */ + { + .pipenum = __cpu_to_le32(9), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + + /* CE10 target->host HTT */ + { + .pipenum = __cpu_to_le32(10), + .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), + .nentries = __cpu_to_le32(0), + .nbytes_max = __cpu_to_le32(0), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + + /* CE11 Not used */ + { + .pipenum = __cpu_to_le32(0), + .pipedir = __cpu_to_le32(0), + .nentries = __cpu_to_le32(0), + .nbytes_max = __cpu_to_le32(0), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, +}; + +/* Map from service/endpoint to Copy Engine. + * This table is derived from the CE_PCI TABLE, above. + * It is passed to the Target at startup for use by firmware. + */ +static const struct service_to_pipe target_service_to_ce_map_wlan[] = { + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(3), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(2), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(3), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(2), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(3), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(2), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(3), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(2), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(3), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(2), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(7), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(2), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(9), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(2), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(0), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(1), + }, + { /* not used */ + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(0), + }, + { /* not used */ + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(1), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ + .pipenum = __cpu_to_le32(4), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(1), + }, + { + .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), + .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ + .pipenum = __cpu_to_le32(5), + }, + + /* (Additions here) */ + + { /* terminator entry */ } +}; + +#define ATH11K_IRQ_CE0_OFFSET 4 + +static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { + "misc-pulse1", + "misc-latch", + "sw-exception", + "watchdog", + "ce0", + "ce1", + "ce2", + "ce3", + "ce4", + "ce5", + "ce6", + "ce7", + "ce8", + "ce9", + "ce10", + "ce11", + "host2wbm-desc-feed", + "host2reo-re-injection", + "host2reo-command", + "host2rxdma-monitor-ring3", + "host2rxdma-monitor-ring2", + "host2rxdma-monitor-ring1", + "reo2ost-exception", + "wbm2host-rx-release", + "reo2host-status", + "reo2host-destination-ring4", + "reo2host-destination-ring3", + "reo2host-destination-ring2", + "reo2host-destination-ring1", + "rxdma2host-monitor-destination-mac3", + "rxdma2host-monitor-destination-mac2", + "rxdma2host-monitor-destination-mac1", + "ppdu-end-interrupts-mac3", + "ppdu-end-interrupts-mac2", + "ppdu-end-interrupts-mac1", + "rxdma2host-monitor-status-ring-mac3", + "rxdma2host-monitor-status-ring-mac2", + "rxdma2host-monitor-status-ring-mac1", + "host2rxdma-host-buf-ring-mac3", + "host2rxdma-host-buf-ring-mac2", + "host2rxdma-host-buf-ring-mac1", + "rxdma2host-destination-ring-mac3", + "rxdma2host-destination-ring-mac2", + "rxdma2host-destination-ring-mac1", + "host2tcl-input-ring4", + "host2tcl-input-ring3", + "host2tcl-input-ring2", + "host2tcl-input-ring1", + "wbm2host-tx-completions-ring3", + "wbm2host-tx-completions-ring2", + "wbm2host-tx-completions-ring1", + "tcl2host-status-ring", +}; + +#define ATH11K_TX_RING_MASK_0 0x1 +#define ATH11K_TX_RING_MASK_1 0x2 +#define ATH11K_TX_RING_MASK_2 0x4 + +#define ATH11K_RX_RING_MASK_0 0x1 +#define ATH11K_RX_RING_MASK_1 0x2 +#define ATH11K_RX_RING_MASK_2 0x4 +#define ATH11K_RX_RING_MASK_3 0x8 + +#define ATH11K_RX_ERR_RING_MASK_0 0x1 + +#define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 + +#define ATH11K_REO_STATUS_RING_MASK_0 0x1 + +#define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 +#define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 +#define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 + +#define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 +#define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 +#define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 + +#define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 +#define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 +#define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 + +const u8 ath11k_tx_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX] = { + ATH11K_TX_RING_MASK_0, + ATH11K_TX_RING_MASK_1, + ATH11K_TX_RING_MASK_2, +}; + +const u8 rx_mon_status_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX] = { + 0, 0, 0, 0, + ATH11K_RX_MON_STATUS_RING_MASK_0, + ATH11K_RX_MON_STATUS_RING_MASK_1, + ATH11K_RX_MON_STATUS_RING_MASK_2, +}; + +const u8 ath11k_rx_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX] = { + 0, 0, 0, 0, 0, 0, 0, + ATH11K_RX_RING_MASK_0, + ATH11K_RX_RING_MASK_1, + ATH11K_RX_RING_MASK_2, + ATH11K_RX_RING_MASK_3, +}; + +const u8 ath11k_rx_err_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX] = { + ATH11K_RX_ERR_RING_MASK_0, +}; + +const u8 ath11k_rx_wbm_rel_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX] = { + ATH11K_RX_WBM_REL_RING_MASK_0, +}; + +const u8 ath11k_reo_status_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX] = { + ATH11K_REO_STATUS_RING_MASK_0, +}; + +const u8 ath11k_rxdma2host_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX] = { + ATH11K_RXDMA2HOST_RING_MASK_0, + ATH11K_RXDMA2HOST_RING_MASK_1, + ATH11K_RXDMA2HOST_RING_MASK_2, +}; + +const u8 ath11k_host2rxdma_ring_mask[ATH11K_EXT_IRQ_GRP_NUM_MAX] = { + ATH11K_HOST2RXDMA_RING_MASK_0, + ATH11K_HOST2RXDMA_RING_MASK_1, + ATH11K_HOST2RXDMA_RING_MASK_2, +}; + +/* enum ext_irq_num - irq numbers that can be used by external modules + * like datapath + */ +enum ext_irq_num { + host2wbm_desc_feed = 16, + host2reo_re_injection, + host2reo_command, + host2rxdma_monitor_ring3, + host2rxdma_monitor_ring2, + host2rxdma_monitor_ring1, + reo2host_exception, + wbm2host_rx_release, + reo2host_status, + reo2host_destination_ring4, + reo2host_destination_ring3, + reo2host_destination_ring2, + reo2host_destination_ring1, + rxdma2host_monitor_destination_mac3, + rxdma2host_monitor_destination_mac2, + rxdma2host_monitor_destination_mac1, + ppdu_end_interrupts_mac3, + ppdu_end_interrupts_mac2, + ppdu_end_interrupts_mac1, + rxdma2host_monitor_status_ring_mac3, + rxdma2host_monitor_status_ring_mac2, + rxdma2host_monitor_status_ring_mac1, + host2rxdma_host_buf_ring_mac3, + host2rxdma_host_buf_ring_mac2, + host2rxdma_host_buf_ring_mac1, + rxdma2host_destination_ring_mac3, + rxdma2host_destination_ring_mac2, + rxdma2host_destination_ring_mac1, + host2tcl_input_ring4, + host2tcl_input_ring3, + host2tcl_input_ring2, + host2tcl_input_ring1, + wbm2host_tx_completions_ring3, + wbm2host_tx_completions_ring2, + wbm2host_tx_completions_ring1, + tcl2host_status_ring, +}; + +static void ath11k_ahb_kill_tasklets(struct ath11k_base *ab) +{ + int i; + + for (i = 0; i < CE_COUNT; i++) { + struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; + + if (ath11k_ce_get_attr_flags(i) & CE_ATTR_DIS_INTR) + continue; + + tasklet_kill(&ce_pipe->intr_tq); + } +} + +static void ath11k_ahb_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp) +{ + int i; + + for (i = 0; i < irq_grp->num_irq; i++) + disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); +} + +static void __ath11k_ahb_ext_irq_disable(struct ath11k_base *ab) +{ + struct sk_buff *skb; + int i; + + for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { + struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + ath11k_ahb_ext_grp_disable(irq_grp); + + napi_synchronize(&irq_grp->napi); + napi_disable(&irq_grp->napi); + + while ((skb = __skb_dequeue(&irq_grp->pending_q))) + dev_kfree_skb_any(skb); + } +} + +static void ath11k_ahb_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp) +{ + int i; + + for (i = 0; i < irq_grp->num_irq; i++) + enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); +} + +static void ath11k_ahb_setbit32(struct ath11k_base *ab, u8 bit, u32 offset) +{ + u32 val; + + val = ath11k_ahb_read32(ab, offset); + ath11k_ahb_write32(ab, offset, val | BIT(bit)); +} + +static void ath11k_ahb_clearbit32(struct ath11k_base *ab, u8 bit, u32 offset) +{ + u32 val; + + val = ath11k_ahb_read32(ab, offset); + ath11k_ahb_write32(ab, offset, val & ~BIT(bit)); +} + +static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) +{ + const struct ce_pipe_config *ce_config; + + ce_config = &target_ce_config_wlan[ce_id]; + if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT) + ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_ADDRESS); + + if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) { + ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS); + ath11k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT, + CE_HOST_IE_3_ADDRESS); + } +} + +static void ath11k_ahb_ce_irq_disable(struct ath11k_base *ab, u16 ce_id) +{ + const struct ce_pipe_config *ce_config; + + ce_config = &target_ce_config_wlan[ce_id]; + if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT) + ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_ADDRESS); + + if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) { + ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS); + ath11k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT, + CE_HOST_IE_3_ADDRESS); + } +} + +static void ath11k_ahb_sync_ce_irqs(struct ath11k_base *ab) +{ + int i; + int irq_idx; + + for (i = 0; i < CE_COUNT; i++) { + if (ath11k_ce_get_attr_flags(i) & CE_ATTR_DIS_INTR) + continue; + + irq_idx = ATH11K_IRQ_CE0_OFFSET + i; + synchronize_irq(ab->irq_num[irq_idx]); + } +} + +static void ath11k_ahb_sync_ext_irqs(struct ath11k_base *ab) +{ + int i, j; + int irq_idx; + + for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { + struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + for (j = 0; j < irq_grp->num_irq; j++) { + irq_idx = irq_grp->irqs[j]; + synchronize_irq(ab->irq_num[irq_idx]); + } + } +} + +static void ath11k_ahb_ce_irqs_enable(struct ath11k_base *ab) +{ + int i; + + for (i = 0; i < CE_COUNT; i++) { + if (ath11k_ce_get_attr_flags(i) & CE_ATTR_DIS_INTR) + continue; + ath11k_ahb_ce_irq_enable(ab, i); + } +} + +static void ath11k_ahb_ce_irqs_disable(struct ath11k_base *ab) +{ + int i; + + for (i = 0; i < CE_COUNT; i++) { + if (ath11k_ce_get_attr_flags(i) & CE_ATTR_DIS_INTR) + continue; + ath11k_ahb_ce_irq_disable(ab, i); + } +} + +int ath11k_ahb_start(struct ath11k_base *ab) +{ + ath11k_ahb_ce_irqs_enable(ab); + ath11k_ce_rx_post_buf(ab); + + return 0; +} + +void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab) +{ + int i; + + for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { + struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + napi_enable(&irq_grp->napi); + ath11k_ahb_ext_grp_enable(irq_grp); + } +} + +void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab) +{ + __ath11k_ahb_ext_irq_disable(ab); + ath11k_ahb_sync_ext_irqs(ab); +} + +void ath11k_ahb_stop(struct ath11k_base *ab) +{ + if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) + ath11k_ahb_ce_irqs_disable(ab); + ath11k_ahb_sync_ce_irqs(ab); + ath11k_ahb_kill_tasklets(ab); + del_timer_sync(&ab->rx_replenish_retry); + ath11k_ce_cleanup_pipes(ab); +} + +int ath11k_ahb_power_up(struct ath11k_base *ab) +{ + int ret; + + ret = rproc_boot(ab->tgt_rproc); + if (ret) + ath11k_err(ab, "failed to boot the remote processor Q6\n"); + + return ret; +} + +void ath11k_ahb_power_down(struct ath11k_base *ab) +{ + rproc_shutdown(ab->tgt_rproc); +} + +static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab) +{ + struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; + + cfg->tgt_ce = (u8 *)target_ce_config_wlan; + cfg->tgt_ce_len = sizeof(target_ce_config_wlan); + + cfg->svc_to_ce_map = (u8 *)target_service_to_ce_map_wlan; + cfg->svc_to_ce_map_len = sizeof(target_service_to_ce_map_wlan); +} + +static void ath11k_ahb_free_ext_irq(struct ath11k_base *ab) +{ + int i, j; + + for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { + struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + for (j = 0; j < irq_grp->num_irq; j++) + free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); + } +} + +static void ath11k_ahb_free_irq(struct ath11k_base *ab) +{ + int irq_idx; + int i; + + for (i = 0; i < CE_COUNT; i++) { + if (ath11k_ce_get_attr_flags(i) & CE_ATTR_DIS_INTR) + continue; + irq_idx = ATH11K_IRQ_CE0_OFFSET + i; + free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); + } + + ath11k_ahb_free_ext_irq(ab); +} + +static void ath11k_ahb_ce_tasklet(unsigned long data) +{ + struct ath11k_ce_pipe *ce_pipe = (struct ath11k_ce_pipe *)data; + + ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); + + ath11k_ahb_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); +} + +static irqreturn_t ath11k_ahb_ce_interrupt_handler(int irq, void *arg) +{ + struct ath11k_ce_pipe *ce_pipe = arg; + + ath11k_ahb_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); + + tasklet_schedule(&ce_pipe->intr_tq); + + return IRQ_HANDLED; +} + +static int ath11k_ahb_ext_grp_napi_poll(struct napi_struct *napi, int budget) +{ + struct ath11k_ext_irq_grp *irq_grp = container_of(napi, + struct ath11k_ext_irq_grp, + napi); + struct ath11k_base *ab = irq_grp->ab; + int work_done; + + work_done = ath11k_dp_service_srng(ab, irq_grp, budget); + if (work_done < budget) { + napi_complete_done(napi, work_done); + ath11k_ahb_ext_grp_enable(irq_grp); + } + + if (work_done > budget) + work_done = budget; + + return work_done; +} + +static irqreturn_t ath11k_ahb_ext_interrupt_handler(int irq, void *arg) +{ + struct ath11k_ext_irq_grp *irq_grp = arg; + + ath11k_ahb_ext_grp_disable(irq_grp); + + napi_schedule(&irq_grp->napi); + + return IRQ_HANDLED; +} + +static int ath11k_ahb_ext_irq_config(struct ath11k_base *ab) +{ + int i, j; + int irq; + int ret; + + for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { + struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + u32 num_irq = 0; + + irq_grp->ab = ab; + irq_grp->grp_id = i; + init_dummy_netdev(&irq_grp->napi_ndev); + netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, + ath11k_ahb_ext_grp_napi_poll, NAPI_POLL_WEIGHT); + __skb_queue_head_init(&irq_grp->pending_q); + + for (j = 0; j < ATH11K_EXT_IRQ_NUM_MAX; j++) { + if (ath11k_tx_ring_mask[i] & BIT(j)) { + irq_grp->irqs[num_irq++] = + wbm2host_tx_completions_ring1 - j; + } + + if (ath11k_rx_ring_mask[i] & BIT(j)) { + irq_grp->irqs[num_irq++] = + reo2host_destination_ring1 - j; + } + + if (ath11k_rx_err_ring_mask[i] & BIT(j)) + irq_grp->irqs[num_irq++] = reo2host_exception; + + if (ath11k_rx_wbm_rel_ring_mask[i] & BIT(j)) + irq_grp->irqs[num_irq++] = wbm2host_rx_release; + + if (ath11k_reo_status_ring_mask[i] & BIT(j)) + irq_grp->irqs[num_irq++] = reo2host_status; + + if (j < MAX_RADIOS) { + if (ath11k_rxdma2host_ring_mask[i] & BIT(j)) { + irq_grp->irqs[num_irq++] = + rxdma2host_destination_ring_mac1 + - ath11k_core_get_hw_mac_id(ab, j); + } + + if (ath11k_host2rxdma_ring_mask[i] & BIT(j)) { + irq_grp->irqs[num_irq++] = + host2rxdma_host_buf_ring_mac1 + - ath11k_core_get_hw_mac_id(ab, j); + } + + if (rx_mon_status_ring_mask[i] & BIT(j)) { + irq_grp->irqs[num_irq++] = + ppdu_end_interrupts_mac1 - + ath11k_core_get_hw_mac_id(ab, j); + irq_grp->irqs[num_irq++] = + rxdma2host_monitor_status_ring_mac1 - + ath11k_core_get_hw_mac_id(ab, j); + } + } + } + irq_grp->num_irq = num_irq; + + for (j = 0; j < irq_grp->num_irq; j++) { + int irq_idx = irq_grp->irqs[j]; + + irq = platform_get_irq_byname(ab->pdev, + irq_name[irq_idx]); + ab->irq_num[irq_idx] = irq; + irq_set_status_flags(irq, IRQ_NOAUTOEN); + ret = request_irq(irq, ath11k_ahb_ext_interrupt_handler, + IRQF_TRIGGER_RISING, + irq_name[irq_idx], irq_grp); + if (ret) { + ath11k_err(ab, "failed request_irq for %d\n", + irq); + } + } + } + + return 0; +} + +static int ath11k_ahb_config_irq(struct ath11k_base *ab) +{ + int irq, irq_idx, i; + int ret; + + /* Configure CE irqs */ + for (i = 0; i < CE_COUNT; i++) { + struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; + + if (ath11k_ce_get_attr_flags(i) & CE_ATTR_DIS_INTR) + continue; + + irq_idx = ATH11K_IRQ_CE0_OFFSET + i; + + tasklet_init(&ce_pipe->intr_tq, ath11k_ahb_ce_tasklet, + (unsigned long)ce_pipe); + irq = platform_get_irq_byname(ab->pdev, irq_name[irq_idx]); + ret = request_irq(irq, ath11k_ahb_ce_interrupt_handler, + IRQF_TRIGGER_RISING, irq_name[irq_idx], + ce_pipe); + if (ret) + return ret; + + ab->irq_num[irq_idx] = irq; + } + + /* Configure external interrupts */ + ret = ath11k_ahb_ext_irq_config(ab); + + return ret; +} + +int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, + u8 *ul_pipe, u8 *dl_pipe) +{ + const struct service_to_pipe *entry; + bool ul_set = false, dl_set = false; + int i; + + for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { + entry = &target_service_to_ce_map_wlan[i]; + + if (__le32_to_cpu(entry->service_id) != service_id) + continue; + + switch (__le32_to_cpu(entry->pipedir)) { + case PIPEDIR_NONE: + break; + case PIPEDIR_IN: + WARN_ON(dl_set); + *dl_pipe = __le32_to_cpu(entry->pipenum); + dl_set = true; + break; + case PIPEDIR_OUT: + WARN_ON(ul_set); + *ul_pipe = __le32_to_cpu(entry->pipenum); + ul_set = true; + break; + case PIPEDIR_INOUT: + WARN_ON(dl_set); + WARN_ON(ul_set); + *dl_pipe = __le32_to_cpu(entry->pipenum); + *ul_pipe = __le32_to_cpu(entry->pipenum); + dl_set = true; + ul_set = true; + break; + } + } + + if (WARN_ON(!ul_set || !dl_set)) + return -ENOENT; + + return 0; +} + +static int ath11k_ahb_probe(struct platform_device *pdev) +{ + struct ath11k_base *ab; + const struct of_device_id *of_id; + struct resource *mem_res; + void __iomem *mem; + int ret; + + of_id = of_match_device(ath11k_ahb_of_match, &pdev->dev); + if (!of_id) { + dev_err(&pdev->dev, "failed to find matching device tree id\n"); + return -EINVAL; + } + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem_res) { + dev_err(&pdev->dev, "failed to get IO memory resource\n"); + return -ENXIO; + } + + mem = devm_ioremap_resource(&pdev->dev, mem_res); + if (IS_ERR(mem)) { + dev_err(&pdev->dev, "ioremap error\n"); + return PTR_ERR(mem); + } + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(&pdev->dev, "failed to set 32-bit consistent dma\n"); + return ret; + } + + ab = ath11k_core_alloc(&pdev->dev); + if (!ab) { + dev_err(&pdev->dev, "failed to allocate ath11k base\n"); + return -ENOMEM; + } + + ab->pdev = pdev; + ab->hw_rev = (enum ath11k_hw_rev)of_id->data; + ab->mem = mem; + ab->mem_len = resource_size(mem_res); + platform_set_drvdata(pdev, ab); + + ret = ath11k_hal_srng_init(ab); + if (ret) + goto err_core_free; + + ret = ath11k_ce_alloc_pipes(ab); + if (ret) { + ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); + goto err_hal_srng_deinit; + } + + ath11k_ahb_init_qmi_ce_config(ab); + + ret = ath11k_ahb_config_irq(ab); + if (ret) { + ath11k_err(ab, "failed to configure irq: %d\n", ret); + goto err_ce_free; + } + + ret = ath11k_core_init(ab); + if (ret) { + ath11k_err(ab, "failed to init core: %d\n", ret); + goto err_ce_free; + } + + return 0; + +err_ce_free: + ath11k_ce_free_pipes(ab); + +err_hal_srng_deinit: + ath11k_hal_srng_deinit(ab); + +err_core_free: + ath11k_core_free(ab); + platform_set_drvdata(pdev, NULL); + + return ret; +} + +static int ath11k_ahb_remove(struct platform_device *pdev) +{ + struct ath11k_base *ab = platform_get_drvdata(pdev); + + reinit_completion(&ab->driver_recovery); + + if (test_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags)) + wait_for_completion_timeout(&ab->driver_recovery, + ATH11K_AHB_RECOVERY_TIMEOUT); + + set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); + cancel_work_sync(&ab->restart_work); + + ath11k_core_deinit(ab); + ath11k_ahb_free_irq(ab); + + ath11k_hal_srng_deinit(ab); + ath11k_ce_free_pipes(ab); + ath11k_core_free(ab); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver ath11k_ahb_driver = { + .driver = { + .name = "ath11k", + .of_match_table = ath11k_ahb_of_match, + }, + .probe = ath11k_ahb_probe, + .remove = ath11k_ahb_remove, +}; + +int ath11k_ahb_init(void) +{ + return platform_driver_register(&ath11k_ahb_driver); +} + +void ath11k_ahb_exit(void) +{ + platform_driver_unregister(&ath11k_ahb_driver); +} diff --git a/drivers/net/wireless/ath/ath11k/ahb.h b/drivers/net/wireless/ath/ath11k/ahb.h new file mode 100644 index 000000000000..93f46dfe22df --- /dev/null +++ b/drivers/net/wireless/ath/ath11k/ahb.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + */ +#ifndef ATH11K_AHB_H +#define ATH11K_AHB_H + +#include "core.h" + +#define ATH11K_AHB_RECOVERY_TIMEOUT (3 * HZ) +struct ath11k_base; + +static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset) +{ + return ioread32(ab->mem + offset); +} + +static inline void ath11k_ahb_write32(struct ath11k_base *ab, u32 offset, u32 value) +{ + iowrite32(value, ab->mem + offset); +} + +void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab); +void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab); +int ath11k_ahb_start(struct ath11k_base *ab); +void ath11k_ahb_stop(struct ath11k_base *ab); +int ath11k_ahb_power_up(struct ath11k_base *ab); +void ath11k_ahb_power_down(struct ath11k_base *ab); +int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, + u8 *ul_pipe, u8 *dl_pipe); + +int ath11k_ahb_init(void); +void ath11k_ahb_exit(void); + +#endif diff --git a/drivers/net/wireless/ath/ath11k/ce.c b/drivers/net/wireless/ath/ath11k/ce.c new file mode 100644 index 000000000000..a6572b414303 --- /dev/null +++ b/drivers/net/wireless/ath/ath11k/ce.c @@ -0,0 +1,805 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + */ + +#include "dp_rx.h" +#include "debug.h" + +static const struct ce_attr host_ce_config_wlan[] = { + /* CE0: host->target HTC control and raw streams */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 16, + .src_sz_max = 2048, + .dest_nentries = 0, + }, + + /* CE1: target->host HTT + HTC control */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 2048, + .dest_nentries = 512, + .recv_cb = ath11k_htc_rx_completion_handler, + }, + + /* CE2: target->host WMI */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 2048, + .dest_nentries = 512, + .recv_cb = ath11k_htc_rx_completion_handler, + }, + + /* CE3: host->target WMI (mac0) */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 32, + .src_sz_max = 2048, + .dest_nentries = 0, + }, + + /* CE4: host->target HTT */ + { + .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, + .src_nentries = 2048, + .src_sz_max = 256, + .dest_nentries = 0, + }, + + /* CE5: target->host pktlog */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 2048, + .dest_nentries = 512, + .recv_cb = ath11k_dp_htt_htc_t2h_msg_handler, + }, + + /* CE6: target autonomous hif_memcpy */ + { + .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, + .src_nentries = 0, + .src_sz_max = 0, + .dest_nentries = 0, + }, + + /* CE7: host->target WMI (mac1) */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 32, + .src_sz_max = 2048, + .dest_nentries = 0, + }, + + /* CE8: target autonomous hif_memcpy */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 0, + .dest_nentries = 0, + }, + + /* CE9: host->target WMI (mac2) */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 32, + .src_sz_max = 2048, + .dest_nentries = 0, + }, + + /* CE10: target->host HTT */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 2048, + .dest_nentries = 512, + .recv_cb = ath11k_htc_rx_completion_handler, + }, + + /* CE11: Not used */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 0, + .dest_nentries = 0, + }, +}; + +static int ath11k_ce_rx_buf_enqueue_pipe(struct ath11k_ce_pipe *pipe, + struct sk_buff *skb, dma_addr_t paddr) +{ + struct ath11k_base *ab = pipe->ab; + struct ath11k_ce_ring *ring = pipe->dest_ring; + struct hal_srng *srng; + unsigned int write_index; + unsigned int nentries_mask = ring->nentries_mask; + u32 *desc; + int ret; + + lockdep_assert_held(&ab->ce.ce_lock); + + write_index = ring->write_index; + + srng = &ab->hal.srng_list[ring->hal_ring_id]; + + spin_lock_bh(&srng->lock); + + ath11k_hal_srng_access_begin(ab, srng); + + if (unlikely(ath11k_hal_srng_src_num_free(ab, srng, false) < 1)) { + ret = -ENOSPC; + goto exit; + } + + desc = ath11k_hal_srng_src_get_next_entry(ab, srng); + if (!desc) { + ret = -ENOSPC; + goto exit; + } + + ath11k_hal_ce_dst_set_desc(desc, paddr); + + ring->skb[write_index] = skb; + write_index = CE_RING_IDX_INCR(nentries_mask, write_index); + ring->write_index = write_index; + + pipe->rx_buf_needed--; + + ret = 0; +exit: + ath11k_hal_srng_access_end(ab, srng); + + spin_unlock_bh(&srng->lock); + + return ret; +} + +static int ath11k_ce_rx_post_pipe(struct ath11k_ce_pipe *pipe) +{ + struct ath11k_base *ab = pipe->ab; + struct sk_buff *skb; + dma_addr_t paddr; + int ret = 0; + + if (!(pipe->dest_ring || pipe->status_ring)) + return 0; + + spin_lock_bh(&ab->ce.ce_lock); + while (pipe->rx_buf_needed) { + skb = dev_alloc_skb(pipe->buf_sz); + if (!skb) { + ret = -ENOMEM; + goto exit; + } + + WARN_ON_ONCE(!IS_ALIGNED((unsigned long)skb->data, 4)); + + paddr = dma_map_single(ab->dev, skb->data, + skb->len + skb_tailroom(skb), + DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(ab->dev, paddr))) { + ath11k_warn(ab, "failed to dma map ce rx buf\n"); + dev_kfree_skb_any(skb); + ret = -EIO; + goto exit; + } + + ATH11K_SKB_RXCB(skb)->paddr = paddr; + + ret = ath11k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr); + + if (ret) { + ath11k_warn(ab, "failed to enqueue rx buf: %d\n", ret); + dma_unmap_single(ab->dev, paddr, + skb->len + skb_tailroom(skb), + DMA_FROM_DEVICE); + dev_kfree_skb_any(skb); + goto exit; + } + } + +exit: + spin_unlock_bh(&ab->ce.ce_lock); + return ret; +} + +static int ath11k_ce_completed_recv_next(struct ath11k_ce_pipe *pipe, + struct sk_buff **skb, int *nbytes) +{ + struct ath11k_base *ab = pipe->ab; + struct hal_srng *srng; + unsigned int sw_index; + unsigned int nentries_mask; + u32 *desc; + int ret = 0; + + spin_lock_bh(&ab->ce.ce_lock); + + sw_index = pipe->dest_ring->sw_index; + nentries_mask = pipe->dest_ring->nentries_mask; + + srng = &ab->hal.srng_list[pipe->status_ring->hal_ring_id]; + + spin_lock_bh(&srng->lock); + + ath11k_hal_srng_access_begin(ab, srng); + + desc = ath11k_hal_srng_dst_get_next_entry(ab, srng); + if (!desc) { + ret = -EIO; + goto err; + } + + *nbytes = ath11k_hal_ce_dst_status_get_length(desc); + if (*nbytes == 0) { + ret = -EIO; + goto err; + } + + *skb = pipe->dest_ring->skb[sw_index]; + pipe->dest_ring->skb[sw_index] = NULL; + + sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); + pipe->dest_ring->sw_index = sw_index; + + pipe->rx_buf_needed++; +err: + ath11k_hal_srng_access_end(ab, srng); + + spin_unlock_bh(&srng->lock); + + spin_unlock_bh(&ab->ce.ce_lock); + + return ret; +} + +static void ath11k_ce_recv_process_cb(struct ath11k_ce_pipe *pipe) +{ + struct ath11k_base *ab = pipe->ab; + struct sk_buff *skb; + struct sk_buff_head list; + unsigned int nbytes, max_nbytes; + int ret; + + __skb_queue_head_init(&list); + while (ath11k_ce_completed_recv_next(pipe, &skb, &nbytes) == 0) { + max_nbytes = skb->len + skb_tailroom(skb); + dma_unmap_single(ab->dev, ATH11K_SKB_RXCB(skb)->paddr, + max_nbytes, DMA_FROM_DEVICE); + + if (unlikely(max_nbytes < nbytes)) { + ath11k_warn(ab, "rxed more than expected (nbytes %d, max %d)", + nbytes, max_nbytes); + dev_kfree_skb_any(skb); + continue; + } + + skb_put(skb, nbytes); + __skb_queue_tail(&list, skb); + } + + while ((skb = __skb_dequeue(&list))) { + ath11k_dbg(ab, ATH11K_DBG_AHB, "rx ce pipe %d len %d\n", + pipe->pipe_num, skb->len); + pipe->recv_cb(ab, skb); + } + + ret = ath11k_ce_rx_post_pipe(pipe); + if (ret && ret != -ENOSPC) { + ath11k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n", + pipe->pipe_num, ret); + mod_timer(&ab->rx_replenish_retry, + jiffies + ATH11K_CE_RX_POST_RETRY_JIFFIES); + } +} + +static struct sk_buff *ath11k_ce_completed_send_next(struct ath11k_ce_pipe *pipe) +{ + struct ath11k_base *ab = pipe->ab; + struct hal_srng *srng; + unsigned int sw_index; + unsigned int nentries_mask; + struct sk_buff *skb; + u32 *desc; + + spin_lock_bh(&ab->ce.ce_lock); + + sw_index = pipe->src_ring->sw_index; + nentries_mask = pipe->src_ring->nentries_mask; + + srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id]; + + spin_lock_bh(&srng->lock); + + ath11k_hal_srng_access_begin(ab, srng); + + desc = ath11k_hal_srng_src_reap_next(ab, srng); + if (!desc) { + skb = ERR_PTR(-EIO); + goto err_unlock; + } + + skb = pipe->src_ring->skb[sw_index]; + + pipe->src_ring->skb[sw_index] = NULL; + + sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index); + pipe->src_ring->sw_index = sw_index; + +err_unlock: + spin_unlock_bh(&srng->lock); + + spin_unlock_bh(&ab->ce.ce_lock); + + return skb; +} + +static void ath11k_ce_send_done_cb(struct ath11k_ce_pipe *pipe) +{ + struct ath11k_base *ab = pipe->ab; + struct sk_buff *skb; + + while (!IS_ERR(skb = ath11k_ce_completed_send_next(pipe))) { + if (!skb) + continue; + + dma_unmap_single(ab->dev, ATH11K_SKB_CB(skb)->paddr, skb->len, + DMA_TO_DEVICE); + dev_kfree_skb_any(skb); + } +} + +static int ath11k_ce_init_ring(struct ath11k_base *ab, + struct ath11k_ce_ring *ce_ring, + int ce_id, enum hal_ring_type type) +{ + struct hal_srng_params params = { 0 }; + int ret; + + params.ring_base_paddr = ce_ring->base_addr_ce_space; + params.ring_base_vaddr = ce_ring->base_addr_owner_space; + params.num_entries = ce_ring->nentries; + + switch (type) { + case HAL_CE_SRC: + if (!(CE_ATTR_DIS_INTR & host_ce_config_wlan[ce_id].flags)) + params.intr_batch_cntr_thres_entries = 1; + break; + case HAL_CE_DST: + params.max_buffer_len = host_ce_config_wlan[ce_id].src_sz_max; + if (!(host_ce_config_wlan[ce_id].flags & CE_ATTR_DIS_INTR)) { + params.intr_timer_thres_us = 1024; + params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; + params.low_threshold = ce_ring->nentries - 3; + } + break; + case HAL_CE_DST_STATUS: + if (!(host_ce_config_wlan[ce_id].flags & CE_ATTR_DIS_INTR)) { + params.intr_batch_cntr_thres_entries = 1; + params.intr_timer_thres_us = 0x1000; + } + break; + default: + ath11k_warn(ab, "Invalid CE ring type %d\n", type); + return -EINVAL; + } + + /* TODO: Init other params needed by HAL to init the ring */ + + ret = ath11k_hal_srng_setup(ab, type, ce_id, 0, ¶ms); + if (ret < 0) { + ath11k_warn(ab, "failed to setup srng: %d ring_id %d\n", + ret, ce_id); + return ret; + } + ce_ring->hal_ring_id = ret; + + return 0; +} + +static struct ath11k_ce_ring * +ath11k_ce_alloc_ring(struct ath11k_base *ab, int nentries, int desc_sz) +{ + struct ath11k_ce_ring *ce_ring; + dma_addr_t base_addr; + + ce_ring = kzalloc(struct_size(ce_ring, skb, nentries), GFP_KERNEL); + if (ce_ring == NULL) + return ERR_PTR(-ENOMEM); + + ce_ring->nentries = nentries; + ce_ring->nentries_mask = nentries - 1; + + /* Legacy platforms that do not support cache + * coherent DMA are unsupported + */ + ce_ring->base_addr_owner_space_unaligned = + dma_alloc_coherent(ab->dev, + nentries * desc_sz + CE_DESC_RING_ALIGN, + &base_addr, GFP_KERNEL); + if (!ce_ring->base_addr_owner_space_unaligned) { + kfree(ce_ring); + return ERR_PTR(-ENOMEM); + } + + ce_ring->base_addr_ce_space_unaligned = base_addr; + + ce_ring->base_addr_owner_space = PTR_ALIGN( + ce_ring->base_addr_owner_space_unaligned, + CE_DESC_RING_ALIGN); + ce_ring->base_addr_ce_space = ALIGN( + ce_ring->base_addr_ce_space_unaligned, + CE_DESC_RING_ALIGN); + + return ce_ring; +} + +static int ath11k_ce_alloc_pipe(struct ath11k_base *ab, int ce_id) +{ + struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id]; + const struct ce_attr *attr = &host_ce_config_wlan[ce_id]; + int nentries; + int desc_sz; + + pipe->attr_flags = attr->flags; + + if (attr->src_nentries) { + pipe->send_cb = ath11k_ce_send_done_cb; + nentries = roundup_pow_of_two(attr->src_nentries); + desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_SRC); + pipe->src_ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz); + if (!pipe->src_ring) + return -ENOMEM; + } + + if (attr->dest_nentries) { + pipe->recv_cb = attr->recv_cb; + nentries = roundup_pow_of_two(attr->dest_nentries); + desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST); + pipe->dest_ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz); + + if (!pipe->dest_ring) + return -ENOMEM; + + desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS); + pipe->status_ring = ath11k_ce_alloc_ring(ab, nentries, desc_sz); + if (!pipe->status_ring) + return -ENOMEM; + } + + return 0; +} + +void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id) +{ + struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id]; + + if (pipe->send_cb) + pipe->send_cb(pipe); + + if (pipe->recv_cb) + ath11k_ce_recv_process_cb(pipe); +} + +void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id) +{ + struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id]; + + if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && pipe->send_cb) + pipe->send_cb(pipe); +} + +int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id, + u16 transfer_id) +{ + struct ath11k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id]; + struct hal_srng *srng; + u32 *desc; + unsigned int write_index, sw_index; + unsigned int nentries_mask; + int ret = 0; + u8 byte_swap_data = 0; + int num_used; + + /* Check if some entries could be regained by handling tx completion if + * the CE has interrupts disabled and the used entries is more than the + * defined usage threshold. + */ + if (pipe->attr_flags & CE_ATTR_DIS_INTR) { + spin_lock_bh(&ab->ce.ce_lock); + write_index = pipe->src_ring->write_index; + + sw_index = pipe->src_ring->sw_index; + + if (write_index >= sw_index) + num_used = write_index - sw_index; + else + num_used = pipe->src_ring->nentries - sw_index + + write_index; + + spin_unlock_bh(&ab->ce.ce_lock); + + if (num_used > ATH11K_CE_USAGE_THRESHOLD) + ath11k_ce_poll_send_completed(ab, pipe->pipe_num); + } + + if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) + return -ESHUTDOWN; + + spin_lock_bh(&ab->ce.ce_lock); + + write_index = pipe->src_ring->write_index; + nentries_mask = pipe->src_ring->nentries_mask; + + srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id]; + + spin_lock_bh(&srng->lock); + + ath11k_hal_srng_access_begin(ab, srng); + + if (unlikely(ath11k_hal_srng_src_num_free(ab, srng, false) < 1)) { + ath11k_hal_srng_access_end(ab, srng); + ret = -ENOBUFS; + goto err_unlock; + } + + desc = ath11k_hal_srng_src_get_next_reaped(ab, srng); + if (!desc) { + ath11k_hal_srng_access_end(ab, srng); + ret = -ENOBUFS; + goto err_unlock; + } + + if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA) + byte_swap_data = 1; + + ath11k_hal_ce_src_set_desc(desc, ATH11K_SKB_CB(skb)->paddr, + skb->len, transfer_id, byte_swap_data); + + pipe->src_ring->skb[write_index] = skb; + pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask, + write_index); + + ath11k_hal_srng_access_end(ab, srng); + + spin_unlock_bh(&srng->lock); + + spin_unlock_bh(&ab->ce.ce_lock); + + return 0; + +err_unlock: + spin_unlock_bh(&srng->lock); + + spin_unlock_bh(&ab->ce.ce_lock); + + return ret; +} + +static void ath11k_ce_rx_pipe_cleanup(struct ath11k_ce_pipe *pipe) +{ + struct ath11k_base *ab = pipe->ab; + struct ath11k_ce_ring *ring = pipe->dest_ring; + struct sk_buff *skb; + int i; + + if (!(ring && pipe->buf_sz)) + return; + + for (i = 0; i < ring->nentries; i++) { + skb = ring->skb[i]; + if (!skb) + continue; + + ring->skb[i] = NULL; + dma_unmap_single(ab->dev, ATH11K_SKB_RXCB(skb)->paddr, + skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); + dev_kfree_skb_any(skb); + } +} + +void ath11k_ce_cleanup_pipes(struct ath11k_base *ab) +{ + struct ath11k_ce_pipe *pipe; + int pipe_num; + + for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { + pipe = &ab->ce.ce_pipe[pipe_num]; + ath11k_ce_rx_pipe_cleanup(pipe); + + /* Cleanup any src CE's which have interrupts disabled */ + ath11k_ce_poll_send_completed(ab, pipe_num); + + /* NOTE: Should we also clean up tx buffer in all pipes? */ + } +} + +void ath11k_ce_rx_post_buf(struct ath11k_base *ab) +{ + struct ath11k_ce_pipe *pipe; + int i; + int ret; + + for (i = 0; i < CE_COUNT; i++) { + pipe = &ab->ce.ce_pipe[i]; + ret = ath11k_ce_rx_post_pipe(pipe); + if (ret) { + if (ret == -ENOSPC) + continue; + + ath11k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n", + i, ret); + mod_timer(&ab->rx_replenish_retry, + jiffies + ATH11K_CE_RX_POST_RETRY_JIFFIES); + + return; + } + } +} + +void ath11k_ce_rx_replenish_retry(struct timer_list *t) +{ + struct ath11k_base *ab = from_timer(ab, t, rx_replenish_retry); + + ath11k_ce_rx_post_buf(ab); +} + +int ath11k_ce_init_pipes(struct ath11k_base *ab) +{ + struct ath11k_ce_pipe *pipe; + int i; + int ret; + + for (i = 0; i < CE_COUNT; i++) { + pipe = &ab->ce.ce_pipe[i]; + + if (pipe->src_ring) { + ret = ath11k_ce_init_ring(ab, pipe->src_ring, i, + HAL_CE_SRC); + if (ret) { + ath11k_warn(ab, "failed to init src ring: %d\n", + ret); + /* Should we clear any partial init */ + return ret; + } + + pipe->src_ring->write_index = 0; + pipe->src_ring->sw_index = 0; + } + + if (pipe->dest_ring) { + ret = ath11k_ce_init_ring(ab, pipe->dest_ring, i, + HAL_CE_DST); + if (ret) { + ath11k_warn(ab, "failed to init dest ring: %d\n", + ret); + /* Should we clear any partial init */ + return ret; + } + + pipe->rx_buf_needed = pipe->dest_ring->nentries ? + pipe->dest_ring->nentries - 2 : 0; + + pipe->dest_ring->write_index = 0; + pipe->dest_ring->sw_index = 0; + } + + if (pipe->status_ring) { + ret = ath11k_ce_init_ring(ab, pipe->status_ring, i, + HAL_CE_DST_STATUS); + if (ret) { + ath11k_warn(ab, "failed to init dest status ing: %d\n", + ret); + /* Should we clear any partial init */ + return ret; + } + + pipe->status_ring->write_index = 0; + pipe->status_ring->sw_index = 0; + } + } + + return 0; +} + +void ath11k_ce_free_pipes(struct ath11k_base *ab) +{ + struct ath11k_ce_pipe *pipe; + int desc_sz; + int i; + + for (i = 0; i < CE_COUNT; i++) { + pipe = &ab->ce.ce_pipe[i]; + + if (pipe->src_ring) { + desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_SRC); + dma_free_coherent(ab->dev, + pipe->src_ring->nentries * desc_sz + + CE_DESC_RING_ALIGN, + pipe->src_ring->base_addr_owner_space, + pipe->src_ring->base_addr_ce_space); + kfree(pipe->src_ring); + pipe->src_ring = NULL; + } + + if (pipe->dest_ring) { + desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST); + dma_free_coherent(ab->dev, + pipe->dest_ring->nentries * desc_sz + + CE_DESC_RING_ALIGN, + pipe->dest_ring->base_addr_owner_space, + pipe->dest_ring->base_addr_ce_space); + kfree(pipe->dest_ring); + pipe->dest_ring = NULL; + } + + if (pipe->status_ring) { + desc_sz = + ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS); + dma_free_coherent(ab->dev, + pipe->status_ring->nentries * desc_sz + + CE_DESC_RING_ALIGN, + pipe->status_ring->base_addr_owner_space, + pipe->status_ring->base_addr_ce_space); + kfree(pipe->status_ring); + pipe->status_ring = NULL; + } + } +} + +int ath11k_ce_alloc_pipes(struct ath11k_base *ab) +{ + struct ath11k_ce_pipe *pipe; + int i; + int ret; + const struct ce_attr *attr; + + spin_lock_init(&ab->ce.ce_lock); + + for (i = 0; i < CE_COUNT; i++) { + attr = &host_ce_config_wlan[i]; + pipe = &ab->ce.ce_pipe[i]; + pipe->pipe_num = i; + pipe->ab = ab; + pipe->buf_sz = attr->src_sz_max; + + ret = ath11k_ce_alloc_pipe(ab, i); + if (ret) { + /* Free any parial successful allocation */ + ath11k_ce_free_pipes(ab); + return ret; + } + } + + return 0; +} + +/* For Big Endian Host, Copy Engine byte_swap is enabled + * When Copy Engine does byte_swap, need to byte swap again for the + * Host to get/put buffer content in the correct byte order + */ +void ath11k_ce_byte_swap(void *mem, u32 len) +{ + int i; + + if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { + if (!mem) + return; + + for (i = 0; i < (len / 4); i++) { + *(u32 *)mem = swab32(*(u32 *)mem); + mem += 4; + } + } +} + +int ath11k_ce_get_attr_flags(int ce_id) +{ + if (ce_id >= CE_COUNT) + return -EINVAL; + + return host_ce_config_wlan[ce_id].flags; +} diff --git a/drivers/net/wireless/ath/ath11k/ce.h b/drivers/net/wireless/ath/ath11k/ce.h new file mode 100644 index 000000000000..6174eac84410 --- /dev/null +++ b/drivers/net/wireless/ath/ath11k/ce.h @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + */ + +#ifndef ATH11K_CE_H +#define ATH11K_CE_H + +#define CE_COUNT 12 + +/* Byte swap data words */ +#define CE_ATTR_BYTE_SWAP_DATA 2 + +/* no interrupt on copy completion */ +#define CE_ATTR_DIS_INTR 8 + +/* Host software's Copy Engine configuration. */ +#ifdef __BIG_ENDIAN +#define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA +#else +#define CE_ATTR_FLAGS 0 +#endif + +/* Threshold to poll for tx completion in case of Interrupt disabled CE's */ +#define ATH11K_CE_USAGE_THRESHOLD 32 + +void ath11k_ce_byte_swap(void *mem, u32 len); + +/* + * Directions for interconnect pipe configuration. + * These definitions may be used during configuration and are shared + * between Host and Target. + * + * Pipe Directions are relative to the Host, so PIPEDIR_IN means + * "coming IN over air through Target to Host" as with a WiFi Rx operation. + * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" + * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" + * Target since things that are "PIPEDIR_OUT" are coming IN to the Target + * over the interconnect. + */ +#define PIPEDIR_NONE 0 +#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ +#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ +#define PIPEDIR_INOUT 3 /* bidirectional */ +#define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ + +/* CE address/mask */ +#define CE_HOST_IE_ADDRESS 0x00A1803C +#define CE_HOST_IE_2_ADDRESS 0x00A18040 +#define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS + +#define CE_HOST_IE_3_SHIFT 0xC + +#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) + +#define ATH11K_CE_RX_POST_RETRY_JIFFIES 50 + +struct ath11k_base; + +/* Establish a mapping between a service/direction and a pipe. */ +struct service_to_pipe { + __le32 service_id; + __le32 pipedir; + __le32 pipenum; +}; + +/* + * Configuration information for a Copy Engine pipe. + * Passed from Host to Target during startup (one per CE). + * + * NOTE: Structure is shared between Host software and Target firmware! + */ +struct ce_pipe_config { + __le32 pipenum; + __le32 pipedir; + __le32 nentries; + __le32 nbytes_max; + __le32 flags; + __le32 reserved; +}; + +struct ce_attr { + /* CE_ATTR_* values */ + unsigned int flags; + + /* #entries in source ring - Must be a power of 2 */ + unsigned int src_nentries; + + /* + * Max source send size for this CE. + * This is also the minimum size of a destination buffer. + */ + unsigned int src_sz_max; + + /* #entries in destination ring - Must be a power of 2 */ + unsigned int dest_nentries; + + void (*recv_cb)(struct ath11k_base *, struct sk_buff *); +}; + +#define CE_DESC_RING_ALIGN 8 + +struct ath11k_ce_ring { + /* Number of entries in this ring; must be power of 2 */ + unsigned int nentries; + unsigned int nentries_mask; + + /* For dest ring, this is the next index to be processed + * by software after it was/is received into. + * + * For src ring, this is the last descriptor that was sent + * and completion processed by software. + * + * Regardless of src or dest ring, this is an invariant + * (modulo ring size): + * write index >= read index >= sw_index + */ + unsigned int sw_index; + /* cached copy */ + unsigned int write_index; + + /* Start of DMA-coherent area reserved for descriptors */ + /* Host address space */ + void *base_addr_owner_space_unaligned; + /* CE address space */ + u32 base_addr_ce_space_unaligned; + + /* Actual start of descriptors. + * Aligned to descriptor-size boundary. + * Points into reserved DMA-coherent area, above. + */ + /* Host address space */ + void *base_addr_owner_space; + + /* CE address space */ + u32 base_addr_ce_space; + + /* HAL ring id */ + u32 hal_ring_id; + + /* keep last */ + struct sk_buff *skb[0]; +}; + +struct ath11k_ce_pipe { + struct ath11k_base *ab; + u16 pipe_num; + unsigned int attr_flags; + unsigned int buf_sz; + unsigned int rx_buf_needed; + + void (*send_cb)(struct ath11k_ce_pipe *); + void (*recv_cb)(struct ath11k_base *, struct sk_buff *); + + struct tasklet_struct intr_tq; + struct ath11k_ce_ring *src_ring; + struct ath11k_ce_ring *dest_ring; + struct ath11k_ce_ring *status_ring; +}; + +struct ath11k_ce { + struct ath11k_ce_pipe ce_pipe[CE_COUNT]; + /* Protects rings of all ce pipes */ + spinlock_t ce_lock; +}; + +void ath11k_ce_cleanup_pipes(struct ath11k_base *ab); +void ath11k_ce_rx_replenish_retry(struct timer_list *t); +void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id); +int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id, + u16 transfer_id); +void ath11k_ce_rx_post_buf(struct ath11k_base *ab); +int ath11k_ce_init_pipes(struct ath11k_base *ab); +int ath11k_ce_alloc_pipes(struct ath11k_base *ab); +void ath11k_ce_free_pipes(struct ath11k_base *ab); +int ath11k_ce_get_attr_flags(int ce_id); +void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id); +#endif diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c new file mode 100644 index 000000000000..b0c71b5879b1 --- /dev/null +++ b/drivers/net/wireless/ath/ath11k/core.c @@ -0,0 +1,772 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include "ahb.h" +#include "core.h" +#include "dp_tx.h" +#include "debug.h" + +unsigned int ath11k_debug_mask; +module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); +MODULE_PARM_DESC(debug_mask, "Debugging mask"); + +static const struct ath11k_hw_params ath11k_hw_params = { + .name = "ipq8074", + .fw = { + .dir = IPQ8074_FW_DIR, + .board_size = IPQ8074_MAX_BOARD_DATA_SZ, + .cal_size = IPQ8074_MAX_CAL_DATA_SZ, + }, +}; + +/* Map from pdev index to hw mac index */ +u8 ath11k_core_get_hw_mac_id(struct ath11k_base *ab, int pdev_idx) +{ + switch (pdev_idx) { + case 0: + return 0; + case 1: + return 2; + case 2: + return 1; + default: + ath11k_warn(ab, "Invalid pdev idx %d\n", pdev_idx); + return ATH11K_INVALID_HW_MAC_ID; + } +} + +static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, + size_t name_len) +{ + /* Note: bus is fixed to ahb. When other bus type supported, + * make it to dynamic.