From 47b06fc2d97a0d98d6053357561f2953d6547d25 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 13 Sep 2014 00:34:31 +0200 Subject: ARM: rockchip: add a cpufreq-cpu0 device Rockchip SoCs can sucessfully use the generic cpufreq-cpu0 driver to do frequency scaling. Therefore add a platform device in the machine init code. Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/rockchip.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 8ab9e0e7ff04..eea1f06366e6 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -24,6 +24,12 @@ #include #include "core.h" +static void __init rockchip_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + platform_device_register_simple("cpufreq-cpu0", 0, NULL, 0); +} + static const char * const rockchip_board_dt_compat[] = { "rockchip,rk2928", "rockchip,rk3066a", @@ -37,4 +43,5 @@ DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, .dt_compat = rockchip_board_dt_compat, + .init_machine = rockchip_dt_init, MACHINE_END -- cgit v1.2.3 From 3eb79a5a9d46b32f63f6b9cd86f9b2bba43e127a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 30 Sep 2014 10:33:27 +0200 Subject: ARM: rockchip: honor renaming of cpufreq-cpu0 to cpufreq-dt cpufreq-cpu0 got renamed to a more generic name cpufreq-dt, so adapt the created platform-device to this. Reported-by: Viresh Kumar Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index eea1f06366e6..d226b71d21d5 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -27,7 +27,7 @@ static void __init rockchip_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - platform_device_register_simple("cpufreq-cpu0", 0, NULL, 0); + platform_device_register_simple("cpufreq-dt", 0, NULL, 0); } static const char * const rockchip_board_dt_compat[] = { -- cgit v1.2.3 From 0da6e72504f327c051979745843b5c614565e2ed Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 24 Sep 2014 23:09:09 +0800 Subject: Documentation: sunxi: Update Allwinner SoC documentation (A31/A31s/A23) Lately we have received documentation for A31 and A31s, in addition to A23 documentation which was received earlier but not added. Add these to the README, and update to reflect that A31 and A23 are supported. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentation/arm/sunxi/README | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index 7945238453ed..57c4da6a9ed2 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README @@ -37,15 +37,24 @@ SunXi family http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf - Allwinner A23 - + Not Supported + + Datasheet + http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf + + User Manual + http://dl.linux-sunxi.org/A23/A23%20User%20Manual%20V1.0%2020130830.pdf * Quad ARM Cortex-A7 based SoCs - Allwinner A31 (sun6i) + Datasheet - http://dl.linux-sunxi.org/A31/A31%20Datasheet%20-%20v1.00%20(2012-12-24).pdf + http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf + + User Manual + http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20user%20manual%20V1.1%2020130630.pdf - Allwinner A31s (sun6i) + Not Supported + + Datasheet + http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20datasheet%20V1.3%2020131106.pdf + + User Manual + http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20User%20Manual%20%20V1.0%2020130322.pdf * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs - Allwinner A80 -- cgit v1.2.3 From d4da889a53d9dabe1c75384f3175dab7ff06c4ee Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 24 Sep 2014 22:48:56 +0800 Subject: ARM: sunxi: Add debug uart used by sun9i (Allwinner A80) The uarts on sun9i are still compatible with the dw_8250, but are located at different addresses. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/Kconfig.debug | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 03dc4c1a8736..0bc06ab9fb86 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -731,6 +731,14 @@ choice Say Y here if you want kernel low-level debugging support on SOCFPGA based platforms. + config DEBUG_SUN9I_UART0 + bool "Kernel low-level debugging messages via sun9i UART0" + depends on MACH_SUN9I + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Allwinner A80 based platforms on the UART0. + config DEBUG_SUNXI_UART0 bool "Kernel low-level debugging messages via sunXi UART0" depends on ARCH_SUNXI @@ -1106,6 +1114,7 @@ config DEBUG_UART_PHYS default 0x02530c00 if DEBUG_KEYSTONE_UART0 default 0x02531000 if DEBUG_KEYSTONE_UART1 default 0x03010fe0 if ARCH_RPC + default 0x07000000 if DEBUG_SUN9I_UART0 default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \ DEBUG_VEXPRESS_UART0_CA9 default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT @@ -1190,6 +1199,7 @@ config DEBUG_UART_VIRT default 0xf2100000 if DEBUG_PXA_UART1 default 0xf4090000 if ARCH_LPC32XX default 0xf4200000 if ARCH_GEMINI + default 0xf7000000 if DEBUG_SUN9I_UART0 default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \ DEBUG_S3C2410_UART0) default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \ -- cgit v1.2.3 From bb647665bae4dfdf7e1d07540325eab81f9800a8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 24 Sep 2014 22:48:59 +0800 Subject: devicetree: bindings: Add vendor prefix for Merrii Technology Co., Ltd. Merrii Technology Co., Ltd. is a Chinese ARM integration developer that specializes in Allwinner SoC based designs. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 723999d73744..3da78a14e6c7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -90,6 +90,7 @@ lltc Linear Technology Corporation marvell Marvell Technology Group Ltd. maxim Maxim Integrated Products mediatek MediaTek Inc. +merrii Merrii Technology Co., Ltd. micrel Micrel Inc. microchip Microchip Technology Inc. mitsubishi Mitsubishi Electric Corporation -- cgit v1.2.3 From 3d4c2f1ced78fc6f74d0d9ddb25f66722f978fd1 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 8 Oct 2014 21:02:52 +0800 Subject: ARM: sunxi: Introduce Allwinner A80 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Allwinner A80 is a new Cortex octo-core A7/A15 big.LITTLE SoC. While it's processor cores and interconnecting bus are new, it re-uses many peripherals found in earlier Allwinner SoCs. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Tested-by: Andreas Färber --- arch/arm/mach-sunxi/Kconfig | 5 +++++ arch/arm/mach-sunxi/sunxi.c | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 1aaa1e15ef70..d04f84b4f937 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -42,4 +42,9 @@ config MACH_SUN8I select MFD_SUN6I_PRCM select RESET_CONTROLLER +config MACH_SUN9I + bool "Allwinner (sun9i) SoCs support" + default ARCH_SUNXI + select ARM_GIC + endif diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index d7598aeed803..1f986758784a 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -63,3 +63,12 @@ static const char * const sun8i_board_dt_compat[] = { DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family") .dt_compat = sun8i_board_dt_compat, MACHINE_END + +static const char * const sun9i_board_dt_compat[] = { + "allwinner,sun9i-a80", + NULL, +}; + +DT_MACHINE_START(SUN9I_DT, "Allwinner sun9i Family") + .dt_compat = sun9i_board_dt_compat, +MACHINE_END -- cgit v1.2.3 From a1a0193bdd855d0bcfbfc62fa59882242236882b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 8 Oct 2014 21:02:55 +0800 Subject: devicetree: bindings: Document supported Allwinner sunxi SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds a list of supported Allwinner SoC bindings. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Tested-by: Andreas Färber --- Documentation/devicetree/bindings/arm/sunxi.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunxi.txt diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt new file mode 100644 index 000000000000..42941fdefb11 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -0,0 +1,12 @@ +Allwinner sunXi Platforms Device Tree Bindings + +Each device tree must specify which Allwinner SoC it uses, +using one of the following compatible strings: + + allwinner,sun4i-a10 + allwinner,sun5i-a10s + allwinner,sun5i-a13 + allwinner,sun6i-a31 + allwinner,sun7i-a20 + allwinner,sun8i-a23 + allwinner,sun9i-a80 -- cgit v1.2.3 From 19e704e35e33e2e468a4d038f83003ff9e9bd4cd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 8 Oct 2014 21:02:56 +0800 Subject: Documentation: sunxi: Add A80 datasheet link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We now have initial support for the A80, as well a the datasheet. Update the documents to reflect this. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Tested-by: Andreas Färber --- Documentation/arm/sunxi/README | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index 57c4da6a9ed2..e68d163df33d 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README @@ -58,4 +58,5 @@ SunXi family * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs - Allwinner A80 - + Not Supported \ No newline at end of file + + Datasheet + http://dl.linux-sunxi.org/A80/A80_Datasheet_Revision_1.0_0404.pdf -- cgit v1.2.3 From 2f4bc73445fd3786b91d24b879fed527ef533cbf Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 12 Oct 2014 17:40:24 +0800 Subject: ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER for sun9i The A80 SoC has reset controls matching bus clock gates. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/mach-sunxi/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d04f84b4f937..a77604fbaf25 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -45,6 +45,8 @@ config MACH_SUN8I config MACH_SUN9I bool "Allwinner (sun9i) SoCs support" default ARCH_SUNXI + select ARCH_HAS_RESET_CONTROLLER select ARM_GIC + select RESET_CONTROLLER endif -- cgit v1.2.3 From 32ed35ff22ec03d8a935dfe8b90c599da4b4cb02 Mon Sep 17 00:00:00 2001 From: Vikas Sajjan Date: Wed, 24 Sep 2014 16:45:13 +0900 Subject: ARM: EXYNOS: Move Disabling of JPEG USE_RETENTION for exynos5250 to pmu.c Move the Disabling of JPEG USE_RETENTION for exynos5250 to pmu.c to make way for refactoring of pm.c and to create common functions across exynos4 and exynos5250. Signed-off-by: Vikas Sajjan Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/pm.c | 7 +------ arch/arm/mach-exynos/pmu.c | 1 + 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index abefacb45976..31e209b38f41 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -255,13 +255,8 @@ static void exynos_pm_prepare(void) s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (soc_is_exynos5250()) { + if (soc_is_exynos5250()) s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); - /* Disable USE_RETENTION of JPEG_MEM_OPTION */ - tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION); - tmp &= ~EXYNOS5_OPTION_USE_RETENTION; - pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); - } /* Set value of power down register for sleep mode */ diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index ff9d23f0a7d9..cfc62e86cdee 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -264,6 +264,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = { { EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, { EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, { EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, + { EXYNOS5_JPEG_MEM_OPTION, { 0x10, 0x10, 0x0} }, { EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, { EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, -- cgit v1.2.3 From 066da1ae52c30ae7e2792dbbb0d6bcbba493245e Mon Sep 17 00:00:00 2001 From: Vikas Sajjan Date: Wed, 24 Sep 2014 16:45:14 +0900 Subject: ARM: EXYNOS: Refactor the pm code to use DT based lookup Refactoring the pm.c to avoid using "soc_is_exynos" checks, instead use the DT based lookup. While at it, consolidate the common code across SoCs and create static helper functions. Signed-off-by: Vikas Sajjan Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/pm.c | 167 ++++++++++++++++++++++++++++++---------- arch/arm/mach-exynos/regs-pmu.h | 1 + 2 files changed, 126 insertions(+), 42 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 31e209b38f41..16b23d156eec 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -36,6 +36,8 @@ #include "regs-pmu.h" #include "regs-sys.h" +#define REG_TABLE_END (-1U) + /** * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping * @hwirq: Hardware IRQ signal of the GIC @@ -59,6 +61,21 @@ static struct sleep_save exynos_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; +struct exynos_pm_data { + const struct exynos_wkup_irq *wkup_irq; + struct sleep_save *extra_save; + int num_extra_save; + unsigned int wake_disable_mask; + unsigned int *release_ret_regs; + + void (*pm_prepare)(void); + void (*pm_resume)(void); + int (*pm_suspend)(void); + int (*cpu_suspend)(unsigned long); +}; + +struct exynos_pm_data *pm_data; + /* * GIC wake-up support */ @@ -77,14 +94,24 @@ static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { { /* sentinel */ }, }; +unsigned int exynos_release_ret_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, + REG_TABLE_END, +}; + static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) { const struct exynos_wkup_irq *wkup_irq; - if (soc_is_exynos5250()) - wkup_irq = exynos5250_wkup_irq; - else - wkup_irq = exynos4_wkup_irq; + if (!pm_data->wkup_irq) + return -ENOENT; + wkup_irq = pm_data->wkup_irq; while (wkup_irq->mask) { if (wkup_irq->hwirq == data->hwirq) { @@ -229,15 +256,8 @@ void exynos_enter_aftr(void) cpu_pm_exit(); } -static int exynos_cpu_suspend(unsigned long arg) +static int exynos_cpu_do_idle(void) { -#ifdef CONFIG_CACHE_L2X0 - outer_flush_all(); -#endif - - if (soc_is_exynos5250()) - flush_cache_all(); - /* issue the standby signal into the pm unit. */ cpu_do_idle(); @@ -245,29 +265,44 @@ static int exynos_cpu_suspend(unsigned long arg) return 1; /* Aborting suspend */ } -static void exynos_pm_prepare(void) +static int exynos_cpu_suspend(unsigned long arg) { - unsigned int tmp; + flush_cache_all(); + outer_flush_all(); + return exynos_cpu_do_idle(); +} +static void exynos_pm_set_wakeup_mask(void) +{ /* Set wake-up mask registers */ pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); +} - s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - - if (soc_is_exynos5250()) - s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); - +static void exynos_pm_enter_sleep_mode(void) +{ /* Set value of power down register for sleep mode */ - exynos_sys_powerdown_conf(SYS_SLEEP); pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); /* ensure at least INFORM0 has the resume address */ - pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); } +static void exynos_pm_prepare(void) +{ + /* Set wake-up mask registers */ + exynos_pm_set_wakeup_mask(); + + s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); + + if (pm_data->extra_save) + s3c_pm_do_save(pm_data->extra_save, + pm_data->num_extra_save); + + exynos_pm_enter_sleep_mode(); +} + static int exynos_pm_suspend(void) { unsigned long tmp; @@ -285,6 +320,15 @@ static int exynos_pm_suspend(void) return 0; } +static void exynos_pm_release_retention(void) +{ + unsigned int i; + + for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) + pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, + pm_data->release_ret_regs[i]); +} + static void exynos_pm_resume(void) { if (exynos_pm_central_resume()) @@ -294,18 +338,11 @@ static void exynos_pm_resume(void) exynos_cpu_restore_register(); /* For release retention */ + exynos_pm_release_retention(); - pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); - pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); - pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); - pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); - pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); - pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); - pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); - - if (soc_is_exynos5250()) - s3c_pm_do_restore(exynos5_sys_save, - ARRAY_SIZE(exynos5_sys_save)); + if (pm_data->extra_save) + s3c_pm_do_restore_core(pm_data->extra_save, + pm_data->num_extra_save); s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); @@ -316,15 +353,8 @@ early_wakeup: /* Clear SLEEP mode set in INFORM1 */ pmu_raw_writel(0x0, S5P_INFORM1); - - return; } -static struct syscore_ops exynos_pm_syscore_ops = { - .suspend = exynos_pm_suspend, - .resume = exynos_pm_resume, -}; - /* * Suspend Ops */ @@ -348,11 +378,12 @@ static int exynos_suspend_enter(suspend_state_t state) } s3c_pm_save_uarts(); - exynos_pm_prepare(); + if (pm_data->pm_prepare) + pm_data->pm_prepare(); flush_cache_all(); s3c_pm_check_store(); - ret = cpu_suspend(0, exynos_cpu_suspend); + ret = cpu_suspend(0, pm_data->cpu_suspend); if (ret) return ret; @@ -387,18 +418,70 @@ static const struct platform_suspend_ops exynos_suspend_ops = { .valid = suspend_valid_only_mem, }; +static const struct exynos_pm_data exynos4_pm_data = { + .wkup_irq = exynos4_wkup_irq, + .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), + .release_ret_regs = exynos_release_ret_regs, + .pm_suspend = exynos_pm_suspend, + .pm_resume = exynos_pm_resume, + .pm_prepare = exynos_pm_prepare, + .cpu_suspend = exynos_cpu_suspend, +}; + +static const struct exynos_pm_data exynos5250_pm_data = { + .wkup_irq = exynos5250_wkup_irq, + .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), + .release_ret_regs = exynos_release_ret_regs, + .extra_save = exynos5_sys_save, + .num_extra_save = ARRAY_SIZE(exynos5_sys_save), + .pm_suspend = exynos_pm_suspend, + .pm_resume = exynos_pm_resume, + .pm_prepare = exynos_pm_prepare, + .cpu_suspend = exynos_cpu_suspend, +}; + +static struct of_device_id exynos_pmu_of_device_ids[] = { + { + .compatible = "samsung,exynos4210-pmu", + .data = &exynos4_pm_data, + }, { + .compatible = "samsung,exynos4212-pmu", + .data = &exynos4_pm_data, + }, { + .compatible = "samsung,exynos4412-pmu", + .data = &exynos4_pm_data, + }, { + .compatible = "samsung,exynos5250-pmu", + .data = &exynos5250_pm_data, + }, + { /*sentinel*/ }, +}; + +static struct syscore_ops exynos_pm_syscore_ops; + void __init exynos_pm_init(void) { + const struct of_device_id *match; u32 tmp; + of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match); + if (!match) { + pr_err("Failed to find PMU node\n"); + return; + } + pm_data = (struct exynos_pm_data *) match->data; + /* Platform-specific GIC callback */ gic_arch_extn.irq_set_wake = exynos_irq_set_wake; /* All wakeup disable */ tmp = pmu_raw_readl(S5P_WAKEUP_MASK); - tmp |= ((0xFF << 8) | (0x1F << 1)); + tmp |= pm_data->wake_disable_mask; pmu_raw_writel(tmp, S5P_WAKEUP_MASK); + exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; + exynos_pm_syscore_ops.resume = pm_data->pm_resume; + register_syscore_ops(&exynos_pm_syscore_ops); suspend_set_ops(&exynos_suspend_ops); } diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 96a1569262b5..30c03017aa6a 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -21,6 +21,7 @@ #define S5P_USE_STANDBY_WFI0 (1 << 16) #define S5P_USE_STANDBY_WFE0 (1 << 24) +#define EXYNOS_WAKEUP_FROM_LOWPWR (1 << 28) #define EXYNOS_SWRESET 0x0400 #define EXYNOS5440_SWRESET 0x00C4 -- cgit v1.2.3 From 9c261f89a30010a33c15e6b7cfc7c79ae6bea653 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 24 Sep 2014 01:24:35 +0900 Subject: ARM: firmware: Introduce suspend and resume operations This patch extends the firmware_ops structure with two new callbacks: .suspend() and .resume(). The former is intended to ask the firmware to save all its volatile state and suspend the system, without returning back to the kernel in between. The latter is to be called early by very low level platform suspend code after waking up to restore low level hardware state, which can't be restored in non-secure mode. While at it, outdated version of the structure is removed from the documentation and replaced with a reference to the header file. Signed-off-by: Tomasz Figa Acked-by: Alexandre Courbot Signed-off-by: Kukjin Kim --- Documentation/arm/firmware.txt | 28 +++++----------------------- arch/arm/include/asm/firmware.h | 8 ++++++++ 2 files changed, 13 insertions(+), 23 deletions(-) diff --git a/Documentation/arm/firmware.txt b/Documentation/arm/firmware.txt index c2e468fe7b0b..da6713adac8a 100644 --- a/Documentation/arm/firmware.txt +++ b/Documentation/arm/firmware.txt @@ -7,32 +7,14 @@ world, which changes the way some things have to be initialized. This makes a need to provide an interface for such platforms to specify available firmware operations and call them when needed. -Firmware operations can be specified using struct firmware_ops - - struct firmware_ops { - /* - * Enters CPU idle mode - */ - int (*do_idle)(void); - /* - * Sets boot address of specified physical CPU - */ - int (*set_cpu_boot_addr)(int cpu, unsigned long boot_addr); - /* - * Boots specified physical CPU - */ - int (*cpu_boot)(int cpu); - /* - * Initializes L2 cache - */ - int (*l2x0_init)(void); - }; - -and then registered with register_firmware_ops function +Firmware operations can be specified by filling in a struct firmware_ops +with appropriate callbacks and then registering it with register_firmware_ops() +function. void register_firmware_ops(const struct firmware_ops *ops) -the ops pointer must be non-NULL. +The ops pointer must be non-NULL. More information about struct firmware_ops +and its members can be found in arch/arm/include/asm/firmware.h header. There is a default, empty set of operations provided, so there is no need to set anything if platform does not require firmware operations. diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h index 2c9f10df7568..5904f59b0409 100644 --- a/arch/arm/include/asm/firmware.h +++ b/arch/arm/include/asm/firmware.h @@ -41,6 +41,14 @@ struct firmware_ops { * Initializes L2 cache */ int (*l2x0_init)(void); + /* + * Enter system-wide suspend. + */ + int (*suspend)(void); + /* + * Restore state of privileged hardware after system-wide suspend. + */ + int (*resume)(void); }; /* Global pointer for current firmware_ops structure, can't be NULL. */ -- cgit v1.2.3 From 2b9d9c321b5900c7ce82110a81cf3827ca9b33c6 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 24 Sep 2014 01:24:39 +0900 Subject: ARM: EXYNOS: Add support for firmware-assisted suspend/resume On a numer of Exynos-based boards Linux kernel is running in non-secure mode under a secure firmware. This means that certain operations need to be handled in special way, with firmware assistance. System-wide suspend/resume is an example of such operations. This patch adds support for firmware-assisted suspend/resume by leveraging recently introduced suspend and resume firmware operations and modifying existing suspend/resume paths to account for presence of secure firmware. Signed-off-by: Tomasz Figa [kgene.kim@samsung.com: rebased] Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/Makefile | 1 + arch/arm/mach-exynos/common.h | 4 ++++ arch/arm/mach-exynos/firmware.c | 45 +++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-exynos/pm.c | 16 ++++++++++----- arch/arm/mach-exynos/sleep.S | 28 +++++++++++++++++++++++++ arch/arm/mach-exynos/smc.h | 4 ++++ 6 files changed, 93 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 27ae6144679c..45bef21a3b66 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -21,6 +21,7 @@ CFLAGS_hotplug.o += -march=armv7-a plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec) obj-$(CONFIG_EXYNOS5420_MCPM) += mcpm-exynos.o CFLAGS_mcpm-exynos.o += -march=armv7-a diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 47b904b3b973..c218200f8544 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -111,6 +111,9 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) #define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ soc_is_exynos5420() || soc_is_exynos5800()) +extern u32 cp15_save_diag; +extern u32 cp15_save_power; + extern void __iomem *sysram_ns_base_addr; extern void __iomem *sysram_base_addr; extern void __iomem *pmu_base_addr; @@ -127,6 +130,7 @@ static inline void exynos_pm_init(void) {} #endif extern void exynos_cpu_resume(void); +extern void exynos_cpu_resume_ns(void); extern struct smp_operations exynos_smp_ops; diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index e8797bb78871..f5e626d55951 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -14,13 +14,20 @@ #include #include +#include +#include #include +#include #include #include "common.h" #include "smc.h" +#define EXYNOS_SLEEP_MAGIC 0x00000bad +#define EXYNOS_BOOT_ADDR 0x8 +#define EXYNOS_BOOT_FLAG 0xc + static int exynos_do_idle(void) { exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); @@ -69,10 +76,48 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) return 0; } +static int exynos_cpu_suspend(unsigned long arg) +{ + flush_cache_all(); + outer_flush_all(); + + exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); + + pr_info("Failed to suspend the system\n"); + writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); + return 1; +} + +static int exynos_suspend(void) +{ + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { + /* Save Power control and Diagnostic registers */ + asm ("mrc p15, 0, %0, c15, c0, 0\n" + "mrc p15, 0, %1, c15, c0, 1\n" + : "=r" (cp15_save_power), "=r" (cp15_save_diag) + : : "cc"); + } + + writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); + writel(virt_to_phys(exynos_cpu_resume_ns), + sysram_ns_base_addr + EXYNOS_BOOT_ADDR); + + return cpu_suspend(0, exynos_cpu_suspend); +} + +static int exynos_resume(void) +{ + writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); + + return 0; +} + static const struct firmware_ops exynos_firmware_ops = { .do_idle = exynos_do_idle, .set_cpu_boot_addr = exynos_set_cpu_boot_addr, .cpu_boot = exynos_cpu_boot, + .suspend = exynos_suspend, + .resume = exynos_resume, }; void __init exynos_firmware_init(void) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 16b23d156eec..047ac302835d 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -331,12 +332,11 @@ static void exynos_pm_release_retention(void) static void exynos_pm_resume(void) { + u32 cpuid = read_cpuid_part(); + if (exynos_pm_central_resume()) goto early_wakeup; - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) - exynos_cpu_restore_register(); - /* For release retention */ exynos_pm_release_retention(); @@ -346,9 +346,13 @@ static void exynos_pm_resume(void) s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) + if (cpuid == ARM_CPU_PART_CORTEX_A9) scu_enable(S5P_VA_SCU); + if (call_firmware_op(resume) == -ENOSYS + && cpuid == ARM_CPU_PART_CORTEX_A9) + exynos_cpu_restore_register(); + early_wakeup: /* Clear SLEEP mode set in INFORM1 */ @@ -383,7 +387,9 @@ static int exynos_suspend_enter(suspend_state_t state) flush_cache_all(); s3c_pm_check_store(); - ret = cpu_suspend(0, pm_data->cpu_suspend); + ret = call_firmware_op(suspend); + if (ret == -ENOSYS) + ret = cpu_suspend(0, pm_data->cpu_suspend); if (ret) return ret; diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index 108a45f4bb62..e3c373082bbe 100644 --- a/arch/arm/mach-exynos/sleep.S +++ b/arch/arm/mach-exynos/sleep.S @@ -16,6 +16,7 @@ */ #include +#include "smc.h" #define CPU_MASK 0xff0ffff0 #define CPU_CORTEX_A9 0x410fc090 @@ -55,3 +56,30 @@ ENTRY(exynos_cpu_resume) #endif b cpu_resume ENDPROC(exynos_cpu_resume) + + .align + +ENTRY(exynos_cpu_resume_ns) + mrc p15, 0, r0, c0, c0, 0 + ldr r1, =CPU_MASK + and r0, r0, r1 + ldr r1, =CPU_CORTEX_A9 + cmp r0, r1 + bne skip_cp15 + + adr r0, cp15_save_power + ldr r1, [r0] + adr r0, cp15_save_diag + ldr r2, [r0] + mov r0, #SMC_CMD_C15RESUME + dsb + smc #0 +skip_cp15: + b cpu_resume +ENDPROC(exynos_cpu_resume_ns) + .globl cp15_save_diag +cp15_save_diag: + .long 0 @ cp15 diagnostic + .globl cp15_save_power +cp15_save_power: + .long 0 @ cp15 power control diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h index 13a1dc8ecbf2..f7b82f9c1e21 100644 --- a/arch/arm/mach-exynos/smc.h +++ b/arch/arm/mach-exynos/smc.h @@ -26,6 +26,10 @@ #define SMC_CMD_L2X0INVALL (-24) #define SMC_CMD_L2X0DEBUG (-25) +#ifndef __ASSEMBLY__ + extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3); +#endif /* __ASSEMBLY__ */ + #endif -- cgit v1.2.3 From 134abc297e43438cdb47f30fc673680b16bc6339 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Thu, 25 Sep 2014 17:59:40 +0900 Subject: ARM: EXYNOS: replace EXYNOS_BOOT_VECTOR_* macros by static inlines Replace EXYNOS_BOOT_VECTOR_ADDR and EXYNOS_BOOT_VECTOR_FLAG macros by exynos_boot_vector_addr() and exynos_boot_vector_flag() static inlines. This patch shouldn't cause any functionality changes. Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Kyungmin Park Acked-by: Daniel Lezcano Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/pm.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 047ac302835d..3407fc162449 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -128,16 +128,23 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) return -ENOENT; } -#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ - pmu_base_addr + S5P_INFORM7 : \ - (samsung_rev() == EXYNOS4210_REV_1_0 ? \ - (sysram_base_addr + 0x24) : \ - pmu_base_addr + S5P_INFORM0)) -#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ - pmu_base_addr + S5P_INFORM6 : \ - (samsung_rev() == EXYNOS4210_REV_1_0 ? \ - (sysram_base_addr + 0x20) : \ - pmu_base_addr + S5P_INFORM1)) +static inline void __iomem *exynos_boot_vector_addr(void) +{ + if (samsung_rev() == EXYNOS4210_REV_1_1) + return pmu_base_addr + S5P_INFORM7; + else if (samsung_rev() == EXYNOS4210_REV_1_0) + return sysram_base_addr + 0x24; + return pmu_base_addr + S5P_INFORM0; +} + +static inline void __iomem *exynos_boot_vector_flag(void) +{ + if (samsung_rev() == EXYNOS4210_REV_1_1) + return pmu_base_addr + S5P_INFORM6; + else if (samsung_rev() == EXYNOS4210_REV_1_0) + return sysram_base_addr + 0x20; + return pmu_base_addr + S5P_INFORM1; +} #define S5P_CHECK_AFTR 0xFCBA0D10 #define S5P_CHECK_SLEEP 0x00000BAD @@ -222,8 +229,9 @@ static void exynos_set_wakeupmask(long mask) static void exynos_cpu_set_boot_vector(long flags) { - __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR); - __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG); + __raw_writel(virt_to_phys(exynos_cpu_resume), + exynos_boot_vector_addr()); + __raw_writel(flags, exynos_boot_vector_flag()); } static int exynos_aftr_finisher(unsigned long flags) -- cgit v1.2.3 From 0b7778a801fde0eacd5ee08242290273507e60a2 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Thu, 25 Sep 2014 17:59:41 +0900 Subject: ARM: firmware: add AFTR mode support to firmware do_idle method On some platforms (i.e. EXYNOS ones) more than one idle mode is available and we need to distinguish them in firmware do_idle method. Add mode parameter to do_idle firmware method and AFTR mode support to EXYNOS do_idle implementation. This change is a preparation for adding secure firmware support to EXYNOS cpuidle driver. This patch shouldn't cause any functionality changes. Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Kyungmin Park Acked-by: Thierry Reding Signed-off-by: Kukjin Kim --- arch/arm/include/asm/firmware.h | 2 +- arch/arm/mach-exynos/common.h | 5 +++++ arch/arm/mach-exynos/firmware.c | 10 ++++++++-- arch/arm/mach-tegra/cpuidle-tegra114.c | 2 +- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h index 5904f59b0409..89aefe10d66b 100644 --- a/arch/arm/include/asm/firmware.h +++ b/arch/arm/include/asm/firmware.h @@ -28,7 +28,7 @@ struct firmware_ops { /* * Enters CPU idle mode */ - int (*do_idle)(void); + int (*do_idle)(unsigned long mode); /* * Sets boot address of specified physical CPU */ diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index c218200f8544..2d830df0f647 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -119,6 +119,11 @@ extern void __iomem *sysram_base_addr; extern void __iomem *pmu_base_addr; void exynos_sysram_init(void); +enum { + FW_DO_IDLE_SLEEP, + FW_DO_IDLE_AFTR, +}; + void exynos_firmware_init(void); extern u32 exynos_get_eint_wake_mask(void); diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index f5e626d55951..e57b7c3039a2 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -28,9 +28,15 @@ #define EXYNOS_BOOT_ADDR 0x8 #define EXYNOS_BOOT_FLAG 0xc -static int exynos_do_idle(void) +static int exynos_do_idle(unsigned long mode) { - exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); + switch (mode) { + case FW_DO_IDLE_AFTR: + exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0); + break; + case FW_DO_IDLE_SLEEP: + exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); + } return 0; } diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index e3ebdce3e71f..425b6c8f0cb0 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c @@ -49,7 +49,7 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev, call_firmware_op(prepare_idle); /* Do suspend by ourselves if the firmware does not implement it */ - if (call_firmware_op(do_idle) == -ENOSYS) + if (call_firmware_op(do_idle, 0) == -ENOSYS) cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); -- cgit v1.2.3 From a135e20185fe6f0258fa6837455043f3063601d8 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Thu, 25 Sep 2014 17:59:41 +0900 Subject: ARM: EXYNOS: add secure firmware support to AFTR mode code * Move cp15 registers saving to exynos_save_cp15() helper and add additional helper usage to do_idle firmware method. * Use resume firmware method instead of exynos_cpu_restore_register() and skip exynos_cpu_save_register() on boards with secure firmware enabled. * Use sysram_ns_base_addr + 0x24/0x20 addresses instead of the default ones used by exynos_cpu_set_boot_vector() on boards with secure firmware enabled. * Use do_idle firmware method instead of cpu_do_idle() on boards with secure firmware enabled. Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/firmware.c | 24 +++++++++++++++++------- arch/arm/mach-exynos/pm.c | 17 ++++++++++++----- 2 files changed, 29 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index e57b7c3039a2..2c5bc6bfcbdf 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -25,13 +25,28 @@ #include "smc.h" #define EXYNOS_SLEEP_MAGIC 0x00000bad +#define EXYNOS_AFTR_MAGIC 0xfcba0d10 #define EXYNOS_BOOT_ADDR 0x8 #define EXYNOS_BOOT_FLAG 0xc +static void exynos_save_cp15(void) +{ + /* Save Power control and Diagnostic registers */ + asm ("mrc p15, 0, %0, c15, c0, 0\n" + "mrc p15, 0, %1, c15, c0, 1\n" + : "=r" (cp15_save_power), "=r" (cp15_save_diag) + : : "cc"); +} + static int exynos_do_idle(unsigned long mode) { switch (mode) { case FW_DO_IDLE_AFTR: + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) + exynos_save_cp15(); + __raw_writel(virt_to_phys(exynos_cpu_resume_ns), + sysram_ns_base_addr + 0x24); + __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0); break; case FW_DO_IDLE_SLEEP: @@ -96,13 +111,8 @@ static int exynos_cpu_suspend(unsigned long arg) static int exynos_suspend(void) { - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { - /* Save Power control and Diagnostic registers */ - asm ("mrc p15, 0, %0, c15, c0, 0\n" - "mrc p15, 0, %1, c15, c0, 1\n" - : "=r" (cp15_save_power), "=r" (cp15_save_diag) - : : "cc"); - } + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) + exynos_save_cp15(); writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); writel(virt_to_phys(exynos_cpu_resume_ns), diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 3407fc162449..6796fce923e2 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -236,11 +236,19 @@ static void exynos_cpu_set_boot_vector(long flags) static int exynos_aftr_finisher(unsigned long flags) { + int ret; + exynos_set_wakeupmask(0x0000ff3e); - exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); /* Set value of power down register for aftr mode */ exynos_sys_powerdown_conf(SYS_AFTR); - cpu_do_idle(); + + ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR); + if (ret == -ENOSYS) { + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) + exynos_cpu_save_register(); + exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); + cpu_do_idle(); + } return 1; } @@ -250,14 +258,13 @@ void exynos_enter_aftr(void) cpu_pm_enter(); exynos_pm_central_suspend(); - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) - exynos_cpu_save_register(); cpu_suspend(0, exynos_aftr_finisher); if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { scu_enable(S5P_VA_SCU); - exynos_cpu_restore_register(); + if (call_firmware_op(resume) == -ENOSYS) + exynos_cpu_restore_register(); } exynos_pm_central_resume(); -- cgit v1.2.3 From c2dd114d24865662a6d7381b101741fc898a0059 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Thu, 25 Sep 2014 17:59:41 +0900 Subject: ARM: EXYNOS: fix register setup for AFTR mode code Add S5P_CENTRAL_SEQ_OPTION register setup to cpuidle AFTR mode code by moving the relevant code from exynos_pm_suspend() (used only by suspend) to exynos_pm_central_suspend() (used by both suspend and AFTR). Without this setup AFTR mode doesn't show any benefit over WFI one (at least on Exynos4412 SoC). When this setup is applied AFTR mode reduces power consumption by ~12% (as measured on Trats2 board). This change is a preparation for adding secure firmware support to EXYNOS cpuidle driver. Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/pm.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 6796fce923e2..16c5c3206f14 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -196,6 +196,10 @@ static void exynos_pm_central_suspend(void) tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); tmp &= ~S5P_CENTRAL_LOWPWR_CFG; pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + + /* Setting SEQ_OPTION register */ + pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, + S5P_CENTRAL_SEQ_OPTION); } static int exynos_pm_central_resume(void) @@ -321,15 +325,8 @@ static void exynos_pm_prepare(void) static int exynos_pm_suspend(void) { - unsigned long tmp; - exynos_pm_central_suspend(); - /* Setting SEQ_OPTION register */ - - tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); - pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) exynos_cpu_save_register(); -- cgit v1.2.3 From 42d5dc37866610448453859bf2c4be57fce3834c Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Thu, 25 Sep 2014 17:59:41 +0900 Subject: ARM: EXYNOS: allow driver usage on Exynos4x12 SoCs Register cpuidle platform device on Exynos4x12 SoCs allowing EXYNOS cpuidle driver usage on these SoCs. AFTR mode reduces power consumption on Trats2 board (Exynos4412 SoC with secure firmware enabled) by ~12% when EXYNOS cpuidle driver is enabled (in both cases the default exynos_defconfig config is used and CPU1-3 are offlined). Currently Exynos4412 SoC support is limited to Trats2 board. Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/exynos.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 6b283eb3202e..a487e59555da 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -318,7 +318,10 @@ static void __init exynos_dt_machine_init(void) exynos_sysram_init(); if (of_machine_is_compatible("samsung,exynos4210") || - of_machine_is_compatible("samsung,exynos5250")) + of_machine_is_compatible("samsung,exynos4212") || + (of_machine_is_compatible("samsung,exynos4412") && + of_machine_is_compatible("samsung,trats2")) || + of_machine_is_compatible("samsung,exynos5250")) platform_device_register(&exynos_cpuidle); platform_device_register_simple("exynos-cpufreq", -1, NULL, 0); -- cgit v1.2.3 From 0d713cf1a6286aae6a12affab0887dbe2a4fbb83 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Thu, 25 Sep 2014 18:02:45 +0900 Subject: ARM: EXYNOS: Fix build with PM_SLEEP=n and ARM_EXYNOS_CPUIDLE=y Fix building of exynos_defconfig with CONFIG_PM_SLEEP disabled and CONFIG_ARM_EXYNOS_CPUIDLE enabled by: * adding EXYNOS_CPU_SUSPEND config option * always building sleep.o * building pm.o if EXYNOS_CPU_SUSPEND is enabled * moving suspend specific code from pm.c to suspend.c * enabling pm-common.o build also for EXYNOS_CPU_SUSPEND option [ Please note that there are no changes in the code moved from pm.c to suspend.c except making few functions non-static and cleaning up includes. ] Also while at it update Copyright dates. The build error messages: drivers/built-in.o: In function `exynos_enter_core0_aftr': /home/bzolnier/linux/drivers/cpuidle/cpuidle-exynos.c:36: undefined reference to `cpu_suspend' arch/arm/mach-exynos/built-in.o:(.data+0x74): undefined reference to `exynos_enter_aftr' make: *** [vmlinux] Error 1 This patch has been tested on Exynos4210 based Origen board. Signed-off-by: Bartlomiej Zolnierkiewicz Acked-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/Kconfig | 5 + arch/arm/mach-exynos/Makefile | 5 +- arch/arm/mach-exynos/common.h | 4 + arch/arm/mach-exynos/pm.c | 338 +------------------------------------- arch/arm/mach-exynos/suspend.c | 356 +++++++++++++++++++++++++++++++++++++++++ arch/arm/plat-samsung/Makefile | 1 + 6 files changed, 374 insertions(+), 335 deletions(-) create mode 100644 arch/arm/mach-exynos/suspend.c diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 2d0240f241b8..46f3c0d0d01f 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -123,4 +123,9 @@ config EXYNOS5420_MCPM This is needed to provide CPU and cluster power management on Exynos5420 implementing big.LITTLE. +config EXYNOS_CPU_SUSPEND + bool + select ARM_CPU_SUSPEND + default PM_SLEEP || ARM_EXYNOS_CPUIDLE + endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 45bef21a3b66..3d680f2a5520 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -9,9 +9,10 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree) # Core -obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o +obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o sleep.o -obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o +obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o +obj-$(CONFIG_PM_SLEEP) += suspend.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 2d830df0f647..ef95cb1cc00a 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -164,6 +164,10 @@ extern int exynos_cpu_power_state(int cpu); extern void exynos_cluster_power_down(int cluster); extern void exynos_cluster_power_up(int cluster); extern int exynos_cluster_power_state(int cluster); +extern void exynos_cpu_save_register(void); +extern void exynos_cpu_restore_register(void); +extern void exynos_pm_central_suspend(void); +extern int exynos_pm_central_resume(void); extern void exynos_enter_aftr(void); extern void s5p_init_cpu(void __iomem *cpuid_addr); diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 16c5c3206f14..4f10fa6bfe10 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. + * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. * http://www.samsung.com * * EXYNOS - Power Management support @@ -15,119 +15,20 @@ #include #include -#include #include #include -#include #include -#include -#include #include -#include #include #include #include -#include - -#include #include "common.h" #include "regs-pmu.h" #include "regs-sys.h" -#define REG_TABLE_END (-1U) - -/** - * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping - * @hwirq: Hardware IRQ signal of the GIC - * @mask: Mask in PMU wake-up mask register - */ -struct exynos_wkup_irq { - unsigned int hwirq; - u32 mask; -}; - -static struct sleep_save exynos5_sys_save[] = { - SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), -}; - -static struct sleep_save exynos_core_save[] = { - /* SROM side */ - SAVE_ITEM(S5P_SROM_BW), - SAVE_ITEM(S5P_SROM_BC0), - SAVE_ITEM(S5P_SROM_BC1), - SAVE_ITEM(S5P_SROM_BC2), - SAVE_ITEM(S5P_SROM_BC3), -}; - -struct exynos_pm_data { - const struct exynos_wkup_irq *wkup_irq; - struct sleep_save *extra_save; - int num_extra_save; - unsigned int wake_disable_mask; - unsigned int *release_ret_regs; - - void (*pm_prepare)(void); - void (*pm_resume)(void); - int (*pm_suspend)(void); - int (*cpu_suspend)(unsigned long); -}; - -struct exynos_pm_data *pm_data; - -/* - * GIC wake-up support - */ - -static u32 exynos_irqwake_intmask = 0xffffffff; - -static const struct exynos_wkup_irq exynos4_wkup_irq[] = { - { 76, BIT(1) }, /* RTC alarm */ - { 77, BIT(2) }, /* RTC tick */ - { /* sentinel */ }, -}; - -static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { - { 75, BIT(1) }, /* RTC alarm */ - { 76, BIT(2) }, /* RTC tick */ - { /* sentinel */ }, -}; - -unsigned int exynos_release_ret_regs[] = { - S5P_PAD_RET_MAUDIO_OPTION, - S5P_PAD_RET_GPIO_OPTION, - S5P_PAD_RET_UART_OPTION, - S5P_PAD_RET_MMCA_OPTION, - S5P_PAD_RET_MMCB_OPTION, - S5P_PAD_RET_EBIA_OPTION, - S5P_PAD_RET_EBIB_OPTION, - REG_TABLE_END, -}; - -static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) -{ - const struct exynos_wkup_irq *wkup_irq; - - if (!pm_data->wkup_irq) - return -ENOENT; - wkup_irq = pm_data->wkup_irq; - - while (wkup_irq->mask) { - if (wkup_irq->hwirq == data->hwirq) { - if (!state) - exynos_irqwake_intmask |= wkup_irq->mask; - else - exynos_irqwake_intmask &= ~wkup_irq->mask; - return 0; - } - ++wkup_irq; - } - - return -ENOENT; -} - static inline void __iomem *exynos_boot_vector_addr(void) { if (samsung_rev() == EXYNOS4210_REV_1_1) @@ -147,12 +48,11 @@ static inline void __iomem *exynos_boot_vector_flag(void) } #define S5P_CHECK_AFTR 0xFCBA0D10 -#define S5P_CHECK_SLEEP 0x00000BAD /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; -static void exynos_cpu_save_register(void) +void exynos_cpu_save_register(void) { unsigned long tmp; @@ -169,7 +69,7 @@ static void exynos_cpu_save_register(void) save_arm_register[1] = tmp; } -static void exynos_cpu_restore_register(void) +void exynos_cpu_restore_register(void) { unsigned long tmp; @@ -188,7 +88,7 @@ static void exynos_cpu_restore_register(void) : "cc"); } -static void exynos_pm_central_suspend(void) +void exynos_pm_central_suspend(void) { unsigned long tmp; @@ -202,7 +102,7 @@ static void exynos_pm_central_suspend(void) S5P_CENTRAL_SEQ_OPTION); } -static int exynos_pm_central_resume(void) +int exynos_pm_central_resume(void) { unsigned long tmp; @@ -275,231 +175,3 @@ void exynos_enter_aftr(void) cpu_pm_exit(); } - -static int exynos_cpu_do_idle(void) -{ - /* issue the standby signal into the pm unit. */ - cpu_do_idle(); - - pr_info("Failed to suspend the system\n"); - return 1; /* Aborting suspend */ -} - -static int exynos_cpu_suspend(unsigned long arg) -{ - flush_cache_all(); - outer_flush_all(); - return exynos_cpu_do_idle(); -} - -static void exynos_pm_set_wakeup_mask(void) -{ - /* Set wake-up mask registers */ - pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); - pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); -} - -static void exynos_pm_enter_sleep_mode(void) -{ - /* Set value of power down register for sleep mode */ - exynos_sys_powerdown_conf(SYS_SLEEP); - pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); - - /* ensure at least INFORM0 has the resume address */ - pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); -} - -static void exynos_pm_prepare(void) -{ - /* Set wake-up mask registers */ - exynos_pm_set_wakeup_mask(); - - s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - - if (pm_data->extra_save) - s3c_pm_do_save(pm_data->extra_save, - pm_data->num_extra_save); - - exynos_pm_enter_sleep_mode(); -} - -static int exynos_pm_suspend(void) -{ - exynos_pm_central_suspend(); - - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) - exynos_cpu_save_register(); - - return 0; -} - -static void exynos_pm_release_retention(void) -{ - unsigned int i; - - for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) - pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, - pm_data->release_ret_regs[i]); -} - -static void exynos_pm_resume(void) -{ - u32 cpuid = read_cpuid_part(); - - if (exynos_pm_central_resume()) - goto early_wakeup; - - /* For release retention */ - exynos_pm_release_retention(); - - if (pm_data->extra_save) - s3c_pm_do_restore_core(pm_data->extra_save, - pm_data->num_extra_save); - - s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - - if (cpuid == ARM_CPU_PART_CORTEX_A9) - scu_enable(S5P_VA_SCU); - - if (call_firmware_op(resume) == -ENOSYS - && cpuid == ARM_CPU_PART_CORTEX_A9) - exynos_cpu_restore_register(); - -early_wakeup: - - /* Clear SLEEP mode set in INFORM1 */ - pmu_raw_writel(0x0, S5P_INFORM1); -} - -/* - * Suspend Ops - */ - -static int exynos_suspend_enter(suspend_state_t state) -{ - int ret; - - s3c_pm_debug_init(); - - S3C_PMDBG("%s: suspending the system...\n", __func__); - - S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, - exynos_irqwake_intmask, exynos_get_eint_wake_mask()); - - if (exynos_irqwake_intmask == -1U - && exynos_get_eint_wake_mask() == -1U) { - pr_err("%s: No wake-up sources!\n", __func__); - pr_err("%s: Aborting sleep\n", __func__); - return -EINVAL; - } - - s3c_pm_save_uarts(); - if (pm_data->pm_prepare) - pm_data->pm_prepare(); - flush_cache_all(); - s3c_pm_check_store(); - - ret = call_firmware_op(suspend); - if (ret == -ENOSYS) - ret = cpu_suspend(0, pm_data->cpu_suspend); - if (ret) - return ret; - - s3c_pm_restore_uarts(); - - S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, - pmu_raw_readl(S5P_WAKEUP_STAT)); - - s3c_pm_check_restore(); - - S3C_PMDBG("%s: resuming the system...\n", __func__); - - return 0; -} - -static int exynos_suspend_prepare(void) -{ - s3c_pm_check_prepare(); - - return 0; -} - -static void exynos_suspend_finish(void) -{ - s3c_pm_check_cleanup(); -} - -static const struct platform_suspend_ops exynos_suspend_ops = { - .enter = exynos_suspend_enter, - .prepare = exynos_suspend_prepare, - .finish = exynos_suspend_finish, - .valid = suspend_valid_only_mem, -}; - -static const struct exynos_pm_data exynos4_pm_data = { - .wkup_irq = exynos4_wkup_irq, - .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos_release_ret_regs, - .pm_suspend = exynos_pm_suspend, - .pm_resume = exynos_pm_resume, - .pm_prepare = exynos_pm_prepare, - .cpu_suspend = exynos_cpu_suspend, -}; - -static const struct exynos_pm_data exynos5250_pm_data = { - .wkup_irq = exynos5250_wkup_irq, - .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos_release_ret_regs, - .extra_save = exynos5_sys_save, - .num_extra_save = ARRAY_SIZE(exynos5_sys_save), - .pm_suspend = exynos_pm_suspend, - .pm_resume = exynos_pm_resume, - .pm_prepare = exynos_pm_prepare, - .cpu_suspend = exynos_cpu_suspend, -}; - -static struct of_device_id exynos_pmu_of_device_ids[] = { - { - .compatible = "samsung,exynos4210-pmu", - .data = &exynos4_pm_data, - }, { - .compatible = "samsung,exynos4212-pmu", - .data = &exynos4_pm_data, - }, { - .compatible = "samsung,exynos4412-pmu", - .data = &exynos4_pm_data, - }, { - .compatible = "samsung,exynos5250-pmu", - .data = &exynos5250_pm_data, - }, - { /*sentinel*/ }, -}; - -static struct syscore_ops exynos_pm_syscore_ops; - -void __init exynos_pm_init(void) -{ - const struct of_device_id *match; - u32 tmp; - - of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match); - if (!match) { - pr_err("Failed to find PMU node\n"); - return; - } - pm_data = (struct exynos_pm_data *) match->data; - - /* Platform-specific GIC callback */ - gic_arch_extn.irq_set_wake = exynos_irq_set_wake; - - /* All wakeup disable */ - tmp = pmu_raw_readl(S5P_WAKEUP_MASK); - tmp |= pm_data->wake_disable_mask; - pmu_raw_writel(tmp, S5P_WAKEUP_MASK); - - exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; - exynos_pm_syscore_ops.resume = pm_data->pm_resume; - - register_syscore_ops(&exynos_pm_syscore_ops); - suspend_set_ops(&exynos_suspend_ops); -} diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c new file mode 100644 index 000000000000..f5d9773066eb --- /dev/null +++ b/arch/arm/mach-exynos/suspend.c @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - Suspend support + * + * Based on arch/arm/mach-s3c2410/pm.c + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "regs-pmu.h" +#include "regs-sys.h" + +#define S5P_CHECK_SLEEP 0x00000BAD + +#define REG_TABLE_END (-1U) + +/** + * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping + * @hwirq: Hardware IRQ signal of the GIC + * @mask: Mask in PMU wake-up mask register + */ +struct exynos_wkup_irq { + unsigned int hwirq; + u32 mask; +}; + +static struct sleep_save exynos5_sys_save[] = { + SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), +}; + +static struct sleep_save exynos_core_save[] = { + /* SROM side */ + SAVE_ITEM(S5P_SROM_BW), + SAVE_ITEM(S5P_SROM_BC0), + SAVE_ITEM(S5P_SROM_BC1), + SAVE_ITEM(S5P_SROM_BC2), + SAVE_ITEM(S5P_SROM_BC3), +}; + +struct exynos_pm_data { + const struct exynos_wkup_irq *wkup_irq; + struct sleep_save *extra_save; + int num_extra_save; + unsigned int wake_disable_mask; + unsigned int *release_ret_regs; + + void (*pm_prepare)(void); + void (*pm_resume)(void); + int (*pm_suspend)(void); + int (*cpu_suspend)(unsigned long); +}; + +struct exynos_pm_data *pm_data; + +/* + * GIC wake-up support + */ + +static u32 exynos_irqwake_intmask = 0xffffffff; + +static const struct exynos_wkup_irq exynos4_wkup_irq[] = { + { 76, BIT(1) }, /* RTC alarm */ + { 77, BIT(2) }, /* RTC tick */ + { /* sentinel */ }, +}; + +static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { + { 75, BIT(1) }, /* RTC alarm */ + { 76, BIT(2) }, /* RTC tick */ + { /* sentinel */ }, +}; + +unsigned int exynos_release_ret_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, + REG_TABLE_END, +}; + +static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) +{ + const struct exynos_wkup_irq *wkup_irq; + + if (!pm_data->wkup_irq) + return -ENOENT; + wkup_irq = pm_data->wkup_irq; + + while (wkup_irq->mask) { + if (wkup_irq->hwirq == data->hwirq) { + if (!state) + exynos_irqwake_intmask |= wkup_irq->mask; + else + exynos_irqwake_intmask &= ~wkup_irq->mask; + return 0; + } + ++wkup_irq; + } + + return -ENOENT; +} + +static int exynos_cpu_do_idle(void) +{ + /* issue the standby signal into the pm unit. */ + cpu_do_idle(); + + pr_info("Failed to suspend the system\n"); + return 1; /* Aborting suspend */ +} + +static int exynos_cpu_suspend(unsigned long arg) +{ + flush_cache_all(); + outer_flush_all(); + return exynos_cpu_do_idle(); +} + +static void exynos_pm_set_wakeup_mask(void) +{ + /* Set wake-up mask registers */ + pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); + pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); +} + +static void exynos_pm_enter_sleep_mode(void) +{ + /* Set value of power down register for sleep mode */ + exynos_sys_powerdown_conf(SYS_SLEEP); + pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); + + /* ensure at least INFORM0 has the resume address */ + pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); +} + +static void exynos_pm_prepare(void) +{ + /* Set wake-up mask registers */ + exynos_pm_set_wakeup_mask(); + + s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); + + if (pm_data->extra_save) + s3c_pm_do_save(pm_data->extra_save, + pm_data->num_extra_save); + + exynos_pm_enter_sleep_mode(); +} + +static int exynos_pm_suspend(void) +{ + exynos_pm_central_suspend(); + + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) + exynos_cpu_save_register(); + + return 0; +} + +static void exynos_pm_release_retention(void) +{ + unsigned int i; + + for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) + pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, + pm_data->release_ret_regs[i]); +} + +static void exynos_pm_resume(void) +{ + u32 cpuid = read_cpuid_part(); + + if (exynos_pm_central_resume()) + goto early_wakeup; + + /* For release retention */ + exynos_pm_release_retention(); + + if (pm_data->extra_save) + s3c_pm_do_restore_core(pm_data->extra_save, + pm_data->num_extra_save); + + s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); + + if (cpuid == ARM_CPU_PART_CORTEX_A9) + scu_enable(S5P_VA_SCU); + + if (call_firmware_op(resume) == -ENOSYS + && cpuid == ARM_CPU_PART_CORTEX_A9) + exynos_cpu_restore_register(); + +early_wakeup: + + /* Clear SLEEP mode set in INFORM1 */ + pmu_raw_writel(0x0, S5P_INFORM1); +} + +/* + * Suspend Ops + */ + +static int exynos_suspend_enter(suspend_state_t state) +{ + int ret; + + s3c_pm_debug_init(); + + S3C_PMDBG("%s: suspending the system...\n", __func__); + + S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, + exynos_irqwake_intmask, exynos_get_eint_wake_mask()); + + if (exynos_irqwake_intmask == -1U + && exynos_get