From 2a3a0d5d7962628684bb5cf4be38747dcbb1f35e Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Thu, 21 May 2020 12:38:30 -0400 Subject: drm/amd/display: Add DCN3 DCCG Add programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 22 +++++ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c | 100 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h | 66 ++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index 2205cb0204e7..06daf35bb587 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -76,18 +76,40 @@ type REFCLK_CLOCK_EN;\ type REFCLK_SRC_SEL; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#define DCCG3_REG_FIELD_LIST(type) \ + type PHYASYMCLK_FORCE_EN;\ + type PHYASYMCLK_FORCE_SRC_SEL;\ + type PHYBSYMCLK_FORCE_EN;\ + type PHYBSYMCLK_FORCE_SRC_SEL;\ + type PHYCSYMCLK_FORCE_EN;\ + type PHYCSYMCLK_FORCE_SRC_SEL; +#endif + struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCCG3_REG_FIELD_LIST(uint8_t) +#endif }; struct dccg_mask { DCCG_REG_FIELD_LIST(uint32_t) +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + DCCG3_REG_FIELD_LIST(uint32_t) +#endif }; struct dccg_registers { uint32_t DPPCLK_DTO_CTRL; uint32_t DPPCLK_DTO_PARAM[6]; uint32_t REFCLK_CNTL; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + uint32_t HDMICHARCLK_CLOCK_CNTL[6]; + uint32_t PHYASYMCLK_CLOCK_CNTL; + uint32_t PHYBSYMCLK_CLOCK_CNTL; + uint32_t PHYCSYMCLK_CLOCK_CNTL; +#endif }; struct dcn_dccg { diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c new file mode 100644 index 000000000000..b822a13e40ce --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c @@ -0,0 +1,100 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn30_dccg.h" + +#define TO_DCN_DCCG(dccg)\ + container_of(dccg, struct dcn_dccg, base) + +#define REG(reg) \ + (dccg_dcn->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name + +#define CTX \ + dccg_dcn->base.ctx +#define DC_LOGGER \ + dccg->ctx->logger + + +static const struct dccg_funcs dccg3_funcs = { + .update_dpp_dto = dccg2_update_dpp_dto, + .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .dccg_init = dccg2_init +}; + +struct dccg *dccg3_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask) +{ + struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); + struct dccg *base; + + if (dccg_dcn == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + base = &dccg_dcn->base; + base->ctx = ctx; + base->funcs = &dccg3_funcs; + + dccg_dcn->regs = regs; + dccg_dcn->dccg_shift = dccg_shift; + dccg_dcn->dccg_mask = dccg_mask; + + return &dccg_dcn->base; +} + +struct dccg *dccg30_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask) +{ + struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); + struct dccg *base; + + if (dccg_dcn == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + base = &dccg_dcn->base; + base->ctx = ctx; + base->funcs = &dccg3_funcs; + + dccg_dcn->regs = regs; + dccg_dcn->dccg_shift = dccg_shift; + dccg_dcn->dccg_mask = dccg_mask; + + return &dccg_dcn->base; +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h new file mode 100644 index 000000000000..029dda13a464 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h @@ -0,0 +1,66 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DCN30_DCCG_H__ +#define __DCN30_DCCG_H__ + +#include "dcn20/dcn20_dccg.h" + + +#define DCCG_REG_LIST_DCN3AG() \ + DCCG_COMMON_REG_LIST_DCN_BASE(),\ + SR(PHYASYMCLK_CLOCK_CNTL),\ + SR(PHYBSYMCLK_CLOCK_CNTL),\ + SR(PHYCSYMCLK_CLOCK_CNTL) + + +#define DCCG_REG_LIST_DCN30() \ + DCCG_REG_LIST_DCN2(),\ + SR(PHYASYMCLK_CLOCK_CNTL),\ + SR(PHYBSYMCLK_CLOCK_CNTL),\ + SR(PHYCSYMCLK_CLOCK_CNTL) + +#define DCCG_MASK_SH_LIST_DCN3(mask_sh) \ + DCCG_MASK_SH_LIST_DCN2(mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh) + +struct dccg *dccg3_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask); + +struct dccg *dccg30_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask); + +#endif //__DCN30_DCCG_H__ -- cgit v1.2.3