From c5f80c5f6e2f4961284c29e1c5f3bf42034b7323 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 12 Feb 2016 04:00:42 +0200 Subject: clk: shmobile: r8a7795: Add FCP clocks The parent clock isn't documented in the datasheet, use S2D1 as a best guess for now. Signed-off-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven --- drivers/clk/shmobile/r8a7795-cpg-mssr.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index 1f4b21a79bb9..d971db912396 100644 --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c @@ -147,6 +147,21 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), + DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), + DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1), + DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1), + DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1), + DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1), + DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1), + DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), + DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1), + DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1), + DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), + DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1), + DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1), + DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), + DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), + DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1), DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1), DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1), -- cgit v1.2.3 From 31aeb5a523b0f6c1b7cc4f802e6f925168f7d60d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 12 Feb 2016 04:00:43 +0200 Subject: clk: shmobile: r8a7795: Add LVDS module clock The parent clock hasn't been validated yet. Signed-off-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven --- drivers/clk/shmobile/r8a7795-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index d971db912396..79acdd0ebd68 100644 --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c @@ -179,6 +179,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("du2", 722, R8A7795_CLK_S2D1), DEF_MOD("du1", 723, R8A7795_CLK_S2D1), DEF_MOD("du0", 724, R8A7795_CLK_S2D1), + DEF_MOD("lvds", 727, R8A7795_CLK_S2D1), DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2), -- cgit v1.2.3 From 3092d3b8e56e09ff74d7ef9f1c34a4c358e9f0fe Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 18 Feb 2016 15:16:02 +0100 Subject: clk: shmobile: div6: Fix .recalc_rate() using a stale divisor cpg_div6_clock_set_rate() only programs the new divisor if the clock isn't stopped. If the clock is stopped, it will update the cached divisor value only, which will be programmed into the clock registers when enabling the clock later. However, cpg_div6_clock_recalc_rate() reads the divisor from the clock registers instead of using the cached value, leading to an incorrect result if the clock is currently stopped. Make cpg_div6_clock_recalc_rate() use the cached value to fix this. Reported-by: Ramesh Shanmugasundaram Suggested-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Tested-by: Ramesh Shanmugasundaram --- drivers/clk/shmobile/clk-div6.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c index 999994769450..0627860233cb 100644 --- a/drivers/clk/shmobile/clk-div6.c +++ b/drivers/clk/shmobile/clk-div6.c @@ -82,9 +82,8 @@ static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct div6_clock *clock = to_div6_clock(hw); - unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; - return parent_rate / div; + return parent_rate / clock->div; } static unsigned int cpg_div6_clock_calc_div(unsigned long rate, -- cgit v1.2.3 From 11c6fb783256d016295db241ce5e16f65a4da97c Mon Sep 17 00:00:00 2001 From: Ramesh Shanmugasundaram Date: Thu, 25 Feb 2016 17:05:24 +0000 Subject: clk: shmobile: r8a7795: Add CAN peripheral clock Signed-off-by: Ramesh Shanmugasundaram Signed-off-by: Geert Uytterhoeven --- drivers/clk/shmobile/r8a7795-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index 79acdd0ebd68..958043e7bbac 100644 --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c @@ -192,6 +192,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("gpio2", 910, R8A7795_CLK_CP), DEF_MOD("gpio1", 911, R8A7795_CLK_CP), DEF_MOD("gpio0", 912, R8A7795_CLK_CP), + DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2), DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2), DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2), -- cgit v1.2.3 From 7e00d63199f580bd58cf40f4d48787d0cdd983c0 Mon Sep 17 00:00:00 2001 From: Ramesh Shanmugasundaram Date: Thu, 25 Feb 2016 17:05:25 +0000 Subject: clk: shmobile: r8a7795: Add CANFD clock Signed-off-by: Ramesh Shanmugasundaram Signed-off-by: Geert Uytterhoeven --- drivers/clk/shmobile/r8a7795-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index 958043e7bbac..26af939eb25b 100644 --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c @@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), + DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), }; static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { -- cgit v1.2.3 From a080c8c346d650c84adfd5ff16ac2160b646d73e Mon Sep 17 00:00:00 2001 From: Ramesh Shanmugasundaram Date: Thu, 25 Feb 2016 17:05:26 +0000 Subject: clk: shmobile: r8a7795: Add CAN FD peripheral clock Signed-off-by: Ramesh Shanmugasundaram Signed-off-by: Geert Uytterhoeven --- drivers/clk/shmobile/r8a7795-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index 26af939eb25b..b2198aef5ed4 100644 --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c @@ -193,6 +193,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("gpio2", 910, R8A7795_CLK_CP), DEF_MOD("gpio1", 911, R8A7795_CLK_CP), DEF_MOD("gpio0", 912, R8A7795_CLK_CP), + DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2), -- cgit v1.2.3