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path: root/include/asm-mips/barrier.h
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2007-07-20[MIPS] Make support for weakly ordered LL/SC a config option.Ralf Baechle
None of weakly ordered processor supported in tree need this but it seems like this could change ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-12-04[MIPS] Cleanup memory barriers for weakly ordered systems.Ralf Baechle
Also the R4000 / R4600 LL/SC instructions imply a sync so no explicit sync needed. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>