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2020-07-21mt76: mt7915: avoid memcpy in rxv operationRyder Lee
Avoid memcpy in Rx hot path to slightly improve performance. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt76x2u: enable HC-M7662BU1Lorenzo Bianconi
Enable support for HC-M7662BU1 module on mt76x2u driver Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt76x2: fix pci suspend/resume on mt7612eLorenzo Bianconi
Fix the following mt7612e hw hangs during suspend/resume reported on Dell Vostro 3360 mt76x2e 0000:01:00.0: MCU message 2 (seq 11) timed out mt76x2e 0000:01:00.0: MCU message 30 (seq 12) timed out mt76x2e 0000:01:00.0: MCU message 30 (seq 13) timed out mt76x2e 0000:01:00.0: Firmware Version: 0.0.00 mt76x2e 0000:01:00.0: Build: 1 mt76x2e 0000:01:00.0: Build Time: 201507311614____ mt76x2e 0000:01:00.0: Firmware running! ieee80211 phy0: Hardware restart was requested mt76x2e 0000:01:00.0: MCU message 2 (seq 1) timed out mt76x2e 0000:01:00.0: MCU message 30 (seq 2) timed out mt76x2e 0000:01:00.0: MCU message 30 (seq 3) timed out mt76x2e 0000:01:00.0: Firmware Version: 0.0.00 mt76x2e 0000:01:00.0: Build: 1 mt76x2e 0000:01:00.0: Build Time: 201507311614____ mt76x2e 0000:01:00.0: Firmware running! ieee80211 phy0: Hardware restart was requested mt76x2e 0000:01:00.0: MCU message 31 (seq 5) timed out mt76x2e 0000:01:00.0: MCU message 31 (seq 6) timed out mt76x2e 0000:01:00.0: MCU message 31 (seq 7) timed out mt76x2e 0000:01:00.0: MCU message 31 (seq 8) timed out mt76x2e 0000:01:00.0: MCU message 31 (seq 9) timed out mt76x2e 0000:01:00.0: MCU message 31 (seq 10) timed out mt76x2e 0000:01:00.0: MCU message 31 (seq 11) timed out mt76x2e 0000:01:00.0: Firmware Version: 0.0.00 mt76x2e 0000:01:00.0: Build: 1 mt76x2e 0000:01:00.0: Build Time: 201507311614____ mt76x2e 0000:01:00.0: Firmware running! ieee80211 phy0: Hardware restart was requested ------------[ cut here ]----------- CPU: 3 PID: 11956 Comm: kworker/3:1 Not tainted 5.7.0-pf2 #1 Hardware name: Dell Inc. Vostro 3360/0F5DWF, BIOS A18 09/25/2013 Workqueue: events_freezable ieee80211_restart_work [mac80211] RIP: 0010:ieee80211_reconfig+0x234/0x1700 [mac80211] RSP: 0018:ffffb803c23ffdf0 EFLAGS: 00010286 RAX: 00000000fffffff0 RBX: ffff9595a7564900 RCX: 0000000000000008 RDX: 0000000000000000 RSI: 0000000000000100 RDI: 0000000000000100 RBP: ffff9595a7ec07e0 R08: 0000000000000000 R09: 0000000000000001 R10: 0000000000000001 R11: 0000000000000000 R12: ffff9595a7ec18d0 R13: 00000000ffffffff R14: 0000000000000000 R15: 00000000fffffff0 FS: 0000000000000000(0000) GS:ffff9595af2c0000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000055e56d7de000 CR3: 000000042200a001 CR4: 00000000001706e0 Call Trace: ieee80211_restart_work+0xb7/0xe0 [mac80211] process_one_work+0x1d4/0x3c0 worker_thread+0x228/0x470 ? process_one_work+0x3c0/0x3c0 kthread+0x19c/0x1c0 ? __kthread_init_worker+0x30/0x30 ret_from_fork+0x35/0x40 wlp1s0: Failed check-sdata-in-driver check, flags: 0x0 CPU: 3 PID: 11956 Comm: kworker/3:1 Tainted: G W 5.7.0-pf2 #1 Hardware name: Dell Inc. Vostro 3360/0F5DWF, BIOS A18 09/25/2013 Workqueue: events_freezable ieee80211_restart_work [mac80211] RIP: 0010:drv_remove_interface+0x11f/0x130 [mac80211] RSP: 0018:ffffb803c23ffc80 EFLAGS: 00010282 RAX: 0000000000000000 RBX: ffff9595a7564900 RCX: 0000000000000000 RDX: 0000000000000001 RSI: 0000000000000082 RDI: 00000000ffffffff RBP: ffff9595a7ec1930 R08: 00000000000004b6 R09: 0000000000000001 R10: 0000000000000001 R11: 0000000000006f08 R12: ffff9595a7ec1000 R13: ffff9595a75654b8 R14: ffff9595a7ec0ca0 R15: ffff9595a7ec07e0 FS: 0000000000000000(0000) GS:ffff9595af2c0000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000055e56d7de000 CR3: 000000042200a001 CR4: 00000000001706e0 Call Trace: ieee80211_do_stop+0x5af/0x8c0 [mac80211] ieee80211_stop+0x16/0x20 [mac80211] __dev_close_many+0xaa/0x120 dev_close_many+0xa1/0x2b0 dev_close+0x6d/0x90 cfg80211_shutdown_all_interfaces+0x71/0xd0 [cfg80211] ieee80211_reconfig+0xa2/0x1700 [mac80211] ieee80211_restart_work+0xb7/0xe0 [mac80211] process_one_work+0x1d4/0x3c0 worker_thread+0x228/0x470 ? process_one_work+0x3c0/0x3c0 kthread+0x19c/0x1c0 ? __kthread_init_worker+0x30/0x30 ret_from_fork+0x35/0x40 Fixes: 7bc04215a66b ("mt76: add driver code for MT76x2e") Tested-by: Oleksandr Natalenko <oleksandr@redhat.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7915: update HE capabilitiesRyder Lee
Sync from SDK to update HE capabilities. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: implement testmode supportFelix Fietkau
Supports sending a configurable number of packets with a specific rate and configurable tx power levels / antenna settings, as well as displaying rx statistics. Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: add API for testmode supportFelix Fietkau
This can be used for calibration in the manufacturing process. It supports sending a configurable number of packets with a specific rate and configurable tx power levels / antenna settings. It also supports receiving packets and showing some statistics, including packet counters and detailed RSSI information. It will only be compiled in if CONFIG_NL80211_TESTMODE is enabled Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: vif_mask to struct mt76_phyFelix Fietkau
All drivers use this in pretty much the same way. Moving it to core helps with some checks for the upcoming testmode support Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: use full on-chip memory address for WF_PHY registersFelix Fietkau
Now that the bus access functions can use mapping for accessing full register addresses, use it for WF_PHY registers to keep them constant. Needed for follow-up work on testmode support Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: add support for accessing RF registers via MCUFelix Fietkau
Includes debugfs files for testing it. Will be used for testmode support. Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: add support for accessing mapped registers via bus opsFelix Fietkau
Makes it possible to read/write them via debugfs, similar to mt7603 Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: schedule tx tasklet and sta poll on mac tx freeFelix Fietkau
Unlike on earlier chips, DMA completion on MT7615 does not imply actually having sent out any packets. Since AQL will prevent filling the hardware queues and will only allow more packets to be passed to the driver after tx completion, it makes much more sense to schedule the tx tasklet there. This is also needed for scheduling tx in testmode support Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt76x2e: rename routines in pci.cLorenzo Bianconi
Rely on mt76x2e prefix in mt76x2/pci.c and align to the rest of mt76 code Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7915: overwrite qid for non-bufferable mgmt framesRyder Lee
Overwrite hw queue id for non-bufferable management frames if the hw/fw support always txq (altxq) in order to be in sync with mac txwi code Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7915: use ieee80211_tx_queue_params to avoid open codedRyder Lee
This is easy to add MU EDCA parameters in the future. This patch also fixes a wrong cw_min assignment. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7915: add MU-MIMO supportRyder Lee
Enable MU-MIMO DL/UL and add relative counters in debugfs. Currently MU modules read WTBL first to notify BA changes to other cross modules, so adjust mt7915_mcu_sta_ba() accordingly. Tested-by: Evelyn Tsai <evelyn.tsai@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7915: add a fixed AC queue mappingRyder Lee
In MT7915, hardware queue map is flexible. However, certain firmware modules like MU and U-APSD presume a fixed queue order to adapt some devices that have DMA scheduler with a strict order, so this patch can help in the long run. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: add .set_tsf callbackRyder Lee
It is useful for IBSS Mesh to adjust t_clockdrift. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: add U-APSD support on AP sideLorenzo Bianconi
Introduce U-APSD support in mt76 driver for AP interface Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: rely on register macrosLorenzo Bianconi
For consistency with the rest of the code always rely on defined macros for register access Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: fix include in pci.hMarkus Theil
kernel test robot <lkp@intel.com> found the following issue and Kalle Valo forwarded it to Linux wireless. drivers/net/wireless/mediatek/mt76/pci.c:8:6: warning: no previous prototype for 'mt76_pci_disable_aspm' Fix this by adding the missing include of mt76.h as Kalle suggested. Signed-off-by: Markus Theil <markus.theil@tu-ilmenau.de> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: allow more channels, allowed in ETSI domainMarkus Theil
While looking at the ETSI regulatory domain definitions and a patch, which allows more channels for ath10k, I also checked the channels allowed for mt76. ETSI regulations would possibly allow to add channels 32, 68, 96, 144, 169 and 173. IEEE 802.11-2016 defines no operating class for channels 32, 68 and 96. This leaves us channels 144, 169 and 173, which are included in this patch. I tested 169 and 173 with a mt76 based USB dongle (AVM AC 860) and they worked fine. If I saw that right, these channels are also covered by register definitions inside the driver. Channel 144 should also work, but gets disabled by the kernel as of now. Signed-off-by: Markus Theil <markus.theil@tu-ilmenau.de> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: fix up typo in Kconfig for MT7663USean Wang
Fix up typo in Kconfig with indicating MT7663U is an 802.11ac device Fixes: eb99cc95c3b6 ("mt76: mt7615: introduce mt7663u support") Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7663: introduce ARP filter offloadSean Wang
Introduce ARP filter offload Co-developed-by: Wan-Feng Jiang <Wan-Feng.Jiang@mediatek.com> Signed-off-by: Wan-Feng Jiang <Wan-Feng.Jiang@mediatek.com> Co-developed-by: Soul Huang <Soul.Huang@mediatek.com> Signed-off-by: Soul Huang <Soul.Huang@mediatek.com> Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: usb: rely on mt76_for_each_q_rxLorenzo Bianconi
Rely on mt76_for_each_q_rx whenever possible in order to simply the code Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: re-enable offloading of sequence number assignmentFelix Fietkau
Preparation for supporting more offload features Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: overwrite qid for non-bufferable mgmt framesLorenzo Bianconi
Overwrite hw queue id for non-bufferable management frames if the hw support always txq (altxq) in order to be in sync with mac txwi code Fixes: cdad4874057d ("mt76: mt7615: add dma and tx queue initialization for MT7622") Fixes: f40ac0f3d3c0 ("mt76: mt7615: introduce mt7663e support") Suggested-by: Felix Fietkau <nbd@nbd.name> Tested-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: fix hw queue mappingLorenzo Bianconi
mt7622/mt7663 chipsets rely on a fixed reverse queue map order respect to mac80211 one: - q(0): IEEE80211_AC_BK - q(1): IEEE80211_AC_BE - q(2): IEEE80211_AC_VI - q(3): IEEE80211_AC_VO Fixes: cdad4874057d ("mt76: mt7615: add dma and tx queue initialization for MT7622") Fixes: f40ac0f3d3c0 ("mt76: mt7615: introduce mt7663e support") Co-developed-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Co-developed-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: mt7615: fix lmac queue debugsfs entryLorenzo Bianconi
acs and wmm index are swapped in mt7615_queues_acq respect to the hw design Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-21mt76: add missing lock configuring coverage classLorenzo Bianconi
Coverage class callback can potentially run in parallel with other routines (e.g. mt7615_set_channel) that configures timing registers. Run coverage class callback holding mt76 mutex Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2020-07-20net: dsa: qca8k: implement the port MTU callbacksJonathan McDowell
This switch has a single max frame size configuration register, so we track the requested MTU for each port and apply the largest. v2: - Address review feedback from Vladimir Oltean Signed-off-by: Jonathan McDowell <noodles@earth.li> Acked-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net/fealnx: switch from 'pci_' to 'dma_' APIChristophe JAILLET
The wrappers in include/linux/pci-dma-compat.h should go away. The patch has been generated with the coccinelle script below and has been hand modified to replace GFP_ with a correct flag. It has been compile tested. When memory is allocated, GFP_KERNEL can be used because it is called from the probe function (i.e. 'fealnx_init_one()') and no lock is taken. @@ @@ - PCI_DMA_BIDIRECTIONAL + DMA_BIDIRECTIONAL @@ @@ - PCI_DMA_TODEVICE + DMA_TO_DEVICE @@ @@ - PCI_DMA_FROMDEVICE + DMA_FROM_DEVICE @@ @@ - PCI_DMA_NONE + DMA_NONE @@ expression e1, e2, e3; @@ - pci_alloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3; @@ - pci_zalloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3, e4; @@ - pci_free_consistent(e1, e2, e3, e4) + dma_free_coherent(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_single(e1, e2, e3, e4) + dma_map_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_single(e1, e2, e3, e4) + dma_unmap_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4, e5; @@ - pci_map_page(e1, e2, e3, e4, e5) + dma_map_page(&e1->dev, e2, e3, e4, e5) @@ expression e1, e2, e3, e4; @@ - pci_unmap_page(e1, e2, e3, e4) + dma_unmap_page(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_sg(e1, e2, e3, e4) + dma_map_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_sg(e1, e2, e3, e4) + dma_unmap_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_cpu(e1, e2, e3, e4) + dma_sync_single_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_device(e1, e2, e3, e4) + dma_sync_single_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_cpu(e1, e2, e3, e4) + dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_device(e1, e2, e3, e4) + dma_sync_sg_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2; @@ - pci_dma_mapping_error(e1, e2) + dma_mapping_error(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_dma_mask(e1, e2) + dma_set_mask(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_consistent_dma_mask(e1, e2) + dma_set_coherent_mask(&e1->dev, e2) Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20mISDN: switch from 'pci_' to 'dma_' APIChristophe JAILLET
The wrappers in include/linux/pci-dma-compat.h should go away. The patch has been generated with the coccinelle script below and has been hand modified to replace GFP_ with a correct flag. It has been compile tested. When memory is allocated in 'setup_hw()' (hfcpci.c) GFP_KERNEL can be used because it is called from the probe function and no lock is taken. The call chain is: hfc_probe() --> setup_card() --> setup_hw() When memory is allocated in 'inittiger()' (netjet.c) GFP_ATOMIC must be used because a spin_lock is taken by the caller (i.e. 'nj_init_card()') This is also consistent with the other allocations done in the function. @@ @@ - PCI_DMA_BIDIRECTIONAL + DMA_BIDIRECTIONAL @@ @@ - PCI_DMA_TODEVICE + DMA_TO_DEVICE @@ @@ - PCI_DMA_FROMDEVICE + DMA_FROM_DEVICE @@ @@ - PCI_DMA_NONE + DMA_NONE @@ expression e1, e2, e3; @@ - pci_alloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3; @@ - pci_zalloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3, e4; @@ - pci_free_consistent(e1, e2, e3, e4) + dma_free_coherent(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_single(e1, e2, e3, e4) + dma_map_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_single(e1, e2, e3, e4) + dma_unmap_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4, e5; @@ - pci_map_page(e1, e2, e3, e4, e5) + dma_map_page(&e1->dev, e2, e3, e4, e5) @@ expression e1, e2, e3, e4; @@ - pci_unmap_page(e1, e2, e3, e4) + dma_unmap_page(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_sg(e1, e2, e3, e4) + dma_map_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_sg(e1, e2, e3, e4) + dma_unmap_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_cpu(e1, e2, e3, e4) + dma_sync_single_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_device(e1, e2, e3, e4) + dma_sync_single_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_cpu(e1, e2, e3, e4) + dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_device(e1, e2, e3, e4) + dma_sync_sg_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2; @@ - pci_dma_mapping_error(e1, e2) + dma_mapping_error(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_dma_mask(e1, e2) + dma_set_mask(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_consistent_dma_mask(e1, e2) + dma_set_coherent_mask(&e1->dev, e2) Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20crypto/chtls: Enable tcp window scaling optionVinay Kumar Yadav
Enable tcp window scaling option in hw based on sysctl settings and option in connection request. v1->v2: - Set window scale option based on option in connection request. Signed-off-by: Vinay Kumar Yadav <vinay.yadav@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: add hwmon getter for MAC temperatureMark Starovoytov
This patch adds the possibility to obtain MAC temperature via hwmon. On A1 there are two separate temperature sensors. On A2 there's only one temperature sensor, which is used for reporting both MAC and PHY temperature. Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: A0 ntuple filtersDmitry Bogdanov
This patch adds support for ntuple filters on A0. Signed-off-by: Dmitry Bogdanov <dbogdanov@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: use intermediate variable to improve readability a bitNikita Danilov
This patch syncs up hw_atl_a0.c with an out-of-tree driver, where an intermediate variable was introduced in a couple of functions to improve the code readability a bit. Signed-off-by: Nikita Danilov <ndanilov@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: use U32_MAX in aq_hw_utils.cMark Starovoytov
This patch replaces magic constant ~0U usage with U32_MAX in aq_hw_utils.c Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: add support for 64-bit reads/writesPavel Belous
This patch adds support for 64-bit reads/writes where applicable, e.g. A2 supports them. Signed-off-by: Pavel Belous <pbelous@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: enable ipv6 support for TCP LSO and UDP GSOIgor Russkikh
This patch enables ipv6 support for TCP LSO and UDP GSO. The code itself (aq_nic_map_skb) was ready for this after udp gso feature, but corresponding NETIF_F_TSO6 wasn't enabled. We now have tested both tcp and udp v6 GSO, and enabling them safely. Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: PTP statisticsPavel Belous
This patch adds PTP rings statistics. Before that these were missing from overall stats, hardening debugging and analysis. Signed-off-by: Pavel Belous <pbelous@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: additional per-queue statsDmitry Bogdanov
This patch adds additional per-queue stats, these could be useful for debugging and diagnostics. Signed-off-by: Dmitry Bogdanov <dbogdanov@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: use u64_stats_update_* to protect access to 64-bit statsMark Starovoytov
This patch adds u64_stats_update_* usage to protect access to 64-bit stats, where necessary. This is necessary for per-ring stats, because they are updated by the driver directly, so there is a possibility for a partial read. Other stats require no additional protection, e.g.: * all MACSec stats are fetched directly from HW (under semaphore); * nic/ndev stats (aq_stats_s) are fetched directly from FW (under mutex). Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: split rx and tx per-queue statsMark Starovoytov
This patch splits rx and tx per-queue stats. This change simplifies the follow-up introduction of PTP stats and u64_stats_update_* usage. Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: make _get_sw_stats return count as return valueMark Starovoytov
This patch changes aq_vec_get_sw_stats() to return count as a return value (which was unused) instead of an out parameter. Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: use simple assignment in _get_stats and _get_sw_statsMark Starovoytov
This patch replaces addition assignment operator with a simple assignment in aq_vec_get_stats() and aq_vec_get_sw_stats(), because it is sufficient in both cases and this change simplifies the introduction of u64_stats_update_* in these functions. Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20net: atlantic: move FRAC_PER_NS to aq_hw.hMark Starovoytov
This patch moves FRAC_PER_NS to aq_hw.h so that it can be used in both hw_atl (A1) and hw_atl2 (A2) in the future. Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20ethernet: myri10ge: use generic power managementVaibhav Gupta
Drivers using legacy PM have to manage PCI states and device's PM states themselves. They also need to take care of configuration registers. With improved and powerful support of generic PM, PCI Core takes care of above mentioned, device-independent, jobs. This driver makes use of PCI helper functions like pci_save/restore_state(), pci_enable/disable_device(), pci_set_power_state() and pci_set_master() to do required operations. In generic mode, they are no longer needed. Change function parameter in both .suspend() and .resume() to "struct device*" type. Use to_pci_dev() and dev_get_drvdata() to get "struct pci_dev*" variable and drv data. Compile-tested only. Signed-off-by: Vaibhav Gupta <vaibhavgupta40@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20qed: add support for the extended speed and FEC modesAlexander Lobakin
Add all necessary code (NVM parsing, MFW and Ethtool reports etc.) to support extended speed and FEC modes. These new modes are supported by the new boards revisions and newer MFW versions. Misc: correct port type for MEDIA_KR. Signed-off-by: Alexander Lobakin <alobakin@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20qed: populate supported link modes maps on module initAlexander Lobakin
Simplify and lighten qed_set_link() by declaring static link modes maps and populating them on module init. This way we save plenty of text size at the low expense of __ro_after_init and __initconst data (the latter will be purged after module init is done). Misc: sanitize exit callback. Signed-off-by: Alexander Lobakin <alobakin@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-20qed: add missing loopback modesAlexander Lobakin
These modes are relevant only for several boards, but may be reported by MFW as well as the others. Signed-off-by: Alexander Lobakin <alobakin@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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