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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"We have no core changes but lots of incremental development in drivers
all over the place: Renesas, NXP, Mediatek and Actions Semiconductor
keep churning out new SoCs.
I have some subtree maintainers for Renesas and Intel helping out to
keep down the load, it's been working smoothly (Samsung also have a
subtree but it was not used this cycle.)
New drivers:
- NXP (ex Freescale) i.MX 8 QXP SoC driver.
- Mediatek MT6797 SoC driver.
- Mediatek MT7629 SoC driver.
- Actions Semiconductor S700 SoC driver.
- Renesas RZ/A2 SoC driver.
- Allwinner sunxi suniv F1C100 SoC driver.
- Qualcomm PMS405 PMIC driver.
- Microsemi Ocelot Jaguar2 SoC driver.
Improvements:
- Some RT improvements (using raw spinlocks where appropriate).
- A lot of new pin sets on the Renesas PFC pin controllers.
- GPIO hogs now work on the Qualcomm SPMI/SSBI pin controller GPIO
chips, and Xway.
- Major modernization of the Intel pin control drivers.
- STM32 pin control driver will now synchronize usage of pins with
another CPU using a hardware spinlock"
* tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (145 commits)
dt-bindings: arm: fsl-scu: add imx8qm pinctrl support
pinctrl: freescale: Break dependency on SOC_IMX8MQ for i.MX8MQ
pinctrl: imx-scu: Depend on IMX_SCU
pinctrl: ocelot: Add dependency on HAS_IOMEM
pinctrl: ocelot: add MSCC Jaguar2 support
pinctrl: bcm: ns: support updated DT binding as syscon subnode
dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon
MAINTAINERS: merge at91 pinctrl entries
pinctrl: imx8qxp: break the dependency on SOC_IMX8QXP
pinctrl: uniphier: constify uniphier_pinctrl_socdata
pinctrl: mediatek: improve Kconfig dependencies
pinctrl: msm: mark PM functions as __maybe_unused
dt-bindings: pinctrl: sunxi: Add supply properties
pinctrl: meson: meson8b: add the missing GPIO_GROUPs for BOOT and CARD
pinctrl: meson: meson8: add the missing GPIO_GROUPs for BOOT and CARD
pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
pinctrl: meson: meson8b: fix the GPIO function for the GPIOAO pins
pinctrl: meson: meson8: fix the GPIO function for the GPIOAO pins
pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
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Add the BOOT and CARD pins as GROUP_GROUPs as well so they can be
configured in devicetree using groups = BOOTx or groups = CARDx. This
makes the behavior consistent with other pins inside the same driver as
well as with the BOOT and CARD pins of the GXBB and GXL pinctrl drivers.
Fixes: 6ac730951104a4 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Rename the existing "gpio" function to "gpio_periphs". This makes it
consistent with the "gpio_aobus" function. Also GXBB and GXL are also
using the "gpio_periphs" naming, so this makes the code here consistent
with other Amlogic pinctrl drivers.
No functional changes since thee "gpio" function is currently not used.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The GPIOAO pins (as well as the two exotic GPIO_BSD_EN and GPIO_TEST_N)
only belong to the pin controller in the AO domain. With the current
definition these pins cannot be referred to in .dts files as group
(which is possible on GXBB and GXL for example).
Add a separate "gpio_aobus" function to fix the mapping between the pin
controller and the GPIO pins in the AO domain. This is similar to how
the GXBB and GXL drivers implement this functionality.
Fixes: 9dab1868ec0db4 ("pinctrl: amlogic: Make driver independent from two-domain configuration")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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These are only available on the Meson8m2 SoC (which uses the same
DesignWare Ethernet MAC as Meson8b).
The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII
PHYs or the RGMII TX clock (as far as we know the frequency is
controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP
block).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add Meson8m2 support to the existing Meson8 pinctrl driver. Since there
are only very few changes (Meson8m2 has an extra signal on 10 CBUS pins,
no other differences were found so far).
Add the new compatible strings for Meson8m2 to the existing Meson8
driver so we don't have to duplicate the whole driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This change prepare the introduction of new meson SoC. This new SoC will
share the same gpio/pinconf registers but the pinmux part will be
different. While the format of the data associated with each pinmux group
will change, the way to handle pinmuxing will be similar.
To deal with this new situation, the meson_pmx_struture is kept but the
data associated to it is now generic. This allows to reuse the basic
functions which would otherwise be copy/pasted in each pinmux driver
(such as getting the name a count of groups and functions) Only the
functions actually using this specific data is taken out of the common
code and is handling the SoC pinmuxing
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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When meson pinctrl is enabled, all meson platforms pinctrl drivers are
built in the kernel, with a significant amount of data.
This leads to situation where pinctrl drivers targeting an architecture
are also compiled and shipped on another one (ex: meson8 - ARM - compiled
and shipped on ARM64 builds). This is a waste of memory we can easily
avoid.
This change makes 4 pinctrl drivers (1 per SoC) out the original single
driver, allowing to compile and ship only the ones required.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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pin_base was used with the manually set pin offset in meson pinctrl. This
is no longer the case, pin_base is 0 on every meson pinctrl controllers
and should go away.
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Offset on meson pinctrl and gpios is something that was carried from the
vendor driver, where there is a weird link between the 2
controllers. Since these 2 controllers are independent, this offset adds
an unnecessary complexity.
This patch remove this manually set offset and rely on pinctrl to figure
out the gpio base offset
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add GPIO interrupt information to pinctrl data. Added to the original
version from Jerome was data for Meson GXL.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This adds another missing pin found in the Meson8 SoCs. Currently
there's no driver which would use this pin yet.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This adds another missing pin found in the Meson8 SoCs. Currently
there's no driver which would use this pin yet.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This adds support for the I2S and SPDIF input and output pins, similar
to what we have on GXBB and GXL.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This adds the missing pins for the PWM controllers found in Amlogic
Meson8 SoCs. This includes the pins for PWM_A, PWM_B, PWM_C, PWM_D,
PWM_E and PWM_F controllers.
There is an additional PWM function with the name PWM_VS in the vendor
kernel sources which seems to be used for external video input. Thus
it's not part of this change as the IP block behind the pwm-meson driver
is not responsible for these pins.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The driver originally supported more domains (register ranges) per
pinctrl device, but since commit 9dab1868ec0d ("pinctrl: amlogic: Make
driver independent from two-domain configuration") each device gets
assigned a single domain and we instantiate multiple pinctrl devices
in the DT.
Therefore, now the 'meson_domain' and 'meson_domain_data' structures
don't have any reason to exist and can be removed to make the model
simpler to understand. This commit doesn't change behavior.
Tested on a Odroid-C2.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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In the Amlogic Meson8 / Meson8b platforms we have two different buses:
cbus and aobus, corresponding to 2 different power domains (regular and
always-on). On each bus a different set of registers is mapped to manage
muxes, GPIOs and in general to control a clear subset of the pins.
Considering this architecture, having two different pinctrl devices, one
for each bus / power domain, makes much more sense than just having one
single device.
Right now we have one single pin controller driver that uses two
different domains (represented by 'gpio' and 'gpio-ao' sub-nodes in the
DTS) to manage the set of registers on the two buses. This dual-domain
configuration is hardcoded into the driver that strictly requires one
domain for each bus in the same pin controller device.
With this patch we refactor the driver to allow splitting the driver in
two parts. This change is needed to have a proper description of the HW
in the device-tree where we want to introduce aobus and cbus.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This patch introduces a new PIN macro and few small modifications to
simplify and shorten the Meson pinctrl drivers and cleanup the support
file for the AmLogic Meson8 SoC.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. It currently supports only Meson8, however the
common code should be generic enough to work also for other SoCs after
having defined the proper set of functions and groups.
GPIO interrupts are not supported at the moment due to lack of
documentation.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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