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path: root/drivers/mmc/host/dw_mmc.h
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2013-09-25mmc: dw_mmc: control card read thresholdSeungwon Jeon
Card Read Threshold should be ensured that the card clock does not stop in the middle of a block of data being transferred from the card to the Host. Specially, clock stop is allowed in fast transfer such as HS200 or SDR104 mode. And so, it should be enabled. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-09-25mmc: dw_mmc: adjust the fifoth with block sizeSeungwon Jeon
This change helps to choose msize, rx_watermark and tx_watermark depending on block size for IDMAC mode. For SDIO block size can be variable, so if these values are set incorrectly, card clock may stop. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-09-25mmc: dw_mmc: add support tuning schemeSeungwon Jeon
For the speed modes HS200 and SDR104, tuning is needed to determine the correct sampling point. Actual tuning procedure is provided by specific host controller driver. This patch defines the tuning command and tuning data. Additionally, 'struct dw_mci_slot' is moved to header file to consider the extensive usages in driver. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-06-27mmc: dw_mmc: Add support DW SD/MMC driver on SOCFPGADinh Nguyen
Add platform specific functionality for the DW SD/MMC driver for SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms can use this define. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Seungwon Jeon <tgih.jun@samsung.com Signed-off-by: Chris Ball <cjb@laptop.org>
2013-06-27mmc: dw_mmc: change the macro name from DTO to DRTOJaehoon Chung
At Interrupt status register, Bit9 is Data Read Timeout. But we used macro name as the DTO. It could be confused with the Data Transfer Over(DTO)-Bit[3]. It's clearly that is changed the DRTO instead of DTO. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-04-12mmc: dw_mmc: let device core setup the default pin configurationThomas Abraham
With device core now able to setup the default pin configuration, the pin configuration code based on the deprecated Samsung specific gpio bindings is removed. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-10-03mmc: dw_mmc: add support for implementation specific callbacksThomas Abraham
The core dw-mshc controller driver can let platform specific implementations of the dw-mshc controller to control the hardware as required by such implementations. This is acheived by invoking implementation specific (optional) callbacks. Define the list of callbacks supported the add invocation points for the same. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Will Newton <will.newton@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-03-25mmc: Support of PCI mode in the dw_mmc driverShashidhar Hiremath
Support of PCI mode for the dw_mmc driver. This Patch adds the support for the scenario where the Synopsys Designware IP is present on the PCI bus. The patch adds the minimal modifications necessary for the driver to work on PCI platform. Also added separate files for PCI and PLATFORM modes of operation. Signed-off-by: Shashidhar Hiremath <shashidharh@vayavyalabs.com> Acked-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-01-12mmc: dw_mmc: fixed wrong bit operation for SDMMC_GET_FCNT()Jaehoon Chung
In status register, fifo_count is bit[29:17]. (0x1FFF is correct) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Will Newton <will.newton@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-10-26mmc: dw_mmc: modify DATA register offsetJaehoon Chung
In dw_mmc 2.40a spec, Data register's offset is changed. Before we used Data register offset 0x100. but if somebody uses a 2.40a controller, we must use 0x200 for Data register. This patch adds a version-id checking point and uses SDMMC_DATA(x) instead of SDMMC_DATA. It assumes 2.40a is the latest version. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-10-26mmc: dw_mmc: Support SDIO interrupts for all slotsShashidhar Hiremath
The Patch adds the support for SDIO interrupts for all slots. It includes enabling of SDIO interrupts through dw_mci_enable_sdio_irq and the handling of the slot specific interrupts in the Interrupt Service Routine. Signed-off-by: Shashidhar Hiremath <shashidharh@vayavyalabs.com> Acked-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-07-20mmc: dw_mmc: don't hard code fifo depth, fix usageJames Hogan
The FIFO_DEPTH hardware configuration parameter can be found from the power-on value of RX_WMark in the FIFOTH register. This is used to initialise the watermarks, but when calculating the number of free fifo spaces a preprocessor definition is used which is hard coded to 32. Fix reading the value out of FIFOTH (the default value in the RX_WMark field is FIFO_DEPTH-1 not FIFO_DEPTH). Allow the fifo depth to be overriden by platform data (since a bootloader may have changed FIFOTH making auto-detection unreliable). Store the fifo_depth for later use. Also fix the calculation to find the number of free bytes in the fifo to include the fifo depth in the left shift by the data shift, since the fifo depth is measured in fifo items not bytes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Will Newton <will.newton@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-07-20mmc: dw_mmc: brackets in register access macrosJames Hogan
Add brackets around use of the dev argument to the mci_{read,write}{w,l,q}() macros, for extra safety. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Will Newton <will.newton@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-03-15mmc: dw_mmc: support DDR modeJaehoon Chung
This patch adds DDR mode support to dw_mmc. If we set any bit in UHS_REG bit[16:31], the card of that slot is supported for DDR mode. For example, if UHS_REG[16] is set, card number 0 is DDR mode. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Will Newton <will.newton@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-01-08mmc: dw_mmc: Add Synopsys DesignWare mmc host driver.Will Newton
This adds the mmc host driver for the Synopsys DesignWare mmc host controller, found in a number of embedded SoC designs. Signed-off-by: Will Newton <will.newton@imgtec.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Reviewed-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
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