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path: root/drivers/gpu/drm/amd/display
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2020-07-01drm/amd/display: Add DCN3 HUBPBhawanpreet Lakha
Add support to program the DCN3 HUBP (Display to data fabric interface pipe) HW Blocks: +--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 HUBHUBBhawanpreet Lakha
Add support to program the HUBBUB (DCN memory HUB interface) HW Blocks: +--------+ | HUBBUB | +--------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 DPPBhawanpreet Lakha
Add support to program the DCN3 DPP (Multiple pipe and plane combine) HW Blocks: +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 MPCBhawanpreet Lakha
Add support to program the DCN3 MPC (Multiple pipe and plane combine) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 OPP headerBhawanpreet Lakha
Add support to program the DCN3 OPP (Output Plane Processing) HW Blocks: +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 OPTCBhawanpreet Lakha
Add support for programming the DCN3 OPTC (Output Timing Controller) HW Blocks: +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 DCCGBhawanpreet Lakha
Add programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 CLK_MGRBhawanpreet Lakha
Adds support for handling of clocking relevant to the DCN3 block Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 DIOBhawanpreet Lakha
Add support for the DIO (Display IO) block of DCN3, which entails our stream and link encoders. HW Blocks: +--------+ | DIO | +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 chip idsBhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28Revert "drm/amd/display: disable dcn20 abm feature for bring up"Harry Wentland
This reverts commit 96cb7cf13d8530099c256c053648ad576588c387. This change was used for DCN2 bringup and is no longer desired. In fact it breaks backlight on DCN2 systems. Cc: Alexander Monakov <amonakov@ispras.ru> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Anthony Koo <Anthony.Koo@amd.com> Cc: Michael Chiu <Michael.Chiu@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reported-and-tested-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: 3.2.87Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Don't compare same stream for synchronized vblankAlvin Lee
[Why] When determining synchronzied vblank we don't need to compare the stream with itself [How] If comparing same stream, continue to next iteration Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: [FW Promotion] Release 1.0.12Anthony Koo
[Header Changes] - Combine all interface dependencies between driver and fw into a single header file - Add FW Versioning to the dmub_cmd.h file Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: enable plane if container of plane_status changedHugo Hu
[why] We hit an issue which driver reallocate a pipe from desktop bottom pipe to video bottom pipe. In this case, driver need to re-enable plane. [how] Enable plane if container of plane status changed. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: combine public interfaces into single headerAnthony Koo
[Why] We want to better encapsulate all driver-fw dependencies into a single file. [How] Combine all the headers under inc folder into a single header Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Allow Diagnostics test with eDP not connectedEric Bernstein
[Why] Diagnostics DIO test with eDP not connected is required to run [How] Allow Diagnostics test with eDP not connected to skip link detection but still execute DIO test Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: unit show garbage when do OPTC blankPaul Hsieh
[Why] Unit enter to S4, garbage show on screen when do OPTC blank. [How] Wait for vblank then do OPTC blank Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Guard against invalid array accessAric Cyr
[Why] There are scenarios where no OPP is assigned to an OTG so its value is 0xF which is outside the size of the OPP array causing a potential driver crash. [How] Change the assert to an early return to guard against access. If there's no OPP assigned already, then OTG will be blank anyways so no functionality should be lost. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Zhan Liu <Zhan.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Disable PG on NV12Alvin Lee
[Why] HW team request to disable PG on NV12 (fixing missed cases) [How] Disable dpp and hubp PG Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Increase Default Sizes of FW State and Trace BufferDavid Galiffi
[WHY] To facilitate DM removing the dependency between dc and the firmware binary. [HOW] Setting the default values to match VBIOS: 64 KB. These values are only used if meta is absent. Signed-off-by: David Galiffi <David.Galiffi@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Handle link loss interrupt betterAric Cyr
[Why] Link loss currently only retrains and re-enables the stream. This can cause issues for some sinks. [How] When link loss occurs, the link and stream(s) should be completely disabled and then reenabled. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: simplify dml log2 functionDmytro Laktyushkin
Current implementation is slightly inaccurate and will often result in truncation/floor operation decrementing an exact integer output by 1. Only rounded down output is ever expected, just extract the fp exponent for this to increase performance and avoid any truncation issues. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Fix incorrect HDCP caps for dongleBhawanpreet Lakha
[Why] Previously we used link signal type to get the caps. We should use the sink signal type [How] Use sink signal type instead of link signal type Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: link_status not align when power off encoderPaul Hsieh
[Why] The link_status is incorrect cause driver power off eDP when backlight on. Some eDP panels may show garbage on screen. [How] Correct link_status when power off encoder Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: 3.2.86Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Make BREAK_TO_DEBUGGER() a debug printNicholas Kazlauskas
[Why] Warnings in the kernel are generally treated as errors. The BREAK_TO_DEBUGGER macro is not a critical error or warning, but rather intended for developer use to help investigate behavior and sequences for other issues. We do still make use of DC_ERROR/ASSERT(0) in various places in the code for things that are genuine issues. Since most developers don't actually KGDB while debugging the kernel these essentially would have no value on their own since the KGDB breakpoint wouldn't trigger - ASSERT(0) was used as a shortcut to get a stacktrace. [How] Turn it into a DRM_DEBUG_DRIVER print instead. We unfortunately lose the stacktrace, but we still do retain some of the useful debug information this offers by having at least the function and line number loggable. If KGDB is supported in the kernel this will still trigger a real breakpoint as well. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: FW Release 1.0.11Anthony Koo
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Remove nv12 work aroundYongqiang Sun
[Why] dal side nv12 wa has a lot of side effects. KMD side wa is used, so this should be remove. [How] Removed wa from dal side. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: fix dml immediate flip inputDmytro Laktyushkin
Set the correct value to immediate flip required field. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Samson Tam <Samson.Tam@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: fix dml log2 functionDmytro Laktyushkin
This change removes internal rounding in dml_log2 function. Dml_log2 is expected to return a float output. In case an int is needed dml will floor the output on it's own. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Support CW4 for DMUB ringbuffer inboxNicholas Kazlauskas
[Why] Region 4 is non cacheable and slower than using cache window 4. [How] Check the firmware version to determine how we should program the base address and memory windows. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Add DMUB firmware version helpers in DMUB serviceNicholas Kazlauskas
[Why] In order to switch over the inbox from region4 to cw4 we need to know if the firmware is capable of properly invalidating the cache before reading the commands. Easiest way is to just check the firmware version, but we don't have the helper macros or a way for the dmub_srv to know what version it is. [How] Add a new fw_version field to the creation parameters that driver can optional pass in. Assumes a version of 0x00000000 is invalid. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: vbios data table packingJake Wang
[WHY] Currently we're copying the entire bios image into vbios. Loading time for FW with entire bios(54272 bytes) is 105138us. By copying only the sections of bios we're using(4436 bytes), loading time drops to 104326us which saves us 812us. [HOW] ROM header, master data table, and all data tables will be packed in contiguous manner. The offsets for the data tables are remapped to their newly packed location. Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: DP link layer test 4.2.1.1 fix due to specs updateWenjing Liu
[why] DP link layer CTS specs updated to change the test parameters in test 4.2.1.1. Before it requires source to delay 400us on aux no reply. With the specs updates Errata5, it requires source to delay 3.2ms (based on LTTPR aux timeout) This causes our test to fail after updating with the latest test equipment firmware. [how] the change is to allow LTTPR 3.2ms aux timeout delay by default. And only set to 400us if LTTPR is not present. Before this piece of logic is interwined with LTTPR support. Now we will default to 3.2ms aux timeout even if LTTPR support is not enabled by driver. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: update dml interfaces and variablesDmytro Laktyushkin
Preparation for new asic support. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: 3.2.85Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Fix ABM memory alignment issueWyatt Wood
[Why] Due to packing of abm_config_table, memory addresses aren't aligned to 32 bit boundary dmcub prefers. Therefore when using pointers to this structure, it's possible that dmcub will automatically align the data read from that address, yielding incorrect values. [How] Instead of packing 1 byte boundary, explicitly pack values to 4 byte boundary. Since there is a dependency on the existing iram table structure on driver side, we must copy to a second structure, which is aligned correctly, before passing to fw. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: FW release 1.0.10Anthony Koo
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Implement some asic specific abm call backs.Yongqiang Sun
[Why & How] Implement abm set_pipe call stacks Have some asics speicifc call stacks for abm. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Add bit swap helper based on endiannessRodrigo Siqueira
Christian Koenig pointed out a code duplication related to bit swap in case of big-endian manipulation. This commit adds a helper for handling this verification and reduces the requirement of replicate some part of the code. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Don't pass invalid fw_bss_data pointer into DMUB srvNicholas Kazlauskas
[Why] If bss_data_size is 0 then we shouldn't be passing down fw_bss_data into the DMUB service since the region isn't really "valid." [How] Pass NULL instead if the size is 0. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Zhan Liu <Zhan.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Check bss_data_size before going down legacy DMUB load pathNicholas Kazlauskas
[Why] New unified firmware binary with only inst const still passes down fw_bss_data != NULL and params->bss_data_size == 0 from DM. This leads it into the legacy path causing firmware state allocation to be too small. [How] Check bss_data_size as well. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Zhan Liu <Zhan.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Do not fail if build scaling params failsSung Lee
[WHY] Failing validation when building scaling parameters causes corruption to occur due to pipe splitting with smaller pixel widths than HW supports. This needs to fail silently for now to hide the corruption until the corruption itself can be fixed. [HOW] Do not fail validation if building scaling params fails. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amd/display: Handle persistence in DMJaehyun Chung
[Why] Remove dm_write_persistent_data and dm_read_persistent_data as persistence should be handled in DM. [How] Remove functions. Move read/write calls into DM layer while maintaining logic. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-27drm/amd/display: Fix potential integer wraparound resulting in a hangAric Cyr
[Why] If VUPDATE_END is before VUPDATE_START the delay calculated can become very large, causing a soft hang. [How] Take the absolute value of the difference between START and END. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-27drm/amd/display: drop cursor position check in atomic testSimon Ser
get_cursor_position already handles the case where the cursor has negative off-screen coordinates by not setting dc_cursor_position.enabled. Signed-off-by: Simon Ser <contact@emersion.fr> Fixes: 626bf90fe03f ("drm/amd/display: add basic atomic check for cursor plane") Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-22drm/amd/display: Handle GPU reset for DC blockBhawanpreet Lakha
[Why] Previously we used the s3 codepath for gpu reset. This can lead to issues in certain case where we end of waiting for fences which will never come (because parts of the hw are off due to gpu reset) and we end up waiting forever causing a deadlock. [How] Handle GPU reset separately from normal s3 case. We essentially need to redo everything we do in s3, but avoid any drm calls. For GPU reset case suspend: -Acquire DC lock -Cache current dc_state -Commit 0 stream/planes to dc (this puts dc into a state where it can be powered off) -Disable interrupts resume -Edit cached state to force full update -Commit cached state from suspend -Build stream and plane updates from the cached state -Commit stream/plane updates -Enable interrupts -Release DC lock v2: -Formatting -Release dc_state Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-21drm/amd/display: Set/Reset avmute when disable/enable streamJinze Xu
[Why] When disconnect fe from be, something such as unstable clock may cause garbage occurs. [How] Send set avmute at the beginning of disable stream and send reset avmute at the end of enable stream. Signed-off-by: Jinze Xu <jinze.xu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-21drm/amd/display: Fix incorrectly pruned modes with deep colorStylon Wang
[Why] When "max bpc" is set to enable deep color, some modes are removed from the list if they fail validation on max bpc. These modes should be kept if they validates fine with lower bpc. [How] - Retry with lower bpc in mode validation. - Same in atomic commit to apply working bpc, not necessarily max bpc. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 22:12:48 +0000