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path: root/drivers/clk
AgeCommit message (Expand)Author
2018-06-01clk: aspeed: Add 24MHz fixed clockLei YU
2018-06-01clk: imx7d: correct enet clock CCGR registersAnson Huang
2018-06-01clk: imx7d: correct enet phy ref clock gatesAnson Huang
2018-06-01clk: imx6sl: correct ocram_podf clock typeAnson Huang
2018-06-01clk: imx6sx: disable unnecessary clocks during clock initializationAnson Huang
2018-06-01clk: qcom: Add video clock controller driver for SDM845Amit Nischal
2018-06-01clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clkManu Gautam
2018-06-01clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabledRajendra Nayak
2018-06-01clk: qcom: Register the gdscs before the clocksRajendra Nayak
2018-06-01clk: qcom: gdsc: Add support for ALWAYS_ON gdscsRajendra Nayak
2018-06-01clk: berlin: switch to SPDX license identifierJisheng Zhang
2018-05-30clk: davinci: Fix link errors when not all SoCs are enabledDavid Lechner
2018-05-30clk: davinci: psc: allow for dev == NULLDavid Lechner
2018-05-30clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLAREDavid Lechner
2018-05-30clk: davinci: pll: allow dev == NULLDavid Lechner
2018-05-30clk: davinci: psc-dm365: fix few clocksSekhar Nori
2018-05-30clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabledSekhar Nori
2018-05-30clk: davinci: psc-dm355: fix ASP0/1 clkdev lookupsDavid Lechner
2018-05-30clk: davinci: pll-dm355: fix SYSCLKn parent namesDavid Lechner
2018-05-30clk: davinci: pll-dm355: drop pll2_sysclk2David Lechner
2018-05-23clk: rockchip: remove deprecated gate-clk code and dt-bindingHeiko Stuebner
2018-05-22clk: rockchip: use match_string() helperYisheng Xie
2018-05-21clk: meson: axg: let mpll clocks round closestJerome Brunet
2018-05-21clk: meson: mpll: add round closest supportJerome Brunet
2018-05-21clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko
2018-05-18clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko
2018-05-18clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko
2018-05-18clk: meson: use SPDX license identifiers consistentlyJerome Brunet
2018-05-17clk: x86: Add ST oscout platform clockAkshu Agrawal
2018-05-17clk: sunxi-ng: r40: export a regmap to access the GMAC registerIcenowy Zheng
2018-05-17clk: sunxi-ng: r40: rewrite init code to a platform driverIcenowy Zheng
2018-05-15clk: at91: PLL recalc_rate() now using cached MUL and DIV valuesMarcin Ziemianowicz
2018-05-15clk: stm32: fix: stm32 clock drivers are not compiled by defaultGabriel Fernandez
2018-05-15clk: imx6ull: use OSC clock during AXI rate changeStefan Agner
2018-05-15clk: davinci: psc-da830: fix USB0 48MHz PHY clock registrationSekhar Nori
2018-05-15clk: imx: Add new clo01 and clo2 controlled by CCOSRMichael Trimarchi
2018-05-15clk: mediatek: add g3dsys support for MT2701 and MT7623Sean Wang
2018-05-15clk: mediatek: correct the clocks for MT2701 HDMI PHY moduleRyder Lee
2018-05-15clk: bulk: silently error out on EPROBE_DEFERJerome Brunet
2018-05-15clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoCJianguo Sun
2018-05-15clk:aspeed: Fix reset bits for PCI/VGA and PECIJae Hyun Yoo
2018-05-15clk: aspeed: Support second reset registerJoel Stanley
2018-05-15clk: socfpga: stratix10: suppress unbinding platform's clock driverDinh Nguyen
2018-05-15clk: socfpga: stratix10: use platform driver APIsDinh Nguyen
2018-05-15clk: uniphier: add LD11/LD20 stream demux system clockKatsuhiro Suzuki
2018-05-15clk: samsung: simplify getting .drvdataWolfram Sang
2018-05-15clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()'Christophe JAILLET
2018-05-15clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clockGabriel Fernandez
2018-05-15clk: meson: drop CLK_SET_RATE_PARENT flagYixun Lan