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path: root/drivers/clk/imx
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2019-09-17clk: imx: imx8mn: fix pll mux bitPeng Fan
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Suggested-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lkml.kernel.org/r/1568043491-20680-5-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: imx: imx8mm: fix pll mux bitPeng Fan
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Suggested-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lkml.kernel.org/r/1568043491-20680-4-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: imx: clk-pll14xx: unbypass PLL by defaultPeng Fan
When registering the PLL, unbypass the PLL. The PLL has two bypass control bit, BYPASS and EXT_BYPASS. we will expose EXT_BYPASS to clk driver for mux usage, and keep BYPASS inside pll14xx usage. The PLL has a restriction that when M/P change, need to RESET/BYPASS pll to avoid glitch, so we could not expose BYPASS. To make it easy for clk driver usage, unbypass PLL which does not hurt current function. Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lkml.kernel.org/r/1568043491-20680-3-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17clk: imx: pll14xx: avoid glitch when set ratePeng Fan
According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to output unstable clock until lock time passes. PLL1416X/PLL1443XA may generate a glitch at FOUT." So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch. In the end of set rate, BYPASS will be cleared. When prepare clock, also need to take care to avoid glitch. So we also follow Spec to set BYPASS before RESETB changed from 0 to 1. And add a check if the RESETB is already 0, directly return 0; Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lkml.kernel.org/r/1568043491-20680-2-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-24clk: imx: imx8mn: fix audio pll settingPeng Fan
The AUDIO PLL max support 650M, so the original clk settings violate spec. This patch makes the output 786432000 -> 393216000, and 722534400 -> 361267200 to aligned with NXP vendor kernel without any impact on audio functionality and go within 650MHz PLL limit. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mn: Add necessary frequency support for ARM PLL tableAnson Huang
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing frequency for ARM PLL table. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mn: Add missing rate_count assignment for each PLL structureAnson Huang
Add .rate_count assignment which is necessary for searching required PLL rate from the each PLL table. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mn: fix int pll clk gatePeng Fan
To Frac pll, the gate shift is 13, however to Int PLL the gate shift is 11. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mn: Add GIC clockLeonard Crestez
This is enabled by default but if it's not explicitly defined and marked as critical then its parent might get turned off. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mn: Fix incorrect parentsLeonard Crestez
* Replace to audio_pll2_clk with audio_pll2_out * Replace sys3_pll2_out with sys_pll3_out * Replace sys1_pll_40m with sys_pll1_40m * qspi parent[2] is sys_pll2_333m not sys_pll1_800m Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mm: Fix incorrect parentsLeonard Crestez
* There is no video_pll2 on imx8mm, replace with dummy * Replace reference to sys_pll3_clk with sys_pll3_out * qspi parent[2] is sys_pll2_333m not sys_pll1_800m Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mq: Fix sys3 pll referencesLeonard Crestez
The "sys3_pll2_out" CLK was removed in refactoring so all references need to be updated to "sys3_pll_out" Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-12clk: imx8mq: Unregister clks when of_clk_add_provider failedAnson Huang
When of_clk_add_provider failed, all clks should be unregistered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-12clk: imx8mm: Unregister clks when of_clk_add_provider failedAnson Huang
When of_clk_add_provider failed, all clks should be unregistered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mq: Mark AHB clock as criticalAbel Vesa
Initially, the TMU_ROOT clock was marked as critical, which automatically made the AHB clock to stay always on. Since the TMU_ROOT clock is not marked as critical anymore, following commit: "clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOT" all the clocks that derive from ipg_root clock (and implicitly ahb clock) would also have to enable, along with their own gate, the AHB clock. But considering that AHB is actually a bus that has to be always on, we mark it as critical in the clock provider driver and then all the clocks that derive from it can be controlled through the dedicated per IP gate which follows after the ipg_root clock. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mn: Keep uart clocks on for early consoleAnson Huang
Call imx_register_uart_clocks() API to keep uart clocks enabled when earlyprintk or earlycon is active. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx: Remove unused function statementAnson Huang
imx_register_uart_clocks_hws() function is NOT implemented at all, remove it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx7ulp: Make sure earlycon's clock is enabledAnson Huang
Earlycon's clock could be disabled during kernel boot up, if earlycon is enabled and its clock is gated, then kernel boot up will fail. Make sure earlycon's clock is enabled during kernel boot up. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mm: Switch to platform driverAbel Vesa
There is no strong reason for this to use CLK_OF_DECLARE instead of being a platform driver. Plus, this will now be aligned with the other i.MX8M clock drivers which are platform drivers. In order to make the clock provider a platform driver all the data and code needs to be outside of .init section. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx: imx8mm: fix audio pll settingPeng Fan
The AUDIO PLL max support 650M, so the original clk settings violate spec. This patch makes the output 786432000 -> 393216000, and 722534400 -> 361267200 to aligned with NXP vendor kernel without any impact on audio functionality and go within 650MHz PLL limit. Cc: <stable@vger.kernel.org> Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80mAnson Huang
i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT sys_pll1_800m, correct it. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mm: Fix typo of pwm3 clock's mux option #4Anson Huang
i.MX8MM has no sys3_pll2_out clock, PWM3 clock's mux option #4 should be sys_pll3_out, sys3_pll2_out is a typo, fix it. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx: Remove unused clk based APIAbel Vesa
Now that the i.MX6 and i.MX7 clock drivers have been switched to clk_hw based, we can remove the clk based API that is not used by any i.MX clock driver. The following APIs are going away now: - imx_clk_busy_divider - imx_clk_busy_mux - imx_clk_fixup_divider - imx_clk_fixup_mux - imx_clk_mux_ldb - imx_clk_gate_dis_flags - imx_clk_gate_flags Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mq: set correct parent for usb ctrl clocksLi Jun
Per latest imx8mq datasheet of CCM, the parent of usb1_ctrl_root_clk and usb2_ctrl_root_clk is usb_bus. Signed-off-by: Li Jun <jun.li@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOTAnson Huang
IMX8MQ_CLK_TMU_ROOT is ONLY used for thermal module, the driver should manage this clock, so no need to have CLK_IS_CRITICAL flag set. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mm: rename 'share_count_dcss' to 'share_count_disp'Fancy Fang
Rename 'share_count_dcss' to 'share_count_disp', since the DCSS module does not exist on imx8mm platform. So rename it to avoid any unnecessary confusion. Signed-off-by: Fancy Fang <chen.fang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mm: correct the usb1_ctrl parent to be usb_busLi Jun
Per latest imx8mm datasheet of CCM, the parent of usb1_ctrl_root_clk should be usb_bus. Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8: Add DSP related clocksDaniel Baluta
i.MX8QXP contains Hifi4 DSP. There are four clocks associated with DSP: * dsp_lpcg_core_clk * dsp_lpcg_ipg_clk * dsp_lpcg_adb_aclk * ocram_lpcg_ipg_clk Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx: Add support for i.MX8MN clock driverAnson Huang
This patch adds i.MX8MN clock driver support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx: Add API for clk unregister when driver probe failAnson Huang
For i.MX clock drivers probe fail case, clks should be unregistered in the return path, this patch adds a common API for i.MX clock drivers to unregister clocks when fail. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usageAnson Huang
1416X/1443X PLL are used on i.MX8MM and i.MX8MN and maybe other i.MX8M series SoC later, the macro definitions of these PLLs' initialization should be common for usage. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-07-17Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This round of clk driver and framework updates is heavy on the driver update side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits) clk: consoldiate the __clk_get_hw() declarations clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: at91: sckc: add support for SAM9X60 ...
2019-07-12Merge branches 'clk-rpi-cpufreq', 'clk-tegra', 'clk-simplify-provider.h', ↵Stephen Boyd
'clk-sprd' and 'clk-at91' into clk-next - Support for CPU clks on Raspberry Pi devices - Slow clk support for AT91 SAM9X60 SoCs * clk-rpi-cpufreq: clk: raspberrypi: register platform device for raspberrypi-cpufreq firmware: raspberrypi: register clk device clk: bcm283x: add driver interfacing with Raspberry Pi's firmware clk: bcm2835: remove pllb * clk-tegra: clk: tegra: Do not enable PLL_RE_VCO on Tegra210 clk: tegra: Warn if an enabled PLL is in IDDQ clk: tegra: Do not warn unnecessarily clk: tegra210: fix PLLU and PLLU_OUT1 * clk-simplify-provider.h: clk: consoldiate the __clk_get_hw() declarations clk: Unexport __clk_of_table clk: Remove ifdef for COMMON_CLK in clk-provider.h * clk-sprd: clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: sprd: Check error only for devm_regmap_init_mmio() clk: sprd: Switch from of_iomap() to devm_ioremap_resource() * clk-at91: clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: at91: sckc: add support for SAM9X60 dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller clk: at91: sckc: add support to specify registers bit offsets clk: at91: sckc: sama5d4 has no bypass support
2019-07-12clk: consoldiate the __clk_get_hw() declarationsStephen Rothwell
Without this we were getting errors like: In file included from drivers/clk/clkdev.c:22:0: drivers/clk/clk.h:36:23: error: static declaration of '__clk_get_hw' follows non-static declaration include/linux/clk-provider.h:808:16: note: previous declaration of '__clk_get_hw' was here Fixes: 59fcdce425b7 ("clk: Remove ifdef for COMMON_CLK in clk-provider.h") fixes: 73e0e496afda ("clkdev: Always allocate a struct clk and call __clk_get() w/ CCF") Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-24clk: imx8mq: Keep uart clocks on during system bootAnson Huang
Call imx_register_uart_clocks() API to keep uart clocks enabled when earlyprintk or earlycon is active. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-24clk: imx: Remove __init for imx_register_uart_clocks() APIAnson Huang
Some of i.MX SoCs' clock driver use platform driver model, and they need to call imx_register_uart_clocks() API, so imx_register_uart_clocks() API should NOT be in .init section. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 460Thomas Gleixner
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 3 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081201.897982733@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-18clk: imx6q: fix section mismatch warningArnd Bergmann
The imx6q_obtain_fixed_clk_hw lacks an __init marker, which leads to this otherwise harmless warning: WARNING: vmlinux.o(.text+0x495358): Section mismatch in reference from the function imx6q_obtain_fixed_clk_hw() to the function .init.text:imx_obtain_fixed_clock_hw() The function imx6q_obtain_fixed_clk_hw() references the function __init imx_obtain_fixed_clock_hw(). This is often because imx6q_obtain_fixed_clk_hw lacks a __init annotation or the annotation of imx_obtain_fixed_clock_hw is wrong. Fixes: 992b703b5b38 ("clk: imx6q: Switch to clk_hw based API") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()Anson Huang
i.MX8MQ clock driver uses platform driver model, better to use devm_platform_ioremap_resource() instead of of_iomap() to get IO base. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18clk: imx8mq: Use imx_check_clocks() API directlyAnson Huang
Use imx_check_clocks() API to check clocks directly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18clk: imx: Remove __init for imx_check_clocks() APIAnson Huang
Some of i.MX SoCs' clock driver use platform driver model, and they need to call imx_check_clocks() API, so imx_check_clocks() API should NOT be in .init section. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6sll: Switch to clk_hw based APIAbel Vesa
Switch the entire clk-imx6sll driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx7d: Switch to clk_hw based APIAbel Vesa
Switch the entire clk-imx7d driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6ul: Switch to clk_hw based APIAbel Vesa
Switch the entire clk-imx6ul driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6sx: Switch to clk_hw based APIAbel Vesa
Switch the entire clk-imx6sx driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6q: Switch to clk_hw based APIAbel Vesa
Switch the entire clk-imx6q driver to clk_hw based API. Add imx6q_obtain_fixed_clk_hw helper to clean up the registration of the clocks that are either found in device tree or are assigned a fixed zero rate. This switch allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx6sl: Switch to clk_hw based APIAbel Vesa
Switch the entire clk-imx6sl driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: Switch wrappers to clk_hw based APIAbel Vesa
Switch all the wrappers to clk_hw based API and rename them to indicate that. Add macros for clk based legacy users. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-07clk: imx: clk-fixup-mux: Switch to clk_hw based APIAbel Vesa
Switch the imx_clk_fixup_mux function to clk_hw based API, rename accordingly and add a macro for clk based legacy. a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-02 19:03:57 +0000