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2020-07-01drm/amd/display: Add DCN3 HUBPBhawanpreet Lakha
Add support to program the DCN3 HUBP (Display to data fabric interface pipe) HW Blocks: +--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 HUBHUBBhawanpreet Lakha
Add support to program the HUBBUB (DCN memory HUB interface) HW Blocks: +--------+ | HUBBUB | +--------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 DPPBhawanpreet Lakha
Add support to program the DCN3 DPP (Multiple pipe and plane combine) HW Blocks: +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 MPCBhawanpreet Lakha
Add support to program the DCN3 MPC (Multiple pipe and plane combine) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 OPP headerBhawanpreet Lakha
Add support to program the DCN3 OPP (Output Plane Processing) HW Blocks: +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 OPTCBhawanpreet Lakha
Add support for programming the DCN3 OPTC (Output Timing Controller) HW Blocks: +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 DCCGBhawanpreet Lakha
Add programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 CLK_MGRBhawanpreet Lakha
Adds support for handling of clocking relevant to the DCN3 block Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 DIOBhawanpreet Lakha
Add support for the DIO (Display IO) block of DCN3, which entails our stream and link encoders. HW Blocks: +--------+ | DIO | +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 chip idsBhawanpreet Lakha
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: bypass tmr when reserve c2p memoryLikun Gao
C2P memory reserved should not in tmr memory range. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: remove unnecessary check for mem trainLikun Gao
a.Check whether mem train support when try to reserve related memory. b.Remove ASIC check and atom firmware table version check as the check of firmware capability is enough to achieve that purpose. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: support memory training for sienna_cichlidLikun Gao
Add memory training support for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: reserve fb according to return value from vbiosLikun Gao
Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc), otherwise, fallback to legacy approach to check and reserve tmr block for ip discovery data and G6 memory training data respectively Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: let PMFW to handle the features disablement on BACO in V2Evan Quan
For Sienna_Cichlid, PMFW will handle the features disablement on BACO in. No need to have driver stepped in. V2: limit this for baco really Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop sienna_cichlid hardcode of using pptableLikun Gao
Drop the hardcode of sienna_cichlid which will force to use softpptable, so that it can use pptable on vbios once the value of pp_table_id get from vbios is 0. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: update smu function for sienna_cichlidLikun Gao
Add function to check whether baco is support for sienna cichlid. Remove fucntion of get clock by type with latency as it will not be called. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: update golden setting for sienna_cichlidLikun Gao
Update golden setting for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/psp: support for loading PSP SPL fwLikun Gao
Add support for loading SPL firmware. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/psp: initialization PSP SPL fwLikun Gao
Support for psp firmware header version v1_3 initialization and information print. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/psp: add structure to support PSP SPLLikun Gao
Add support for PSP SPL (Security patch level) table to support anti-rollback of FW loaded by Trusted OS. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: show gfxclk=0 in gfxoff stateKenneth Feng
The instant retrieved gfxclk value should be 0 in gfxoff state. This can be fetched with gfxoff enabled. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: enable gfxoff for sienna_cichlidLikun Gao
Enable GFXOFF for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/amdgpu: disable gfxoff to retrieve gfxclkLikun Gao
For Sienna_Cichlid, GFXOFF state puts gfx dpm into standby mode, then the gfxclk can't be retireved. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: support mclk socclk limit value set for sienna_cichlid.Likun Gao
Add support to force and unforce MCLK or SOCCLK to dpm limit value. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/sriov : Add sriov detection for sienna_cichlidshaoyunl
This is a regression due to the rebase , add sienna_cichlid sriov detection back Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: only use one gfx pipe for Sienna_CichlidLikun Gao
Only enable one gfx pipe for sienna_cichlid currently. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop jpeg instance1 dpm setupLikun Gao
VCN removed JPEG for instance 1, so drop jpeg instance1 dpm setup. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: disable runtime pm for sienna_cichlid temporarilyLikun Gao
Disable runtime pm for sienna_cichlid temporarily as BACO regression issue. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable fw ctfKenneth Feng
fw ctf can be triggered if the temperature can't be throttled below the limit. then the gpu will be powered off and the whole system will hang. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: skip GPU scheduler setup for KIQ and MES ringLikun Gao
Fix the coding error to skip GPU scheduler setup for KIQ and MES ring. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable VDDCI and MVDD for sienna_cichlidLikun Gao
Enable VDDCI and MVDD if PP_MCLK_DPM_MASK was enable for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: append pptable for sienna_cichlid (v2)Likun Gao
Add function to append powerplay table from vbios for sienna_cichlid. v2: squash in warning fix Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: and smc dpm info struct for sienna_cichlidLikun Gao
And atom_smc_dpm_info_v4_9 struct for sienna_cichlid use. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriovshaoyunl
On SRIOV run time, driver shouldn't directly access invalidation registers through MMIO. Use kiq to submit wait_reg_mem package for the invalidation Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable ULCK DS for sienna_cichlidLikun Gao
Enable uclk deep sleep for sienna_cichlid. Df cstate kicks in first, then df triggers uclk ds with the sideband. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/vcn3.0: schedule instance 0 for decode and 1 for encodeAlex Deucher
VCN3 has 2 unsymmetrical instances, i.e there're less codecs on instance 1, we use 0 for decode and 1 for encode for now Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/mes10.1: add no scheduler flag for mesAlex Deucher
We don't want a gpu scheduler for mes. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: enable DPG mode for VCN3.0Boyuan Zhang
Enable DPG mode for VCN3.0 by updating related flag. V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add workaround for issue in DPG for VCN3.0Boyuan Zhang
To workaround an issue in DPG V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0Boyuan Zhang
Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0. These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename it to be a general name. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: rename macro for VCN1.0Boyuan Zhang
Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0 These two macros are used specifically for VCN1.0, therefore rename it from general name to VCN1.0 specific name. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add internal reg offset translation for VCN inst 1Boyuan Zhang
Add range for vcn instance 1 for translation for internal register offset, which is needed for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: set indirect sram mode for VCN3.0Boyuan Zhang
Use indirect sram for secure DPG mode V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add pause DPG mode for VCN3.0Boyuan Zhang
Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add stop DPG mode for VCN3.0Boyuan Zhang
Add vcn_v3_0_stop_dpg_mode to power off in DPG mode for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add start DPG mode for VCN3.0Boyuan Zhang
Add vcn_v3_0_start_dpg_mode to setup and start VCN block in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add mc resume DPG mode for VCN3.0Boyuan Zhang
Add vcn_v3_0_mc_resume_dpg_mode to resume memory controller in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add clock gating DPG mode for VCN3.0Boyuan Zhang
Add vcn_v3_0_clock_gating_dpg_mode to enabling clock gating in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/am/powerplay: enable OUT OF BAND MONITER for sienna_cichlidLikun Gao
Enable OUT OF BAND MONITER for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-14 00:05:23 +0000