diff options
Diffstat (limited to 'drivers/pinctrl/spear/pinctrl-spear1310.c')
-rw-r--r-- | drivers/pinctrl/spear/pinctrl-spear1310.c | 2198 |
1 files changed, 2198 insertions, 0 deletions
diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c new file mode 100644 index 000000000000..12b094dc806f --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear1310.c @@ -0,0 +1,2198 @@ +/* + * Driver for the ST Microelectronics SPEAr1310 pinmux + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "pinctrl-spear.h" + +#define DRIVER_NAME "spear1310-pinmux" + +/* pins */ +static const struct pinctrl_pin_desc spear1310_pins[] = { + SPEAR_PIN_0_TO_101, + SPEAR_PIN_102_TO_245, +}; + +/* registers */ +#define PERIP_CFG 0x32C + #define MCIF_SEL_SHIFT 3 + #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT) + #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT) + #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT) + #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT) + +#define PCIE_SATA_CFG 0x3A4 + #define PCIE_SATA2_SEL_PCIE (0 << 31) + #define PCIE_SATA1_SEL_PCIE (0 << 30) + #define PCIE_SATA0_SEL_PCIE (0 << 29) + #define PCIE_SATA2_SEL_SATA (1 << 31) + #define PCIE_SATA1_SEL_SATA (1 << 30) + #define PCIE_SATA0_SEL_SATA (1 << 29) + #define SATA2_CFG_TX_CLK_EN (1 << 27) + #define SATA2_CFG_RX_CLK_EN (1 << 26) + #define SATA2_CFG_POWERUP_RESET (1 << 25) + #define SATA2_CFG_PM_CLK_EN (1 << 24) + #define SATA1_CFG_TX_CLK_EN (1 << 23) + #define SATA1_CFG_RX_CLK_EN (1 << 22) + #define SATA1_CFG_POWERUP_RESET (1 << 21) + #define SATA1_CFG_PM_CLK_EN (1 << 20) + #define SATA0_CFG_TX_CLK_EN (1 << 19) + #define SATA0_CFG_RX_CLK_EN (1 << 18) + #define SATA0_CFG_POWERUP_RESET (1 << 17) + #define SATA0_CFG_PM_CLK_EN (1 << 16) + #define PCIE2_CFG_DEVICE_PRESENT (1 << 11) + #define PCIE2_CFG_POWERUP_RESET (1 << 10) + #define PCIE2_CFG_CORE_CLK_EN (1 << 9) + #define PCIE2_CFG_AUX_CLK_EN (1 << 8) + #define PCIE1_CFG_DEVICE_PRESENT (1 << 7) + #define PCIE1_CFG_POWERUP_RESET (1 << 6) + #define PCIE1_CFG_CORE_CLK_EN (1 << 5) + #define PCIE1_CFG_AUX_CLK_EN (1 << 4) + #define PCIE0_CFG_DEVICE_PRESENT (1 << 3) + #define PCIE0_CFG_POWERUP_RESET (1 << 2) + #define PCIE0_CFG_CORE_CLK_EN (1 << 1) + #define PCIE0_CFG_AUX_CLK_EN (1 << 0) + +#define PAD_FUNCTION_EN_0 0x650 + #define PMX_UART0_MASK (1 << 1) + #define PMX_I2C0_MASK (1 << 2) + #define PMX_I2S0_MASK (1 << 3) + #define PMX_SSP0_MASK (1 << 4) + #define PMX_CLCD1_MASK (1 << 5) + #define PMX_EGPIO00_MASK (1 << 6) + #define PMX_EGPIO01_MASK (1 << 7) + #define PMX_EGPIO02_MASK (1 << 8) + #define PMX_EGPIO03_MASK (1 << 9) + #define PMX_EGPIO04_MASK (1 << 10) + #define PMX_EGPIO05_MASK (1 << 11) + #define PMX_EGPIO06_MASK (1 << 12) + #define PMX_EGPIO07_MASK (1 << 13) + #define PMX_EGPIO08_MASK (1 << 14) + #define PMX_EGPIO09_MASK (1 << 15) + #define PMX_SMI_MASK (1 << 16) + #define PMX_NAND8_MASK (1 << 17) + #define PMX_GMIICLK_MASK (1 << 18) + #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19) + #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20) + #define PMX_GMIID47_MASK (1 << 21) + #define PMX_MDC_MDIO_MASK (1 << 22) + #define PMX_MCI_DATA8_15_MASK (1 << 23) + #define PMX_NFAD23_MASK (1 << 24) + #define PMX_NFAD24_MASK (1 << 25) + #define PMX_NFAD25_MASK (1 << 26) + #define PMX_NFCE3_MASK (1 << 27) + #define PMX_NFWPRT3_MASK (1 << 28) + #define PMX_NFRSTPWDWN0_MASK (1 << 29) + #define PMX_NFRSTPWDWN1_MASK (1 << 30) + #define PMX_NFRSTPWDWN2_MASK (1 << 31) + +#define PAD_FUNCTION_EN_1 0x654 + #define PMX_NFRSTPWDWN3_MASK (1 << 0) + #define PMX_SMINCS2_MASK (1 << 1) + #define PMX_SMINCS3_MASK (1 << 2) + #define PMX_CLCD2_MASK (1 << 3) + #define PMX_KBD_ROWCOL68_MASK (1 << 4) + #define PMX_EGPIO10_MASK (1 << 5) + #define PMX_EGPIO11_MASK (1 << 6) + #define PMX_EGPIO12_MASK (1 << 7) + #define PMX_EGPIO13_MASK (1 << 8) + #define PMX_EGPIO14_MASK (1 << 9) + #define PMX_EGPIO15_MASK (1 << 10) + #define PMX_UART0_MODEM_MASK (1 << 11) + #define PMX_GPT0_TMR0_MASK (1 << 12) + #define PMX_GPT0_TMR1_MASK (1 << 13) + #define PMX_GPT1_TMR0_MASK (1 << 14) + #define PMX_GPT1_TMR1_MASK (1 << 15) + #define PMX_I2S1_MASK (1 << 16) + #define PMX_KBD_ROWCOL25_MASK (1 << 17) + #define PMX_NFIO8_15_MASK (1 << 18) + #define PMX_KBD_COL1_MASK (1 << 19) + #define PMX_NFCE1_MASK (1 << 20) + #define PMX_KBD_COL0_MASK (1 << 21) + #define PMX_NFCE2_MASK (1 << 22) + #define PMX_KBD_ROW1_MASK (1 << 23) + #define PMX_NFWPRT1_MASK (1 << 24) + #define PMX_KBD_ROW0_MASK (1 << 25) + #define PMX_NFWPRT2_MASK (1 << 26) + #define PMX_MCIDATA0_MASK (1 << 27) + #define PMX_MCIDATA1_MASK (1 << 28) + #define PMX_MCIDATA2_MASK (1 << 29) + #define PMX_MCIDATA3_MASK (1 << 30) + #define PMX_MCIDATA4_MASK (1 << 31) + +#define PAD_FUNCTION_EN_2 0x658 + #define PMX_MCIDATA5_MASK (1 << 0) + #define PMX_MCIDATA6_MASK (1 << 1) + #define PMX_MCIDATA7_MASK (1 << 2) + #define PMX_MCIDATA1SD_MASK (1 << 3) + #define PMX_MCIDATA2SD_MASK (1 << 4) + #define PMX_MCIDATA3SD_MASK (1 << 5) + #define PMX_MCIADDR0ALE_MASK (1 << 6) + #define PMX_MCIADDR1CLECLK_MASK (1 << 7) + #define PMX_MCIADDR2_MASK (1 << 8) + #define PMX_MCICECF_MASK (1 << 9) + #define PMX_MCICEXD_MASK (1 << 10) + #define PMX_MCICESDMMC_MASK (1 << 11) + #define PMX_MCICDCF1_MASK (1 << 12) + #define PMX_MCICDCF2_MASK (1 << 13) + #define PMX_MCICDXD_MASK (1 << 14) + #define PMX_MCICDSDMMC_MASK (1 << 15) + #define PMX_MCIDATADIR_MASK (1 << 16) + #define PMX_MCIDMARQWP_MASK (1 << 17) + #define PMX_MCIIORDRE_MASK (1 << 18) + #define PMX_MCIIOWRWE_MASK (1 << 19) + #define PMX_MCIRESETCF_MASK (1 << 20) + #define PMX_MCICS0CE_MASK (1 << 21) + #define PMX_MCICFINTR_MASK (1 << 22) + #define PMX_MCIIORDY_MASK (1 << 23) + #define PMX_MCICS1_MASK (1 << 24) + #define PMX_MCIDMAACK_MASK (1 << 25) + #define PMX_MCISDCMD_MASK (1 << 26) + #define PMX_MCILEDS_MASK (1 << 27) + #define PMX_TOUCH_XY_MASK (1 << 28) + #define PMX_SSP0_CS0_MASK (1 << 29) + #define PMX_SSP0_CS1_2_MASK (1 << 30) + +/* combined macros */ +#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \ + PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ + PMX_RXCLK_RDV_TXEN_D03_MASK | \ + PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK) + +#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \ + PMX_EGPIO02_MASK | \ + PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \ + PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \ + PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \ + PMX_EGPIO09_MASK) +#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \ + PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \ + PMX_EGPIO14_MASK | PMX_EGPIO15_MASK) + +#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ + PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \ + PMX_KBD_COL1_MASK) + +#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \ + PMX_NFAD24_MASK | PMX_NFAD25_MASK | \ + PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \ + PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \ + PMX_NFCE3_MASK) +#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK + +#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK) +#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \ + PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \ + PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ + PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK) + +#define PMX_MCIFALL_1_MASK 0xF8000000 +#define PMX_MCIFALL_2_MASK 0x0FFFFFFF + +#define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \ + PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \ + PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \ + PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \ + PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \ + PMX_NFCE2_MASK) +#define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ + PMX_SSP0_CS1_2_MASK) + +#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK) +#define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \ + PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ + PMX_GMIID47_MASK) +#define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\ + PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \ + PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK) +#define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ + PMX_SSP0_CS1_2_MASK) + +#define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \ + PCIE##x##_CFG_AUX_CLK_EN | \ + PCIE##x##_CFG_CORE_CLK_EN | \ + PCIE##x##_CFG_POWERUP_RESET | \ + PCIE##x##_CFG_DEVICE_PRESENT) +#define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \ + SATA##x##_CFG_PM_CLK_EN | \ + SATA##x##_CFG_POWERUP_RESET | \ + SATA##x##_CFG_RX_CLK_EN | \ + SATA##x##_CFG_TX_CLK_EN) + +/* Pad multiplexing for i2c0 device */ +static const unsigned i2c0_pins[] = { 102, 103 }; +static struct spear_muxreg i2c0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_I2C0_MASK, + .val = PMX_I2C0_MASK, + }, +}; + +static struct spear_modemux i2c0_modemux[] = { + { + .muxregs = i2c0_muxreg, + .nmuxregs = ARRAY_SIZE(i2c0_muxreg), + }, +}; + +static struct spear_pingroup i2c0_pingroup = { + .name = "i2c0_grp", + .pins = i2c0_pins, + .npins = ARRAY_SIZE(i2c0_pins), + .modemuxs = i2c0_modemux, + .nmodemuxs = ARRAY_SIZE(i2c0_modemux), +}; + +static const char *const i2c0_grps[] = { "i2c0_grp" }; +static struct spear_function i2c0_function = { + .name = "i2c0", + .groups = i2c0_grps, + .ngroups = ARRAY_SIZE(i2c0_grps), +}; + +/* Pad multiplexing for ssp0 device */ +static const unsigned ssp0_pins[] = { 109, 110, 111, 112 }; +static struct spear_muxreg ssp0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_SSP0_MASK, + .val = PMX_SSP0_MASK, + }, +}; + +static struct spear_modemux ssp0_modemux[] = { + { + .muxregs = ssp0_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_muxreg), + }, +}; + +static struct spear_pingroup ssp0_pingroup = { + .name = "ssp0_grp", + .pins = ssp0_pins, + .npins = ARRAY_SIZE(ssp0_pins), + .modemuxs = ssp0_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_modemux), +}; + +/* Pad multiplexing for ssp0_cs0 device */ +static const unsigned ssp0_cs0_pins[] = { 96 }; +static struct spear_muxreg ssp0_cs0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_SSP0_CS0_MASK, + .val = PMX_SSP0_CS0_MASK, + }, +}; + +static struct spear_modemux ssp0_cs0_modemux[] = { + { + .muxregs = ssp0_cs0_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg), + }, +}; + +static struct spear_pingroup ssp0_cs0_pingroup = { + .name = "ssp0_cs0_grp", + .pins = ssp0_cs0_pins, + .npins = ARRAY_SIZE(ssp0_cs0_pins), + .modemuxs = ssp0_cs0_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux), +}; + +/* ssp0_cs1_2 device */ +static const unsigned ssp0_cs1_2_pins[] = { 94, 95 }; +static struct spear_muxreg ssp0_cs1_2_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_SSP0_CS1_2_MASK, + .val = PMX_SSP0_CS1_2_MASK, + }, +}; + +static struct spear_modemux ssp0_cs1_2_modemux[] = { + { + .muxregs = ssp0_cs1_2_muxreg, + .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg), + }, +}; + +static struct spear_pingroup ssp0_cs1_2_pingroup = { + .name = "ssp0_cs1_2_grp", + .pins = ssp0_cs1_2_pins, + .npins = ARRAY_SIZE(ssp0_cs1_2_pins), + .modemuxs = ssp0_cs1_2_modemux, + .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux), +}; + +static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp", + "ssp0_cs1_2_grp" }; +static struct spear_function ssp0_function = { + .name = "ssp0", + .groups = ssp0_grps, + .ngroups = ARRAY_SIZE(ssp0_grps), +}; + +/* Pad multiplexing for i2s0 device */ +static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 }; +static struct spear_muxreg i2s0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_I2S0_MASK, + .val = PMX_I2S0_MASK, + }, +}; + +static struct spear_modemux i2s0_modemux[] = { + { + .muxregs = i2s0_muxreg, + .nmuxregs = ARRAY_SIZE(i2s0_muxreg), + }, +}; + +static struct spear_pingroup i2s0_pingroup = { + .name = "i2s0_grp", + .pins = i2s0_pins, + .npins = ARRAY_SIZE(i2s0_pins), + .modemuxs = i2s0_modemux, + .nmodemuxs = ARRAY_SIZE(i2s0_modemux), +}; + +static const char *const i2s0_grps[] = { "i2s0_grp" }; +static struct spear_function i2s0_function = { + .name = "i2s0", + .groups = i2s0_grps, + .ngroups = ARRAY_SIZE(i2s0_grps), +}; + +/* Pad multiplexing for i2s1 device */ +static const unsigned i2s1_pins[] = { 0, 1, 2, 3 }; +static struct spear_muxreg i2s1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_I2S1_MASK, + .val = PMX_I2S1_MASK, + }, +}; + +static struct spear_modemux i2s1_modemux[] = { + { + .muxregs = i2s1_muxreg, + .nmuxregs = ARRAY_SIZE(i2s1_muxreg), + }, +}; + +static struct spear_pingroup i2s1_pingroup = { + .name = "i2s1_grp", + .pins = i2s1_pins, + .npins = ARRAY_SIZE(i2s1_pins), + .modemuxs = i2s1_modemux, + .nmodemuxs = ARRAY_SIZE(i2s1_modemux), +}; + +static const char *const i2s1_grps[] = { "i2s1_grp" }; +static struct spear_function i2s1_function = { + .name = "i2s1", + .groups = i2s1_grps, + .ngroups = ARRAY_SIZE(i2s1_grps), +}; + +/* Pad multiplexing for clcd device */ +static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120, + 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, + 135, 136, 137, 138, 139, 140, 141, 142 }; +static struct spear_muxreg clcd_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_CLCD1_MASK, + .val = PMX_CLCD1_MASK, + }, +}; + +static struct spear_modemux clcd_modemux[] = { + { + .muxregs = clcd_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_muxreg), + }, +}; + +static struct spear_pingroup clcd_pingroup = { + .name = "clcd_grp", + .pins = clcd_pins, + .npins = ARRAY_SIZE(clcd_pins), + .modemuxs = clcd_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_modemux), +}; + +static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52 }; +static struct spear_muxreg clcd_high_res_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_CLCD2_MASK, + .val = PMX_CLCD2_MASK, + }, +}; + +static struct spear_modemux clcd_high_res_modemux[] = { + { + .muxregs = clcd_high_res_muxreg, + .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg), + }, +}; + +static struct spear_pingroup clcd_high_res_pingroup = { + .name = "clcd_high_res_grp", + .pins = clcd_high_res_pins, + .npins = ARRAY_SIZE(clcd_high_res_pins), + .modemuxs = clcd_high_res_modemux, + .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux), +}; + +static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res" }; +static struct spear_function clcd_function = { + .name = "clcd", + .groups = clcd_grps, + .ngroups = ARRAY_SIZE(clcd_grps), +}; + +static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145, + 146, 147, 148, 149, 150, 151, 152 }; +static struct spear_muxreg arm_gpio_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_EGPIO_0_GRP_MASK, + .val = PMX_EGPIO_0_GRP_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_EGPIO_1_GRP_MASK, + .val = PMX_EGPIO_1_GRP_MASK, + }, +}; + +static struct spear_modemux arm_gpio_modemux[] = { + { + .muxregs = arm_gpio_muxreg, + .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg), + }, +}; + +static struct spear_pingroup arm_gpio_pingroup = { + .name = "arm_gpio_grp", + .pins = arm_gpio_pins, + .npins = ARRAY_SIZE(arm_gpio_pins), + .modemuxs = arm_gpio_modemux, + .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux), +}; + +static const char *const arm_gpio_grps[] = { "arm_gpio_grp" }; +static struct spear_function arm_gpio_function = { + .name = "arm_gpio", + .groups = arm_gpio_grps, + .ngroups = ARRAY_SIZE(arm_gpio_grps), +}; + +/* Pad multiplexing for smi 2 chips device */ +static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 }; +static struct spear_muxreg smi_2_chips_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_SMI_MASK, + .val = PMX_SMI_MASK, + }, +}; + +static struct spear_modemux smi_2_chips_modemux[] = { + { + .muxregs = smi_2_chips_muxreg, + .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg), + }, +}; + +static struct spear_pingroup smi_2_chips_pingroup = { + .name = "smi_2_chips_grp", + .pins = smi_2_chips_pins, + .npins = ARRAY_SIZE(smi_2_chips_pins), + .modemuxs = smi_2_chips_modemux, + .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux), +}; + +static const unsigned smi_4_chips_pins[] = { 54, 55 }; +static struct spear_muxreg smi_4_chips_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_SMI_MASK, + .val = PMX_SMI_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, + .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, + }, +}; + +static struct spear_modemux smi_4_chips_modemux[] = { + { + .muxregs = smi_4_chips_muxreg, + .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg), + }, +}; + +static struct spear_pingroup smi_4_chips_pingroup = { + .name = "smi_4_chips_grp", + .pins = smi_4_chips_pins, + .npins = ARRAY_SIZE(smi_4_chips_pins), + .modemuxs = smi_4_chips_modemux, + .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux), +}; + +static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" }; +static struct spear_function smi_function = { + .name = "smi", + .groups = smi_grps, + .ngroups = ARRAY_SIZE(smi_grps), +}; + +/* Pad multiplexing for gmii device */ +static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180, + 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, + 195, 196, 197, 198, 199, 200 }; +static struct spear_muxreg gmii_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_GMII_MASK, + .val = PMX_GMII_MASK, + }, +}; + +static struct spear_modemux gmii_modemux[] = { + { + .muxregs = gmii_muxreg, + .nmuxregs = ARRAY_SIZE(gmii_muxreg), + }, +}; + +static struct spear_pingroup gmii_pingroup = { + .name = "gmii_grp", + .pins = gmii_pins, + .npins = ARRAY_SIZE(gmii_pins), + .modemuxs = gmii_modemux, + .nmodemuxs = ARRAY_SIZE(gmii_modemux), +}; + +static const char *const gmii_grps[] = { "gmii_grp" }; +static struct spear_function gmii_function = { + .name = "gmii", + .groups = gmii_grps, + .ngroups = ARRAY_SIZE(gmii_grps), +}; + +/* Pad multiplexing for rgmii device */ +static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, + 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175, + 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 }; +static struct spear_muxreg rgmii_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_RGMII_REG0_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_RGMII_REG1_MASK, + .val = 0, + }, { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_RGMII_REG2_MASK, + .val = 0, + }, +}; + +static struct spear_modemux rgmii_modemux[] = { + { + .muxregs = rgmii_muxreg, + .nmuxregs = ARRAY_SIZE(rgmii_muxreg), + }, +}; + +static struct spear_pingroup rgmii_pingroup = { + .name = "rgmii_grp", + .pins = rgmii_pins, + .npins = ARRAY_SIZE(rgmii_pins), + .modemuxs = rgmii_modemux, + .nmodemuxs = ARRAY_SIZE(rgmii_modemux), +}; + +static const char *const rgmii_grps[] = { "rgmii_grp" }; +static struct spear_function rgmii_function = { + .name = "rgmii", + .groups = rgmii_grps, + .ngroups = ARRAY_SIZE(rgmii_grps), +}; + +/* Pad multiplexing for smii_0_1_2 device */ +static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, + 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, + 51, 52, 53, 54, 55 }; +static struct spear_muxreg smii_0_1_2_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_SMII_0_1_2_MASK, + .val = 0, + }, +}; + +static struct spear_modemux smii_0_1_2_modemux[] = { + { + .muxregs = smii_0_1_2_muxreg, + .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg), + }, +}; + +static struct spear_pingroup smii_0_1_2_pingroup = { + .name = "smii_0_1_2_grp", + .pins = smii_0_1_2_pins, + .npins = ARRAY_SIZE(smii_0_1_2_pins), + .modemuxs = smii_0_1_2_modemux, + .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux), +}; + +static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" }; +static struct spear_function smii_0_1_2_function = { + .name = "smii_0_1_2", + .groups = smii_0_1_2_grps, + .ngroups = ARRAY_SIZE(smii_0_1_2_grps), +}; + +/* Pad multiplexing for ras_mii_txclk device */ +static const unsigned ras_mii_txclk_pins[] = { 98, 99 }; +static struct spear_muxreg ras_mii_txclk_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_NFCE2_MASK, + .val = 0, + }, +}; + +static struct spear_modemux ras_mii_txclk_modemux[] = { + { + .muxregs = ras_mii_txclk_muxreg, + .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg), + }, +}; + +static struct spear_pingroup ras_mii_txclk_pingroup = { + .name = "ras_mii_txclk_grp", + .pins = ras_mii_txclk_pins, + .npins = ARRAY_SIZE(ras_mii_txclk_pins), + .modemuxs = ras_mii_txclk_modemux, + .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux), +}; + +static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" }; +static struct spear_function ras_mii_txclk_function = { + .name = "ras_mii_txclk", + .groups = ras_mii_txclk_grps, + .ngroups = ARRAY_SIZE(ras_mii_txclk_grps), +}; + +/* Pad multiplexing for nand 8bit device (cs0 only) */ +static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64, + 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, + 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, + 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, + 212 }; +static struct spear_muxreg nand_8bit_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_NAND8BIT_0_MASK, + .val = PMX_NAND8BIT_0_MASK, + }, { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_NAND8BIT_1_MASK, + .val = PMX_NAND8BIT_1_MASK, + }, +}; + +static struct spear_modemux nand_8bit_modemux[] = { + { + .muxregs = nand_8bit_muxreg, + .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg), + }, +}; + +static struct spear_pingroup nand_8bit_pingroup = { + .name = "nand_8bit_grp", + .pins = nand_8bit_pins, + .npins = ARRAY_SIZE(nand_8bit_pins), + .modemuxs = nand_8bit_modemux, + .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux), +}; + +/* Pad multiplexing for nand 16bit device */ +static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209, + 210 }; +static struct spear_muxreg nand_16bit_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_NAND16BIT_1_MASK, + .val = PMX_NAND16BIT_1_MASK, + }, +}; + +static struct spear_modemux nand_16bit_modemux[] = { + { + .muxregs = nand_16bit_muxreg, + .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg), + }, +}; + +static struct spear_pingroup nand_16bit_pingroup = { + .name = "nand_16bit_grp", + .pins = nand_16bit_pins, + .npins = ARRAY_SIZE(nand_16bit_pins), + .modemuxs = nand_16bit_modemux, + .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux), +}; + +/* Pad multiplexing for nand 4 chips */ +static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 }; +static struct spear_muxreg nand_4_chips_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_NAND_4CHIPS_MASK, + .val = PMX_NAND_4CHIPS_MASK, + }, +}; + +static struct spear_modemux nand_4_chips_modemux[] = { + { + .muxregs = nand_4_chips_muxreg, + .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg), + }, +}; + +static struct spear_pingroup nand_4_chips_pingroup = { + .name = "nand_4_chips_grp", + .pins = nand_4_chips_pins, + .npins = ARRAY_SIZE(nand_4_chips_pins), + .modemuxs = nand_4_chips_modemux, + .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux), +}; + +static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp", + "nand_4_chips_grp" }; +static struct spear_function nand_function = { + .name = "nand", + .groups = nand_grps, + .ngroups = ARRAY_SIZE(nand_grps), +}; + +/* Pad multiplexing for keyboard_6x6 device */ +static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212 }; +static struct spear_muxreg keyboard_6x6_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK | + PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK | + PMX_NFWPRT2_MASK, + .val = PMX_KEYBOARD_6X6_MASK, + }, +}; + +static struct spear_modemux keyboard_6x6_modemux[] = { + { + .muxregs = keyboard_6x6_muxreg, + .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg), + }, +}; + +static struct spear_pingroup keyboard_6x6_pingroup = { + .name = "keyboard_6x6_grp", + .pins = keyboard_6x6_pins, + .npins = ARRAY_SIZE(keyboard_6x6_pins), + .modemuxs = keyboard_6x6_modemux, + .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux), +}; + +/* Pad multiplexing for keyboard_rowcol6_8 device */ +static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 }; +static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_KBD_ROWCOL68_MASK, + .val = PMX_KBD_ROWCOL68_MASK, + }, +}; + +static struct spear_modemux keyboard_rowcol6_8_modemux[] = { + { + .muxregs = keyboard_rowcol6_8_muxreg, + .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg), + }, +}; + +static struct spear_pingroup keyboard_rowcol6_8_pingroup = { + .name = "keyboard_rowcol6_8_grp", + .pins = keyboard_rowcol6_8_pins, + .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins), + .modemuxs = keyboard_rowcol6_8_modemux, + .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux), +}; + +static const char *const keyboard_grps[] = { "keyboard_6x6_grp", + "keyboard_rowcol6_8_grp" }; +static struct spear_function keyboard_function = { + .name = "keyboard", + .groups = keyboard_grps, + .ngroups = ARRAY_SIZE(keyboard_grps), +}; + +/* Pad multiplexing for uart0 device */ +static const unsigned uart0_pins[] = { 100, 101 }; +static struct spear_muxreg uart0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_0, + .mask = PMX_UART0_MASK, + .val = PMX_UART0_MASK, + }, +}; + +static struct spear_modemux uart0_modemux[] = { + { + .muxregs = uart0_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_muxreg), + }, +}; + +static struct spear_pingroup uart0_pingroup = { + .name = "uart0_grp", + .pins = uart0_pins, + .npins = ARRAY_SIZE(uart0_pins), + .modemuxs = uart0_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_modemux), +}; + +/* Pad multiplexing for uart0_modem device */ +static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 }; +static struct spear_muxreg uart0_modem_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_UART0_MODEM_MASK, + .val = PMX_UART0_MODEM_MASK, + }, +}; + +static struct spear_modemux uart0_modem_modemux[] = { + { + .muxregs = uart0_modem_muxreg, + .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg), + }, +}; + +static struct spear_pingroup uart0_modem_pingroup = { + .name = "uart0_modem_grp", + .pins = uart0_modem_pins, + .npins = ARRAY_SIZE(uart0_modem_pins), + .modemuxs = uart0_modem_modemux, + .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux), +}; + +static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" }; +static struct spear_function uart0_function = { + .name = "uart0", + .groups = uart0_grps, + .ngroups = ARRAY_SIZE(uart0_grps), +}; + +/* Pad multiplexing for gpt0_tmr0 device */ +static const unsigned gpt0_tmr0_pins[] = { 10, 11 }; +static struct spear_muxreg gpt0_tmr0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_GPT0_TMR0_MASK, + .val = PMX_GPT0_TMR0_MASK, + }, +}; + +static struct spear_modemux gpt0_tmr0_modemux[] = { + { + .muxregs = gpt0_tmr0_muxreg, + .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg), + }, +}; + +static struct spear_pingroup gpt0_tmr0_pingroup = { + .name = "gpt0_tmr0_grp", + .pins = gpt0_tmr0_pins, + .npins = ARRAY_SIZE(gpt0_tmr0_pins), + .modemuxs = gpt0_tmr0_modemux, + .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux), +}; + +/* Pad multiplexing for gpt0_tmr1 device */ +static const unsigned gpt0_tmr1_pins[] = { 8, 9 }; +static struct spear_muxreg gpt0_tmr1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_GPT0_TMR1_MASK, + .val = PMX_GPT0_TMR1_MASK, + }, +}; + +static struct spear_modemux gpt0_tmr1_modemux[] = { + { + .muxregs = gpt0_tmr1_muxreg, + .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg), + }, +}; + +static struct spear_pingroup gpt0_tmr1_pingroup = { + .name = "gpt0_tmr1_grp", + .pins = gpt0_tmr1_pins, + .npins = ARRAY_SIZE(gpt0_tmr1_pins), + .modemuxs = gpt0_tmr1_modemux, + .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux), +}; + +static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" }; +static struct spear_function gpt0_function = { + .name = "gpt0", + .groups = gpt0_grps, + .ngroups = ARRAY_SIZE(gpt0_grps), +}; + +/* Pad multiplexing for gpt1_tmr0 device */ +static const unsigned gpt1_tmr0_pins[] = { 6, 7 }; +static struct spear_muxreg gpt1_tmr0_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_GPT1_TMR0_MASK, + .val = PMX_GPT1_TMR0_MASK, + }, +}; + +static struct spear_modemux gpt1_tmr0_modemux[] = { + { + .muxregs = gpt1_tmr0_muxreg, + .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg), + }, +}; + +static struct spear_pingroup gpt1_tmr0_pingroup = { + .name = "gpt1_tmr0_grp", + .pins = gpt1_tmr0_pins, + .npins = ARRAY_SIZE(gpt1_tmr0_pins), + .modemuxs = gpt1_tmr0_modemux, + .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux), +}; + +/* Pad multiplexing for gpt1_tmr1 device */ +static const unsigned gpt1_tmr1_pins[] = { 4, 5 }; +static struct spear_muxreg gpt1_tmr1_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_1, + .mask = PMX_GPT1_TMR1_MASK, + .val = PMX_GPT1_TMR1_MASK, + }, +}; + +static struct spear_modemux gpt1_tmr1_modemux[] = { + { + .muxregs = gpt1_tmr1_muxreg, + .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg), + }, +}; + +static struct spear_pingroup gpt1_tmr1_pingroup = { + .name = "gpt1_tmr1_grp", + .pins = gpt1_tmr1_pins, + .npins = ARRAY_SIZE(gpt1_tmr1_pins), + .modemuxs = gpt1_tmr1_modemux, + .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux), +}; + +static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" }; +static struct spear_function gpt1_function = { + .name = "gpt1", + .groups = gpt1_grps, + .ngroups = ARRAY_SIZE(gpt1_grps), +}; + +/* Pad multiplexing for mcif device */ +static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214, + 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, + 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, + 243, 244, 245 }; +#define MCIF_MUXREG \ + { \ + .reg = PAD_FUNCTION_EN_0, \ + .mask = PMX_MCI_DATA8_15_MASK, \ + .val = PMX_MCI_DATA8_15_MASK, \ + }, { \ + .reg = PAD_FUNCTION_EN_1, \ + .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ + PMX_NFWPRT2_MASK, \ + .val = PMX_MCIFALL_1_MASK, \ + }, { \ + .reg = PAD_FUNCTION_EN_2, \ + .mask = PMX_MCIFALL_2_MASK, \ + .val = PMX_MCIFALL_2_MASK, \ + } + +/* sdhci device */ +static struct spear_muxreg sdhci_muxreg[] = { + MCIF_MUXREG, + { + .reg = PERIP_CFG, + .mask = MCIF_SEL_MASK, + .val = MCIF_SEL_SD, + }, +}; + +static struct spear_modemux sdhci_modemux[] = { + { + .muxregs = sdhci_muxreg, + .nmuxregs = ARRAY_SIZE(sdhci_muxreg), + }, +}; + +static struct spear_pingroup sdhci_pingroup = { + .name = "sdhci_grp", + .pins = mcif_pins, + .npins = ARRAY_SIZE(mcif_pins), + .modemuxs = sdhci_modemux, + .nmodemuxs = ARRAY_SIZE(sdhci_modemux), +}; + +static const char *const sdhci_grps[] = { "sdhci_grp" }; +static struct spear_function sdhci_function = { + .name = "sdhci", + .groups = sdhci_grps, + .ngroups = ARRAY_SIZE(sdhci_grps), +}; + +/* cf device */ +static struct spear_muxreg cf_muxreg[] = { + MCIF_MUXREG, + { + .reg = PERIP_CFG, + .mask = MCIF_SEL_MASK, + .val = MCIF_SEL_CF, + }, +}; + +static struct spear_modemux cf_modemux[] = { + { + .muxregs = cf_muxreg, + .nmuxregs = ARRAY_SIZE(cf_muxreg), + }, +}; + +static struct spear_pingroup cf_pingroup = { + .name = "cf_grp", + .pins = mcif_pins, + .npins = ARRAY_SIZE(mcif_pins), + .modemuxs = cf_modemux, + .nmodemuxs = ARRAY_SIZE(cf_modemux), +}; + +static const char *const cf_grps[] = { "cf_grp" }; +static struct spear_function cf_function = { + .name = "cf", + .groups = cf_grps, + .ngroups = ARRAY_SIZE(cf_grps), +}; + +/* xd device */ +static struct spear_muxreg xd_muxreg[] = { + MCIF_MUXREG, + { + .reg = PERIP_CFG, + .mask = MCIF_SEL_MASK, + .val = MCIF_SEL_XD, + }, +}; + +static struct spear_modemux xd_modemux[] = { + { + .muxregs = xd_muxreg, + .nmuxregs = ARRAY_SIZE(xd_muxreg), + }, +}; + +static struct spear_pingroup xd_pingroup = { + .name = "xd_grp", + .pins = mcif_pins, + .npins = ARRAY_SIZE(mcif_pins), + .modemuxs = xd_modemux, + .nmodemuxs = ARRAY_SIZE(xd_modemux), +}; + +static const char *const xd_grps[] = { "xd_grp" }; +static struct spear_function xd_function = { + .name = "xd", + .groups = xd_grps, + .ngroups = ARRAY_SIZE(xd_grps), +}; + +/* Pad multiplexing for touch_xy device */ +static const unsigned touch_xy_pins[] = { 97 }; +static struct spear_muxreg touch_xy_muxreg[] = { + { + .reg = PAD_FUNCTION_EN_2, + .mask = PMX_TOUCH_XY_MASK, + .val = PMX_TOUCH_XY_MASK, + }, +}; + +static struct spear_modemux touch_xy_modemux[] = { + { + .muxregs = touch_xy_muxreg, + .nmuxregs = ARRAY_SIZE(touch_xy_muxreg), + }, +}; + +static struct spear_pingroup touch_xy_pingroup = { + .name = "touch |