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path: root/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
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Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c')
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c32
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
index 1f6d800dd1be..9d97080a9d17 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
@@ -29,8 +29,22 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
{ CUDBG_MBOX_LOG, cudbg_collect_mbox_log },
{ CUDBG_DEV_LOG, cudbg_collect_fw_devlog },
{ CUDBG_REG_DUMP, cudbg_collect_reg_dump },
+ { CUDBG_CIM_IBQ_TP0, cudbg_collect_cim_ibq_tp0 },
+ { CUDBG_CIM_IBQ_TP1, cudbg_collect_cim_ibq_tp1 },
+ { CUDBG_CIM_IBQ_ULP, cudbg_collect_cim_ibq_ulp },
+ { CUDBG_CIM_IBQ_SGE0, cudbg_collect_cim_ibq_sge0 },
+ { CUDBG_CIM_IBQ_SGE1, cudbg_collect_cim_ibq_sge1 },
+ { CUDBG_CIM_IBQ_NCSI, cudbg_collect_cim_ibq_ncsi },
+ { CUDBG_CIM_OBQ_ULP0, cudbg_collect_cim_obq_ulp0 },
+ { CUDBG_CIM_OBQ_ULP1, cudbg_collect_cim_obq_ulp1 },
+ { CUDBG_CIM_OBQ_ULP2, cudbg_collect_cim_obq_ulp2 },
+ { CUDBG_CIM_OBQ_ULP3, cudbg_collect_cim_obq_ulp3 },
+ { CUDBG_CIM_OBQ_SGE, cudbg_collect_cim_obq_sge },
+ { CUDBG_CIM_OBQ_NCSI, cudbg_collect_cim_obq_ncsi },
{ CUDBG_TP_INDIRECT, cudbg_collect_tp_indirect },
{ CUDBG_SGE_INDIRECT, cudbg_collect_sge_indirect },
+ { CUDBG_CIM_OBQ_RXQ0, cudbg_collect_obq_sge_rx_q0 },
+ { CUDBG_CIM_OBQ_RXQ1, cudbg_collect_obq_sge_rx_q1 },
{ CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect },
{ CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect },
{ CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect },
@@ -59,6 +73,24 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
case CUDBG_DEV_LOG:
len = adap->params.devlog.size;
break;
+ case CUDBG_CIM_IBQ_TP0:
+ case CUDBG_CIM_IBQ_TP1:
+ case CUDBG_CIM_IBQ_ULP:
+ case CUDBG_CIM_IBQ_SGE0:
+ case CUDBG_CIM_IBQ_SGE1:
+ case CUDBG_CIM_IBQ_NCSI:
+ len = CIM_IBQ_SIZE * 4 * sizeof(u32);
+ break;
+ case CUDBG_CIM_OBQ_ULP0:
+ case CUDBG_CIM_OBQ_ULP1:
+ case CUDBG_CIM_OBQ_ULP2:
+ case CUDBG_CIM_OBQ_ULP3:
+ case CUDBG_CIM_OBQ_SGE:
+ case CUDBG_CIM_OBQ_NCSI:
+ case CUDBG_CIM_OBQ_RXQ0:
+ case CUDBG_CIM_OBQ_RXQ1:
+ len = 6 * CIM_OBQ_SIZE * 4 * sizeof(u32);
+ break;
case CUDBG_EDC0:
value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
if (value & EDRAM0_ENABLE_F) {