diff options
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r-- | arch/blackfin/mach-common/Makefile | 17 | ||||
-rw-r--r-- | arch/blackfin/mach-common/arch_checks.c | 66 | ||||
-rw-r--r-- | arch/blackfin/mach-common/cache-c.c | 85 | ||||
-rw-r--r-- | arch/blackfin/mach-common/cache.S | 124 | ||||
-rw-r--r-- | arch/blackfin/mach-common/clock.h | 28 | ||||
-rw-r--r-- | arch/blackfin/mach-common/clocks-init.c | 121 | ||||
-rw-r--r-- | arch/blackfin/mach-common/dpmc.c | 164 | ||||
-rw-r--r-- | arch/blackfin/mach-common/dpmc_modes.S | 320 | ||||
-rw-r--r-- | arch/blackfin/mach-common/entry.S | 1711 | ||||
-rw-r--r-- | arch/blackfin/mach-common/head.S | 229 | ||||
-rw-r--r-- | arch/blackfin/mach-common/interrupt.S | 326 | ||||
-rw-r--r-- | arch/blackfin/mach-common/ints-priority.c | 1366 | ||||
-rw-r--r-- | arch/blackfin/mach-common/pm.c | 301 | ||||
-rw-r--r-- | arch/blackfin/mach-common/scb-init.c | 52 | ||||
-rw-r--r-- | arch/blackfin/mach-common/smp.c | 432 |
15 files changed, 0 insertions, 5342 deletions
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile deleted file mode 100644 index fcef1c8e117f..000000000000 --- a/arch/blackfin/mach-common/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/mach-common/Makefile -# - -obj-y := \ - cache.o cache-c.o entry.o head.o \ - interrupt.o arch_checks.o ints-priority.o - -obj-$(CONFIG_PM) += pm.o -ifneq ($(CONFIG_BF60x),y) -obj-$(CONFIG_PM) += dpmc_modes.o -endif -obj-$(CONFIG_SCB_PRIORITY) += scb-init.o -obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o -obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c deleted file mode 100644 index d8643fdd0fcf..000000000000 --- a/arch/blackfin/mach-common/arch_checks.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Do some checking to make sure things are OK - * - * Copyright 2007-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <asm/fixed_code.h> -#include <mach/anomaly.h> -#include <asm/clocks.h> - -#ifdef CONFIG_BFIN_KERNEL_CLOCK - -# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ) -# error "VCO selected is more than maximum value. Please change the VCO multipler" -# endif - -# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ) -# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" -# endif - -# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ) -# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" -# endif - -# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ) -# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK" -# endif - -# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) -# error "Please select sclk less than cclk" -# endif - -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ - -#if CONFIG_BOOT_LOAD < FIXED_CODE_END -# error "The kernel load address must be after the fixed code section" -#endif - -#if (CONFIG_BOOT_LOAD & 0x3) -# error "The kernel load address must be 4 byte aligned" -#endif - -/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */ -#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000 -# error "The kernel load address is too high; keep it below 10meg for safety" -#endif - -#if ANOMALY_05000263 && defined(CONFIG_MPU) -# error the MPU will not function safely while Anomaly 05000263 applies -#endif - -#if ANOMALY_05000448 -# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. -#endif - -/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ -#if ANOMALY_05000220 && \ - (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)) -# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory" -#endif - -#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1) -# error You need IFLUSH in L1 inst while Anomaly 05000491 applies -#endif diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c deleted file mode 100644 index f4adedc92895..000000000000 --- a/arch/blackfin/mach-common/cache-c.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Blackfin cache control code (simpler control-style functions) - * - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <asm/blackfin.h> -#include <asm/cplbinit.h> - -/* Invalidate the Entire Data cache by - * clearing DMC[1:0] bits - */ -void blackfin_invalidate_entire_dcache(void) -{ - u32 dmem = bfin_read_DMEM_CONTROL(); - bfin_write_DMEM_CONTROL(dmem & ~0xc); - SSYNC(); - bfin_write_DMEM_CONTROL(dmem); - SSYNC(); -} - -/* Invalidate the Entire Instruction cache by - * clearing IMC bit - */ -void blackfin_invalidate_entire_icache(void) -{ - u32 imem = bfin_read_IMEM_CONTROL(); - bfin_write_IMEM_CONTROL(imem & ~0x4); - SSYNC(); - bfin_write_IMEM_CONTROL(imem); - SSYNC(); -} - -#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE) - -static void -bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr, - unsigned long cplb_data, unsigned long mem_control, - unsigned long mem_mask) -{ - int i; -#ifdef CONFIG_L1_PARITY_CHECK - u32 ctrl; - - if (cplb_addr == DCPLB_ADDR0) { - ctrl = bfin_read32(mem_control) | (1 << RDCHK); - CSYNC(); - bfin_write32(mem_control, ctrl); - SSYNC(); - } -#endif - - for (i = 0; i < MAX_CPLBS; i++) { - bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr); - bfin_write32(cplb_data + i * 4, cplb_tbl[i].data); - } - - _enable_cplb(mem_control, mem_mask); -} - -#ifdef CONFIG_BFIN_ICACHE -void bfin_icache_init(struct cplb_entry *icplb_tbl) -{ - bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL, - (IMC | ENICPLB)); -} -#endif - -#ifdef CONFIG_BFIN_DCACHE -void bfin_dcache_init(struct cplb_entry *dcplb_tbl) -{ - /* - * Anomaly notes: - * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL - * register, so that the port preferences for DAG0 and DAG1 are set - * to port B - */ - bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL, - (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0))); -} -#endif - -#endif diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S deleted file mode 100644 index 9f4dd35bfd74..000000000000 --- a/arch/blackfin/mach-common/cache.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Blackfin cache control code - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/linkage.h> -#include <asm/blackfin.h> -#include <asm/cache.h> -#include <asm/page.h> - -/* 05000443 - IFLUSH cannot be last instruction in hardware loop */ -#if ANOMALY_05000443 -# define BROK_FLUSH_INST "IFLUSH" -#else -# define BROK_FLUSH_INST "no anomaly! yeah!" -#endif - -/* Since all L1 caches work the same way, we use the same method for flushing - * them. Only the actual flush instruction differs. We write this in asm as - * GCC can be hard to coax into writing nice hardware loops. - * - * Also, we assume the following register setup: - * R0 = start address - * R1 = end address - */ -.macro do_flush flushins:req label - - R2 = -L1_CACHE_BYTES; - - /* start = (start & -L1_CACHE_BYTES) */ - R0 = R0 & R2; - - /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ - R1 += -1; - R1 = R1 & R2; - R1 += L1_CACHE_BYTES; - - /* count = (end - start) >> L1_CACHE_SHIFT */ - R2 = R1 - R0; - R2 >>= L1_CACHE_SHIFT; - P1 = R2; - -.ifnb \label -\label : -.endif - P0 = R0; - - LSETUP (1f, 2f) LC1 = P1; -1: -.ifeqs "\flushins", BROK_FLUSH_INST - \flushins [P0++]; - nop; - nop; -2: nop; -.else -2: \flushins [P0++]; -.endif - - RTS; -.endm - -#ifdef CONFIG_ICACHE_FLUSH_L1 -.section .l1.text -#else -.text -#endif - -/* Invalidate all instruction cache lines assocoiated with this memory area */ -#ifdef CONFIG_SMP -# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1 -#endif -ENTRY(_blackfin_icache_flush_range) - do_flush IFLUSH -ENDPROC(_blackfin_icache_flush_range) - -#ifdef CONFIG_SMP -.text -# undef _blackfin_icache_flush_range -ENTRY(_blackfin_icache_flush_range) - p0.L = LO(DSPID); - p0.H = HI(DSPID); - r3 = [p0]; - r3 = r3.b (z); - p2 = r3; - p0.L = _blackfin_iflush_l1_entry; - p0.H = _blackfin_iflush_l1_entry; - p0 = p0 + (p2 << 2); - p1 = [p0]; - jump (p1); -ENDPROC(_blackfin_icache_flush_range) -#endif - -#ifdef CONFIG_DCACHE_FLUSH_L1 -.section .l1.text -#else -.text -#endif - -/* Throw away all D-cached data in specified region without any obligation to - * write them back. Since the Blackfin ISA does not have an "invalidate" - * instruction, we use flush/invalidate. Perhaps as a speed optimization we - * could bang on the DTEST MMRs ... - */ -ENTRY(_blackfin_dcache_invalidate_range) - do_flush FLUSHINV -ENDPROC(_blackfin_dcache_invalidate_range) - -/* Flush all data cache lines assocoiated with this memory area */ -ENTRY(_blackfin_dcache_flush_range) - do_flush FLUSH, .Ldfr -ENDPROC(_blackfin_dcache_flush_range) - -/* Our headers convert the page structure to an address, so just need to flush - * its contents like normal. We know the start address is page aligned (which - * greater than our cache alignment), as is the end address. So just jump into - * the middle of the dcache flush function. - */ -ENTRY(_blackfin_dflush_page) - P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); - jump .Ldfr; -ENDPROC(_blackfin_dflush_page) diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h deleted file mode 100644 index fed851a51aaf..000000000000 --- a/arch/blackfin/mach-common/clock.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __MACH_COMMON_CLKDEV_H -#define __MACH_COMMON_CLKDEV_H - -#include <linux/clk.h> - -struct clk_ops { - unsigned long (*get_rate)(struct clk *clk); - unsigned long (*round_rate)(struct clk *clk, unsigned long rate); - int (*set_rate)(struct clk *clk, unsigned long rate); - int (*enable)(struct clk *clk); - int (*disable)(struct clk *clk); -}; - -struct clk { - const char *name; - unsigned long rate; - spinlock_t lock; - u32 flags; - const struct clk_ops *ops; - const struct params *params; - void __iomem *reg; - u32 mask; - u32 shift; -}; - -#endif - diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c deleted file mode 100644 index d436bd907fc8..000000000000 --- a/arch/blackfin/mach-common/clocks-init.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/linkage.h> -#include <asm/blackfin.h> - -#include <asm/dma.h> -#include <asm/clocks.h> -#include <asm/mem_init.h> -#include <asm/dpmc.h> - -#ifdef CONFIG_BF60x - -#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF) -#define CGU_DIV_VAL \ - ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \ - (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \ - (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \ - (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \ - (CONFIG_DCLK_DIV << DSEL_OFFSET)) - -#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000) -#if ((CONFIG_BFIN_DCLK != 125) && \ - (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \ - (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \ - (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250)) -#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" -#endif - -#else -#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ -#define PLL_CTL_VAL \ - (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ - (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) -#endif - -__attribute__((l1_text)) -static void do_sync(void) -{ - __builtin_bfin_ssync(); -} - -__attribute__((l1_text)) -void init_clocks(void) -{ - /* Kill any active DMAs as they may trigger external memory accesses - * in the middle of reprogramming things, and that'll screw us up. - * For example, any automatic DMAs left by U-Boot for splash screens. - */ -#ifdef CONFIG_BF60x - init_cgu(CGU_DIV_VAL, CGU_CTL_VAL); - init_dmc(CONFIG_BFIN_DCLK); -#else - size_t i; - for (i = 0; i < MAX_DMA_CHANNELS; ++i) { - struct dma_register *dma = dma_io_base_addr[i]; - dma->cfg = 0; - } - - do_sync(); - -#ifdef SIC_IWR0 - bfin_write_SIC_IWR0(IWR_ENABLE(0)); -# ifdef SIC_IWR1 - /* BF52x system reset does not properly reset SIC_IWR1 which - * will screw up the bootrom as it relies on MDMA0/1 waking it - * up from IDLE instructions. See this report for more info: - * http://blackfin.uclinux.org/gf/tracker/4323 - */ - if (ANOMALY_05000435) - bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); - else - bfin_write_SIC_IWR1(IWR_DISABLE_ALL); -# endif -# ifdef SIC_IWR2 - bfin_write_SIC_IWR2(IWR_DISABLE_ALL); -# endif -#else - bfin_write_SIC_IWR(IWR_ENABLE(0)); -#endif - do_sync(); -#ifdef EBIU_SDGCTL - bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); - do_sync(); -#endif - -#ifdef CLKBUFOE - bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE); - do_sync(); - __asm__ __volatile__("IDLE;"); -#endif - bfin_write_PLL_LOCKCNT(0x300); - do_sync(); - /* We always write PLL_CTL thus avoiding Anomaly 05000242 */ - bfin_write16(PLL_CTL, PLL_CTL_VAL); - __asm__ __volatile__("IDLE;"); - bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); -#ifdef EBIU_SDGCTL - bfin_write_EBIU_SDRRC(mem_SDRRC); - bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL); -#else - bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); - do_sync(); - bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1); - bfin_write_EBIU_DDRCTL0(mem_DDRCTL0); - bfin_write_EBIU_DDRCTL1(mem_DDRCTL1); - bfin_write_EBIU_DDRCTL2(mem_DDRCTL2); -#ifdef CONFIG_MEM_EBIU_DDRQUE - bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); -#endif -#endif -#endif - do_sync(); - bfin_read16(0); - -} diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c deleted file mode 100644 index 724a8c5f5578..000000000000 --- a/arch/blackfin/mach-common/dpmc.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/cdev.h> -#include <linux/device.h> -#include <linux/errno.h> -#include <linux/fs.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/types.h> -#include <linux/cpufreq.h> - -#include <asm/delay.h> -#include <asm/dpmc.h> - -#define DRIVER_NAME "bfin dpmc" - -struct bfin_dpmc_platform_data *pdata; - -/** - * bfin_set_vlev - Update VLEV field in VR_CTL Reg. - * Avoid BYPASS sequence - */ -static void bfin_set_vlev(unsigned int vlev) -{ - unsigned pll_lcnt; - - pll_lcnt = bfin_read_PLL_LOCKCNT(); - - bfin_write_PLL_LOCKCNT(1); - bfin_write_VR_CTL((bfin_read_VR_CTL() & ~VLEV) | vlev); - bfin_write_PLL_LOCKCNT(pll_lcnt); -} - -/** - * bfin_get_vlev - Get CPU specific VLEV from platform device data - */ -static unsigned int bfin_get_vlev(unsigned int freq) -{ - int i; - - if (!pdata) - goto err_out; - - freq >>= 16; - - for (i = 0; i < pdata->tabsize; i++) - if (freq <= (pdata->tuple_tab[i] & 0xFFFF)) - return pdata->tuple_tab[i] >> 16; - -err_out: - printk(KERN_WARNING "DPMC: No suitable CCLK VDDINT voltage pair found\n"); - return VLEV_120; -} - -#ifdef CONFIG_CPU_FREQ -# ifdef CONFIG_SMP -static void bfin_idle_this_cpu(void *info) -{ - unsigned long flags = 0; - unsigned long iwr0, iwr1, iwr2; - unsigned int cpu = smp_processor_id(); - - local_irq_save_hw(flags); - bfin_iwr_set_sup0(&iwr0, &iwr1, &iwr2); - - platform_clear_ipi(cpu, IRQ_SUPPLE_0); - SSYNC(); - asm("IDLE;"); - bfin_iwr_restore(iwr0, iwr1, iwr2); - - local_irq_restore_hw(flags); -} - -static void bfin_idle_cpu(void) -{ - smp_call_function(bfin_idle_this_cpu, NULL, 0); -} - -static void bfin_wakeup_cpu(void) -{ - unsigned int cpu; - unsigned int this_cpu = smp_processor_id(); - cpumask_t mask; - - cpumask_copy(&mask, cpu_online_mask); - cpumask_clear_cpu(this_cpu, &mask); - for_each_cpu(cpu, &mask) - platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); -} - -# else -static void bfin_idle_cpu(void) {} -static void bfin_wakeup_cpu(void) {} -# endif - -static int -vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data) -{ - struct cpufreq_freqs *freq = data; - - if (freq->cpu != CPUFREQ_CPU) - return 0; - - if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) { - bfin_idle_cpu(); - bfin_set_vlev(bfin_get_vlev(freq->new)); - udelay(pdata->vr_settling_time); /* Wait until Volatge settled */ - bfin_wakeup_cpu(); - } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) { - bfin_idle_cpu(); - bfin_set_vlev(bfin_get_vlev(freq->new)); - bfin_wakeup_cpu(); - } - - return 0; -} - -static struct notifier_block vreg_cpufreq_notifier_block = { - .notifier_call = vreg_cpufreq_notifier -}; -#endif /* CONFIG_CPU_FREQ */ - -/** - * bfin_dpmc_probe - - * - */ -static int bfin_dpmc_probe(struct platform_device *pdev) -{ - if (pdev->dev.platform_data) - pdata = pdev->dev.platform_data; - else - return -EINVAL; - - return cpufreq_register_notifier(&vreg_cpufreq_notifier_block, - CPUFREQ_TRANSITION_NOTIFIER); -} - -/** - * bfin_dpmc_remove - - */ -static int bfin_dpmc_remove(struct platform_device *pdev) -{ - pdata = NULL; - return cpufreq_unregister_notifier(&vreg_cpufreq_notifier_block, - CPUFREQ_TRANSITION_NOTIFIER); -} - -struct platform_driver bfin_dpmc_device_driver = { - .probe = bfin_dpmc_probe, - .remove = bfin_dpmc_remove, - .driver = { - .name = DRIVER_NAME, - } -}; -module_platform_driver(bfin_dpmc_device_driver); - -MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); -MODULE_DESCRIPTION("cpu power management driver for Blackfin"); -MODULE_LICENSE("GPL"); diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S deleted file mode 100644 index de99f3aac2c5..000000000000 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/linkage.h> -#include <asm/blackfin.h> -#include <mach/irq.h> -#include <asm/dpmc.h> - -.section .l1.text -ENTRY(_sleep_mode) - [--SP] = (R7:4, P5:3); - [--SP] = RETS; - - call _set_sic_iwr; - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R1 = W[P0](z); - BITSET (R1, 3); - W[P0] = R1.L; - - CLI R2; - SSYNC; - IDLE; - STI R2; - - call _test_pll_locked; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R7 = w[p0](z); - BITCLR (R7, 3); - BITCLR (R7, 5); - w[p0] = R7.L; - IDLE; - - bfin_init_pm_bench_cycles; - - call _test_pll_locked; - - RETS = [SP++]; - (R7:4, P5:3) = [SP++]; - RTS; -ENDPROC(_sleep_mode) - -/* - * This func never returns as it puts the part into hibernate, and - * is only called from do_hibernate, so we don't bother saving or - * restoring any of the normal C runtime state. When we wake up, - * the entry point will be in do_hibernate and not here. - * - * We accept just one argument -- the value to write to VR_CTL. - */ - -ENTRY(_hibernate_mode) - /* Save/setup the regs we need early for minor pipeline optimization */ - R4 = R0; - - P3.H = hi(VR_CTL); - P3.L = lo(VR_CTL); - /* Disable all wakeup sources */ - R0 = IWR_DISABLE_ALL; - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - call _set_sic_iwr; - call _set_dram_srfs; - SSYNC; - - /* Finally, we climb into our cave to hibernate */ - W[P3] = R4.L; - - bfin_init_pm_bench_cycles; - - CLI R2; - IDLE; -.Lforever: - jump .Lforever; -ENDPROC(_hibernate_mode) - -ENTRY(_sleep_deeper) - [--SP] = (R7:4, P5:3); - [--SP] = RETS; - - CLI R4; - - P3 = R0; - P4 = R1; - P5 = R2; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; - call _set_dram_srfs; /* Set SDRAM Self Refresh */ - - P0.H = hi(PLL_DIV); - P0.L = lo(PLL_DIV); - R6 = W[P0](z); - R0.L = 0xF; - W[P0] = R0.l; /* Set Max VCO to SCLK divider */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R5 = W[P0](z); - R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9; - W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */ - - SSYNC; - IDLE; - - call _test_pll_locked; - - P0.H = hi(VR_CTL); - P0.L = lo(VR_CTL); - R7 = W[P0](z); - R1 = 0x6; - R1 <<= 16; - R2 = 0x0404(Z); - R1 = R1|R2; - - R2 = DEPOSIT(R7, R1); - W[P0] = R2; /* Set Min Core Voltage */ - - SSYNC; - IDLE; - - call _test_pll_locked; - - R0 = P3; - R1 = P4; - R3 = P5; - call _set_sic_iwr; /* Set Awake from IDLE */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - R0 = W[P0](z); - BITSET (R0, 3); - W[P0] = R0.L; /* Turn CCLK OFF */ - SSYNC; - IDLE; - - call _test_pll_locked; - - R0 = IWR_ENABLE(0); - R1 = IWR_DISABLE_ALL; - R2 = IWR_DISABLE_ALL; - - call _set_sic_iwr; /* Set Awake from IDLE PLL */ - - P0.H = hi(VR_CTL); - P0.L = lo(VR_CTL); - W[P0]= R7; - - SSYNC; - IDLE; - - bfin_init_pm_bench_cycles; - - call _test_pll_locked; - - P0.H = hi(PLL_DIV); - P0.L = lo(PLL_DIV); - W[P0]= R6; /* Restore CCLK and SCLK divider */ - - P0.H = hi(PLL_CTL); - P0.L = lo(PLL_CTL); - w[p0] = R5; /* Restore VCO multiplier */ - IDLE; - call _test_pll_locked; - - call _unset_dram_srfs; /* SDRAM Self Refresh Off */ - - STI R4; - - RETS = [SP++]; - (R7:4, P5:3) = [SP++]; - RTS; -ENDPROC(_sleep_deeper) - -ENTRY(_set_dram_srfs) - /* set the dram to self refresh mode */ - SSYNC; -#if defined(EBIU_RSTCTL) /* DDR */ - P0.H = hi(EBIU_RSTCTL); - P0.L = lo(EBIU_RSTCTL); - R2 = [P0]; - BITSET(R2, 3); /* SRREQ enter self-refresh mode */ - [P0] = R2; - SSYNC; -1: - R2 = [P0]; - CC = BITTST(R2, 4); - if !CC JUMP 1b; -#else /* SDRAM */ - P0.L = lo(EBIU_SDGCTL); - P0.H = hi(EBIU_SDGCTL); - P1.L = lo(EBIU_SDSTAT); - P1.H = hi(EBIU_SDSTAT); - - R2 = [P0]; - BITSET(R2, 24); /* SRFS enter self-refresh mode */ - [P0] = R2; - SSYNC; - -1: - R2 = w[P1]; - SSYNC; - cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */ - if !cc jump 1b; - - R2 = [P0]; - BITCLR(R2, 0); /* SCTLE disable CLKOUT */ - [P0] = R2; -#endif - RTS; -ENDPROC(_set_dram_srfs) - -ENTRY(_unset_dram_srfs) - /* set the dram out of self refresh mode */ - -#if defined(EBIU_RSTCTL) /* DDR */ - P0.H = hi(EBIU_RSTCTL); - P0.L = lo(EBIU_RSTCTL); - R2 = [P0]; - BITCLR(R2, 3); /* clear SRREQ bit */ - [P0] = R2; -#elif defined(EBIU_SDGCTL) /* SDRAM */ - /* release CLKOUT from self-refresh */ - P0.L = lo(EBIU_SDGCTL); - P0.H = hi(EBIU_SDGCTL); - - R2 = [P0]; - BITSET(R2, 0); /* SCTLE enable CLKOUT */ - [P0] = R2 - SSYNC; - - /* release SDRAM from self-refresh */ - R2 = [P0]; - BITCLR(R2, 24); /* clear SRFS bit */ - [P0] = R2 -#endif - - SSYNC; - RTS; -ENDPROC(_unset_dram_srfs) - -ENTRY(_set_sic_iwr) -#ifdef SIC_IWR0 - P0.H = hi(SYSMMR_BASE); - P0.L = lo(SYSMMR_BASE); - [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0; - [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1; -# ifdef SIC_IWR2 - [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2; -# endif -#else - P0.H = hi(SIC_IWR); - P0.L = lo(SIC_IWR); - [P0] = R0; -#endif - - SSYNC; - RTS; -ENDPROC(_set_sic_iwr) - -ENTRY(_test_pll_locked) - P0.H = hi(PLL_STAT); - P0.L = lo(PLL_STAT); -1: - R0 = W[P0] (Z); - CC = BITTST(R0,5); - IF !CC JUMP 1b; - RTS; -ENDPROC(_test_pll_locked) - -.section .text -ENTRY(_do_hibernate) - bfin_cpu_reg_save; - bfin_sys_mmr_save; - bfin_core_mmr_save; - - /* Setup args to hibernate mode early for pipeline optimization */ - R0 = M3; - P1.H = _hibernate_mode; - P1.L = _hibernate_mode; - - /* Save Magic, return address and Stack Pointer */ - P0 = 0; - R1.H = 0xDEAD; /* Hibernate Magic */ - R1.L = 0xBEEF; - R2.H = .Lpm_resume_here; - R2.L = .Lpm_resume_here; - [P0++] = R1; /* Store Hibernate Magic */ - [P0++] = R2; /* Save Return Address */ - [P0++] = SP; /* Save Stack Pointer */ - - /* Must use an indirect call as we need to jump to L1 */ - call (P1); /* Goodbye */ - -.Lpm_resume_here: - - bfin_core_mmr_restore; - bfin_sys_mmr_restore; - bfin_cpu_reg_restore; - - [--sp] = RETI; /* Clear Global Interrupt Disable */ - SP += 4; - - RTS; -ENDPROC(_do_hibernate) diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S deleted file mode 100644 index 8d9431e22e8c..000000000000 --- a/arch/blackfin/mach-common/entry.S +++ /dev/null @@ -1,1711 +0,0 @@ -/* - * Contains the system-call and fault low-level handling routines. - * This also contains the timer-interrupt handler, as well as all - * interrupts and faults that can result in a task-switch. - * - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -/* NOTE: This code handles signal-recognition, which happens every time - * after a timer-interrupt and after each system call. - */ - -#include <linux/init.h> -#include <linux/linkage.h> -#include <linux/unistd.h> -#include <asm/blackfin.h> -#include <asm/errno.h> -#include <asm/fixed_code.h> -#include <asm/thread_info.h> /* TIF_NEED_RESCHED */ -#include <asm/asm-offsets.h> -#include <asm/trace.h> -#include <asm/traps.h> - -#include <asm/context.S> - - -#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 -.section .l1.text -#else -.text -#endif - -/* Slightly simplified and streamlined entry point for CPLB misses. - * This one does not lower the level to IRQ5, and thus can be used to - * patch up CPLB misses on the kernel stack. - */ -#if ANOMALY_05000261 -#define _ex_dviol _ex_workaround_261 -#define _ex_dmiss _ex_workaround_261 -#define _ex_dmult _ex_workaround_261 - -ENTRY(_ex_workaround_261) - /* - * Work around an anomaly: if we see a new DCPLB fault, return - * without doing anything. Then, if we get the same fault again, - * handle it. - */ - P4 = R7; /* Store EXCAUSE */ - - GET_PDA(p5, r7); - r7 = [p5 + PDA_LFRETX]; - r6 = retx; - [p5 + PDA_LFRETX] = r6; - cc = r6 == r7; - if !cc jump _bfin_return_from_exception; - /* fall through */ - R7 = P4; - R6 = VEC_CPLB_M; /* Data CPLB Miss */ - cc = R6 == R7; - if cc jump _ex_dcplb_miss (BP); -#ifdef CONFIG_MPU - R6 = VEC_CPLB_VL; /* Data CPLB Violation */ - cc = R6 == R7; - if cc jump _ex_dcplb_viol (BP); -#endif - /* Handle Data CPLB Protection Violation - * and Data CPLB Multiple Hits - Linux Trap Zero - */ - jump _ex_trap_c; -ENDPROC(_ex_workaround_261) - -#else -#ifdef CONFIG_MPU -#define _ex_dviol _ex_dcplb_viol -#else -#define _ex_dviol _ex_trap_c -#endif -#define _ex_dmiss _ex_dcplb_miss -#define _ex_dmult _ex_trap_c -#endif - - -ENTRY(_ex_dcplb_viol) -ENTRY(_ex_dcplb_miss) -ENTRY(_ex_icplb_miss) - (R7:6,P5:4) = [sp++]; - /* We leave the previously pushed ASTAT on the stack. */ - SAVE_CONTEXT_CPLB - - /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that - * will change the stack pointer. */ - R0 = SEQSTAT; - R1 = SP; - - DEBUG_HWTRACE_SAVE(p5, r7) - - sp += -12; - call _cplb_hdr; - sp += 12; - CC = R0 == 0; - IF !CC JUMP _handle_bad_cplb; - -#ifdef CONFIG_DEBUG_DOUBLEFAULT - /* While we were processing this, did we double fault? */ - r7 = SEQSTAT; /* reason code is in bit 5:0 */ - r6.l = lo(SEQSTAT_EXCAUSE); - r6.h = hi(SEQSTAT_EXCAUSE); - r7 = r7 & r6; - r6 = 0x25; - CC = R7 == R6; - if CC JUMP _double_fault; -#endif - - DEBUG_HWTRACE_RESTORE(p5, r7) - RESTORE_CONTEXT_CPLB - ASTAT = [SP++]; - SP = EX_SCRATCH_REG; - rtx; -ENDPROC(_ex_icplb_miss) - -ENTRY(_ex_syscall) - raise 15; /* invoked by TRAP #0, for sys call */ - jump.s _bfin_return_from_exception; -ENDPROC(_ex_syscall) - -ENTRY(_ex_single_step) - /* If we just returned from an interrupt, the single step event is - for the RTI instruction. */ - r7 = retx; - r6 = reti; - cc = r7 == r6; - if cc jump _bfin_return_from_exception; - -#ifdef CONFIG_KGDB - /* Don't do single step in hardware exception handler */ - p5.l = lo(IPEND); - p5.h = hi(IPEND); - r6 = [p5]; - cc = bittst(r6, 4); - if cc jump _bfin_return_from_exception; - cc = bittst(r6, 5); - if cc jump _bfin_return_from_exception; - - /* skip single step if current |