diff options
65 files changed, 2764 insertions, 1174 deletions
diff --git a/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp b/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp new file mode 100644 index 000000000000..00fa04c76ff3 --- /dev/null +++ b/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp @@ -0,0 +1,103 @@ +What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs* +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" <jollys@xilinx.com> +Description: + Read/Write PMU global general storage register value, + GLOBAL_GEN_STORAGE{0:3}. + Global general storage register that can be used + by system to pass information between masters. + + The register is reset during system or power-on + resets. Three registers are used by the FSBL and + other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}. + + Usage: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + + Example: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + +Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs* +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" <jollys@xilinx.com> +Description: + Read/Write PMU persistent global general storage register + value, PERS_GLOB_GEN_STORAGE{0:3}. + Persistent global general storage register that + can be used by system to pass information between + masters. + + This register is only reset by the power-on reset + and maintains its value through a system reset. + Four registers are used by the FSBL and other Xilinx + software products: PERS_GLOB_GEN_STORAGE{4:7}. + Register is reset only by a POR reset. + + Usage: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + + Example: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + +Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" <jollys@xilinx.com> +Description: + This sysfs interface allows to set the shutdown scope for the + next shutdown request. When the next shutdown is performed, the + platform specific portion of PSCI-system_off can use the chosen + shutdown scope. + + Following are available shutdown scopes(subtypes): + + subsystem: Only the APU along with all of its peripherals + not used by other processing units will be + shut down. This may result in the FPD power + domain being shut down provided that no other + processing unit uses FPD peripherals or DRAM. + ps_only: The complete PS will be shut down, including the + RPU, PMU, etc. Only the PL domain (FPGA) + remains untouched. + system: The complete system/device is shut down. + + Usage: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + # echo <scope> > /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + + Example: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + # echo "subsystem" > /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + +Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/health_status +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" <jollys@xilinx.com> +Description: + This sysfs interface allows to set the health status. If PMUFW + is compiled with CHECK_HEALTHY_BOOT, it will check the healthy + bit on FPD WDT expiration. If healthy bit is set by a user + application running in Linux, PMUFW will do APU only restart. If + healthy bit is not set during FPD WDT expiration, PMUFW will do + system restart. + + Usage: + Set healthy bit + # echo 1 > /sys/devices/platform/firmware\:zynqmp-firmware/health_status + + Unset healthy bit + # echo 0 > /sys/devices/platform/firmware\:zynqmp-firmware/health_status + +Users: Xilinx diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-dfl_fme b/Documentation/ABI/testing/sysfs-bus-event_source-devices-dfl_fme new file mode 100644 index 000000000000..c9278a3b3df1 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-dfl_fme @@ -0,0 +1,104 @@ +What: /sys/bus/event_source/devices/dfl_fmeX/format +Date: April 2020 +KernelVersion: 5.8 +Contact: Wu Hao <hao.wu@intel.com> +Description: Read-only. Attribute group to describe the magic bits + that go into perf_event_attr.config for a particular pmu. + (See ABI/testing/sysfs-bus-event_source-devices-format). + + Each attribute under this group defines a bit range of the + perf_event_attr.config. All supported attributes are listed + below. + + event = "config:0-11" - event ID + evtype = "config:12-15" - event type + portid = "config:16-23" - event source + + For example, + + fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff" + + It shows this fab_mmio_read is a fabric type (0x02) event with + 0x06 local event id for overall monitoring (portid=0xff). + +What: /sys/bus/event_source/devices/dfl_fmeX/cpumask +Date: April 2020 +KernelVersion: 5.8 +Contact: Wu Hao <hao.wu@intel.com> +Description: Read-only. This file always returns cpu which the PMU is bound + for access to all fme pmu performance monitoring events. + +What: /sys/bus/event_source/devices/dfl_fmeX/events +Date: April 2020 +KernelVersion: 5.8 +Contact: Wu Hao <hao.wu@intel.com> +Description: Read-only. Attribute group to describe performance monitoring + events specific to fme. Each attribute in this group describes + a single performance monitoring event supported by this fme pmu. + The name of the file is the name of the event. + (See ABI/testing/sysfs-bus-event_source-devices-events). + + All supported performance monitoring events are listed below. + + Basic events (evtype=0x00) + + clock = "event=0x00,evtype=0x00,portid=0xff" + + Cache events (evtype=0x01) + + cache_read_hit = "event=0x00,evtype=0x01,portid=0xff" + cache_read_miss = "event=0x01,evtype=0x01,portid=0xff" + cache_write_hit = "event=0x02,evtype=0x01,portid=0xff" + cache_write_miss = "event=0x03,evtype=0x01,portid=0xff" + cache_hold_request = "event=0x05,evtype=0x01,portid=0xff" + cache_data_write_port_contention = + "event=0x06,evtype=0x01,portid=0xff" + cache_tag_write_port_contention = + "event=0x07,evtype=0x01,portid=0xff" + cache_tx_req_stall = "event=0x08,evtype=0x01,portid=0xff" + cache_rx_req_stall = "event=0x09,evtype=0x01,portid=0xff" + cache_eviction = "event=0x0a,evtype=0x01,portid=0xff" + + Fabric events (evtype=0x02) + + fab_pcie0_read = "event=0x00,evtype=0x02,portid=0xff" + fab_pcie0_write = "event=0x01,evtype=0x02,portid=0xff" + fab_pcie1_read = "event=0x02,evtype=0x02,portid=0xff" + fab_pcie1_write = "event=0x03,evtype=0x02,portid=0xff" + fab_upi_read = "event=0x04,evtype=0x02,portid=0xff" + fab_upi_write = "event=0x05,evtype=0x02,portid=0xff" + fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff" + fab_mmio_write = "event=0x07,evtype=0x02,portid=0xff" + fab_port_pcie0_read = "event=0x00,evtype=0x02,portid=?" + fab_port_pcie0_write = "event=0x01,evtype=0x02,portid=?" + fab_port_pcie1_read = "event=0x02,evtype=0x02,portid=?" + fab_port_pcie1_write = "event=0x03,evtype=0x02,portid=?" + fab_port_upi_read = "event=0x04,evtype=0x02,portid=?" + fab_port_upi_write = "event=0x05,evtype=0x02,portid=?" + fab_port_mmio_read = "event=0x06,evtype=0x02,portid=?" + fab_port_mmio_write = "event=0x07,evtype=0x02,portid=?" + + VTD events (evtype=0x03) + + vtd_port_read_transaction = "event=0x00,evtype=0x03,portid=?" + vtd_port_write_transaction = "event=0x01,evtype=0x03,portid=?" + vtd_port_devtlb_read_hit = "event=0x02,evtype=0x03,portid=?" + vtd_port_devtlb_write_hit = "event=0x03,evtype=0x03,portid=?" + vtd_port_devtlb_4k_fill = "event=0x04,evtype=0x03,portid=?" + vtd_port_devtlb_2m_fill = "event=0x05,evtype=0x03,portid=?" + vtd_port_devtlb_1g_fill = "event=0x06,evtype=0x03,portid=?" + + VTD SIP events (evtype=0x04) + + vtd_sip_iotlb_4k_hit = "event=0x00,evtype=0x04,portid=0xff" + vtd_sip_iotlb_2m_hit = "event=0x01,evtype=0x04,portid=0xff" + vtd_sip_iotlb_1g_hit = "event=0x02,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l3_hit = "event=0x03,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l4_hit = "event=0x04,evtype=0x04,portid=0xff" + vtd_sip_rcc_hit = "event=0x05,evtype=0x04,portid=0xff" + vtd_sip_iotlb_4k_miss = "event=0x06,evtype=0x04,portid=0xff" + vtd_sip_iotlb_2m_miss = "event=0x07,evtype=0x04,portid=0xff" + vtd_sip_iotlb_1g_miss = "event=0x08,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l3_miss = "event=0x09,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l4_miss = "event=0x0a,evtype=0x04,portid=0xff" + vtd_sip_rcc_miss = "event=0x0b,evtype=0x04,portid=0xff" diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 094fc8aacd8e..978c4af416a4 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -118,6 +118,11 @@ More functions are exposed through sysfs management information (current temperature, thresholds, threshold status, etc.). + Performance reporting + performance counters are exposed through perf PMU APIs. Standard perf tool + can be used to monitor all available perf events. Please see performance + counter section below for more detailed information. + FIU - PORT ========== @@ -378,6 +383,85 @@ The device nodes used for ioctl() or mmap() can be referenced through:: /sys/class/fpga_region/<regionX>/<dfl-port.n>/dev +Performance Counters +==================== +Performance reporting is one private feature implemented in FME. It could +supports several independent, system-wide, device counter sets in hardware to +monitor and count for performance events, including "basic", "cache", "fabric", +"vtd" and "vtd_sip" counters. Users could use standard perf tool to monitor +FPGA cache hit/miss rate, transaction number, interface clock counter of AFU +and other FPGA performance events. + +Different FPGA devices may have different counter sets, depending on hardware +implementation. E.g., some discrete FPGA cards don't have any cache. User could +use "perf list" to check which perf events are supported by target hardware. + +In order to allow user to use standard perf API to access these performance +counters, driver creates a perf PMU, and related sysfs interfaces in +/sys/bus/event_source/devices/dfl_fme* to describe available perf events and +configuration options. + +The "format" directory describes the format of the config field of struct +perf_event_attr. There are 3 bitfields for config: "evtype" defines which type +the perf event belongs to; "event" is the identity of the event within its +category; "portid" is introduced to decide counters set to monitor on FPGA +overall data or a specific port. + +The "events" directory describes the configuration templates for all available +events which can be used with perf tool directly. For example, fab_mmio_read +has the configuration "event=0x06,evtype=0x02,portid=0xff", which shows this +event belongs to fabric type (0x02), the local event id is 0x06 and it is for +overall monitoring (portid=0xff). + +Example usage of perf:: + + $# perf list |grep dfl_fme + + dfl_fme0/fab_mmio_read/ [Kernel PMU event] + <...> + dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event] + <...> + + $# perf stat -a -e dfl_fme0/fab_mmio_read/ <command> + or + $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0xff/ <command> + or + $# perf stat -a -e dfl_fme0/config=0xff2006/ <command> + +Another example, fab_port_mmio_read monitors mmio read of a specific port. So +its configuration template is "event=0x06,evtype=0x01,portid=?". The portid +should be explicitly set. + +Its usage of perf:: + + $# perf stat -a -e dfl_fme0/fab_port_mmio_read,portid=0x0/ <command> + or + $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0x0/ <command> + or + $# perf stat -a -e dfl_fme0/config=0x2006/ <command> + +Please note for fabric counters, overall perf events (fab_*) and port perf +events (fab_port_*) actually share one set of counters in hardware, so it can't +monitor both at the same time. If this set of counters is configured to monitor +overall data, then per port perf data is not supported. See below example:: + + $# perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,\ + portid=0/ sleep 1 + + Performance counter stats for 'system wide': + + 3 dfl_fme0/fab_mmio_read/ + <not supported> dfl_fme0/fab_port_mmio_write,portid=0x0/ + + 1.001750904 seconds time elapsed + +The driver also provides a "cpumask" sysfs attribute, which contains only one +CPU id used to access these perf events. Counting on multiple CPU is not allowed +since they are system-wide counters on FPGA device. + +The current driver does not support sampling. So "perf record" is unsupported. + + Add new FIUs support ==================== It's possible that developers made some new function blocks (FIUs) under this diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c index 9ecad74183a3..7cf566aafe1f 100644 --- a/drivers/android/binderfs.c +++ b/drivers/android/binderfs.c @@ -650,7 +650,7 @@ static int binderfs_fill_super(struct super_block *sb, struct fs_context *fc) struct binderfs_info *info; struct binderfs_mount_opts *ctx = fc->fs_private; struct inode *inode = NULL; - struct binderfs_device device_info = { 0 }; + struct binderfs_device device_info = {}; const char *name; size_t len; @@ -747,7 +747,7 @@ static const struct fs_context_operations binderfs_fs_context_ops = { static int binderfs_init_fs_context(struct fs_context *fc) { - struct binderfs_mount_opts *ctx = fc->fs_private; + struct binderfs_mount_opts *ctx; ctx = kzalloc(sizeof(struct binderfs_mount_opts), GFP_KERNEL); if (!ctx) diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c index 97e06cc586e4..c26eed06e5cc 100644 --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c @@ -258,7 +258,7 @@ int mhi_destroy_device(struct device *dev, void *data) return 0; } -static void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) +void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) { struct mhi_driver *mhi_drv; @@ -270,6 +270,7 @@ static void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) if (mhi_drv->status_cb) mhi_drv->status_cb(mhi_dev, cb_reason); } +EXPORT_SYMBOL_GPL(mhi_notify); /* Bind MHI channels to MHI devices */ void mhi_create_devices(struct mhi_controller *mhi_cntrl) diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c index dc83d65f7784..e7c831867a23 100644 --- a/drivers/bus/mhi/core/pm.c +++ b/drivers/bus/mhi/core/pm.c @@ -669,6 +669,149 @@ void mhi_pm_st_worker(struct work_struct *work) } } +int mhi_pm_suspend(struct mhi_controller *mhi_cntrl) +{ + struct mhi_chan *itr, *tmp; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + enum mhi_pm_state new_state; + int ret; + + if (mhi_cntrl->pm_state == MHI_PM_DISABLE) + return -EINVAL; + + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) + return -EIO; + + /* Return busy if there are any pending resources */ + if (atomic_read(&mhi_cntrl->dev_wake)) + return -EBUSY; + + /* Take MHI out of M2 state */ + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_get(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->dev_state == MHI_STATE_M0 || + mhi_cntrl->dev_state == MHI_STATE_M1 || + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_put(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + + if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + dev_err(dev, + "Could not enter M0/M1 state"); + return -EIO; + } + + write_lock_irq(&mhi_cntrl->pm_lock); + + if (atomic_read(&mhi_cntrl->dev_wake)) { + write_unlock_irq(&mhi_cntrl->pm_lock); + return -EBUSY; + } + + dev_info(dev, "Allowing M3 transition\n"); + new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER); + if (new_state != MHI_PM_M3_ENTER) { + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_err(dev, + "Error setting to PM state: %s from: %s\n", + to_mhi_pm_state_str(MHI_PM_M3_ENTER), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + /* Set MHI to M3 and wait for completion */ + mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3); + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_info(dev, "Wait for M3 completion\n"); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->dev_state == MHI_STATE_M3 || + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + dev_err(dev, + "Did not enter M3 state, MHI state: %s, PM state: %s\n", + TO_MHI_STATE_STR(mhi_cntrl->dev_state), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + /* Notify clients about entering LPM */ + list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) { + mutex_lock(&itr->mutex); + if (itr->mhi_dev) + mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER); + mutex_unlock(&itr->mutex); + } + + return 0; +} +EXPORT_SYMBOL_GPL(mhi_pm_suspend); + +int mhi_pm_resume(struct mhi_controller *mhi_cntrl) +{ + struct mhi_chan *itr, *tmp; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + enum mhi_pm_state cur_state; + int ret; + + dev_info(dev, "Entered with PM state: %s, MHI state: %s\n", + to_mhi_pm_state_str(mhi_cntrl->pm_state), + TO_MHI_STATE_STR(mhi_cntrl->dev_state)); + + if (mhi_cntrl->pm_state == MHI_PM_DISABLE) + return 0; + + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) + return -EIO; + + /* Notify clients about exiting LPM */ + list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) { + mutex_lock(&itr->mutex); + if (itr->mhi_dev) + mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT); + mutex_unlock(&itr->mutex); + } + + write_lock_irq(&mhi_cntrl->pm_lock); + cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT); + if (cur_state != MHI_PM_M3_EXIT) { |