diff options
70 files changed, 819 insertions, 848 deletions
diff --git a/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt b/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt new file mode 100644 index 000000000000..e5ca4ccd55ed --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt @@ -0,0 +1,7 @@ +Innolux Corporation 10.1" EE101IA-01D WXGA (1280x800) LVDS panel + +Required properties: +- compatible: should be "innolux,ee101ia-01d" + +This binding is compatible with the lvds-panel binding, which is specified +in panel-lvds.txt in this directory. diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst index a752aa561ea4..c9fd23efd957 100644 --- a/Documentation/gpu/drm-uapi.rst +++ b/Documentation/gpu/drm-uapi.rst @@ -238,6 +238,14 @@ DRM specific patterns. Note that ENOTTY has the slightly unintuitive meaning of Testing and validation ====================== +Testing Requirements for userspace API +-------------------------------------- + +New cross-driver userspace interface extensions, like new IOCTL, new KMS +properties, new files in sysfs or anything else that constitutes an API change +should have driver-agnostic testcases in IGT for that feature, if such a test +can be reasonably made using IGT for the target hardware. + Validating changes with IGT --------------------------- diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index cda4a37a02f0..159a4aba49e6 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -398,10 +398,6 @@ KMS cleanups Some of these date from the very introduction of KMS in 2008 ... -- drm_display_mode doesn't need to be derived from drm_mode_object. That's - leftovers from older (never merged into upstream) KMS designs where modes - where set using their ID, including support to add/remove modes. - - Make ->funcs and ->helper_private vtables optional. There's a bunch of empty function tables in drivers, but before we can remove them we need to make sure that all the users in helpers and drivers do correctly check for a NULL diff --git a/Documentation/gpu/vkms.rst b/Documentation/gpu/vkms.rst index 7dfc349a4508..61586fc861bb 100644 --- a/Documentation/gpu/vkms.rst +++ b/Documentation/gpu/vkms.rst @@ -23,17 +23,6 @@ CRC API Improvements - Add igt test to check extreme alpha values i.e. fully opaque and fully transparent (intermediate values are affected by hw-specific rounding modes). -Vblank issues -------------- - -Some IGT test cases are failing. Need to analyze why and fix the issues: - -- plain-flip-fb-recreate -- plain-flip-ts-check -- flip-vs-blocking-wf-vblank -- plain-flip-fb-recreate-interruptible -- flip-vs-wf_vblank-interruptible - Runtime Configuration --------------------- diff --git a/drivers/gpu/drm/bochs/bochs_mm.c b/drivers/gpu/drm/bochs/bochs_mm.c index 641a33f134ee..49463348a07a 100644 --- a/drivers/gpu/drm/bochs/bochs_mm.c +++ b/drivers/gpu/drm/bochs/bochs_mm.c @@ -442,5 +442,6 @@ int bochs_gem_prime_mmap(struct drm_gem_object *obj, { struct bochs_bo *bo = gem_to_bochs_bo(obj); - return ttm_fbdev_mmap(vma, &bo->bo); + bo->gem.vma_node.vm_node.start = bo->bo.vma_node.vm_node.start; + return drm_gem_prime_mmap(obj, vma); } diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 2fee47b0d50b..8840f396a7b6 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -30,6 +30,7 @@ config DRM_CDNS_DSI select DRM_KMS_HELPER select DRM_MIPI_DSI select DRM_PANEL_BRIDGE + select GENERIC_PHY_MIPI_DPHY depends on OF help Support Cadence DPI to DSI bridge. This is an internal diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c b/drivers/gpu/drm/bridge/cdns-dsi.c index 924abe82ea3c..6166dca6be81 100644 --- a/drivers/gpu/drm/bridge/cdns-dsi.c +++ b/drivers/gpu/drm/bridge/cdns-dsi.c @@ -23,6 +23,9 @@ #include <linux/pm_runtime.h> #include <linux/reset.h> +#include <linux/phy/phy.h> +#include <linux/phy/phy-mipi-dphy.h> + #define IP_CONF 0x0 #define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26) #define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21) @@ -421,44 +424,11 @@ #define DSI_NULL_FRAME_OVERHEAD 6 #define DSI_EOT_PKT_SIZE 4 -#define REG_WAKEUP_TIME_NS 800 -#define DPHY_PLL_RATE_HZ 108000000 - -/* DPHY registers */ -#define DPHY_PMA_CMN(reg) (reg) -#define DPHY_PMA_LCLK(reg) (0x100 + (reg)) -#define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg)) -#define DPHY_PMA_RCLK(reg) (0x600 + (reg)) -#define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg)) -#define DPHY_PCS(reg) (0xb00 + (reg)) - -#define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) -#define DPHY_CMN_SSM_EN BIT(0) -#define DPHY_CMN_TX_MODE_EN BIT(9) - -#define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) -#define DPHY_CMN_PWM_DIV(x) ((x) << 20) -#define DPHY_CMN_PWM_LOW(x) ((x) << 10) -#define DPHY_CMN_PWM_HIGH(x) (x) - -#define DPHY_CMN_FBDIV DPHY_PMA_CMN(0x4c) -#define DPHY_CMN_FBDIV_VAL(low, high) (((high) << 11) | ((low) << 22)) -#define DPHY_CMN_FBDIV_FROM_REG (BIT(10) | BIT(21)) - -#define DPHY_CMN_OPIPDIV DPHY_PMA_CMN(0x50) -#define DPHY_CMN_IPDIV_FROM_REG BIT(0) -#define DPHY_CMN_IPDIV(x) ((x) << 1) -#define DPHY_CMN_OPDIV_FROM_REG BIT(6) -#define DPHY_CMN_OPDIV(x) ((x) << 7) - -#define DPHY_PSM_CFG DPHY_PCS(0x4) -#define DPHY_PSM_CFG_FROM_REG BIT(0) -#define DPHY_PSM_CLK_DIV(x) ((x) << 1) - struct cdns_dsi_output { struct mipi_dsi_device *dev; struct drm_panel *panel; struct drm_bridge *bridge; + union phy_configure_opts phy_opts; }; enum cdns_dsi_input_id { @@ -467,14 +437,6 @@ enum cdns_dsi_input_id { CDNS_DSC_INPUT, }; -struct cdns_dphy_cfg { - u8 pll_ipdiv; - u8 pll_opdiv; - u16 pll_fbdiv; - unsigned long lane_bps; - unsigned int nlanes; -}; - struct cdns_dsi_cfg { unsigned int hfp; unsigned int hsa; @@ -483,34 +445,6 @@ struct cdns_dsi_cfg { unsigned int htotal; }; -struct cdns_dphy; - -enum cdns_dphy_clk_lane_cfg { - DPHY_CLK_CFG_LEFT_DRIVES_ALL = 0, - DPHY_CLK_CFG_LEFT_DRIVES_RIGHT = 1, - DPHY_CLK_CFG_LEFT_DRIVES_LEFT = 2, - DPHY_CLK_CFG_RIGHT_DRIVES_ALL = 3, -}; - -struct cdns_dphy_ops { - int (*probe)(struct cdns_dphy *dphy); - void (*remove)(struct cdns_dphy *dphy); - void (*set_psm_div)(struct cdns_dphy *dphy, u8 div); - void (*set_clk_lane_cfg)(struct cdns_dphy *dphy, - enum cdns_dphy_clk_lane_cfg cfg); - void (*set_pll_cfg)(struct cdns_dphy *dphy, - const struct cdns_dphy_cfg *cfg); - unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy); -}; - -struct cdns_dphy { - struct cdns_dphy_cfg cfg; - void __iomem *regs; - struct clk *psm_clk; - struct clk *pll_ref_clk; - const struct cdns_dphy_ops *ops; -}; - struct cdns_dsi_input { enum cdns_dsi_input_id id; struct drm_bridge bridge; @@ -528,7 +462,7 @@ struct cdns_dsi { struct reset_control *dsi_p_rst; struct clk *dsi_sys_clk; bool link_initialized; - struct cdns_dphy *dphy; + struct phy *dphy; }; static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input) @@ -547,173 +481,13 @@ bridge_to_cdns_dsi_input(struct drm_bridge *bridge) return container_of(bridge, struct cdns_dsi_input, bridge); } -static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, - struct cdns_dphy_cfg *cfg, - unsigned int dpi_htotal, - unsigned int dpi_bpp, - unsigned int dpi_hz, - unsigned int dsi_htotal, - unsigned int dsi_nlanes, - unsigned int *dsi_hfp_ext) -{ - u64 dlane_bps, dlane_bps_max, fbdiv, fbdiv_max, adj_dsi_htotal; - unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); - - memset(cfg, 0, sizeof(*cfg)); - - cfg->nlanes = dsi_nlanes; - - if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000) - return -EINVAL; - else if (pll_ref_hz < 19200000) - cfg->pll_ipdiv = 1; - else if (pll_ref_hz < 38400000) - cfg->pll_ipdiv = 2; - else if (pll_ref_hz < 76800000) - cfg->pll_ipdiv = 4; - else - cfg->pll_ipdiv = 8; - - /* - * Make sure DSI htotal is aligned on a lane boundary when calculating - * the expected data rate. This is done by extending HFP in case of - * misalignment. - */ - adj_dsi_htotal = dsi_htotal; - if (dsi_htotal % dsi_nlanes) - adj_dsi_htotal += dsi_nlanes - (dsi_htotal % dsi_nlanes); - - dlane_bps = (u64)dpi_hz * adj_dsi_htotal; - - /* data rate in bytes/sec is not an integer, refuse the mode. */ - if (do_div(dlane_bps, dsi_nlanes * dpi_htotal)) - return -EINVAL; - - /* data rate was in bytes/sec, convert to bits/sec. */ - dlane_bps *= 8; - - if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL) - return -EINVAL; - else if (dlane_bps >= 1250000000) - cfg->pll_opdiv = 1; - else if (dlane_bps >= 630000000) - cfg->pll_opdiv = 2; - else if (dlane_bps >= 320000000) - cfg->pll_opdiv = 4; - else if (dlane_bps >= 160000000) - cfg->pll_opdiv = 8; - - /* - * Allow a deviation of 0.2% on the per-lane data rate to try to - * recover a potential mismatch between DPI and PPI clks. - */ - dlane_bps_max = dlane_bps + DIV_ROUND_DOWN_ULL(dlane_bps, 500); - fbdiv_max = DIV_ROUND_DOWN_ULL(dlane_bps_max * 2 * - cfg->pll_opdiv * cfg->pll_ipdiv, - pll_ref_hz); - fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv * - cfg->pll_ipdiv, - pll_ref_hz); - - /* - * Iterate over all acceptable fbdiv and try to find an adjusted DSI - * htotal length providing an exact match. - * - * Note that we could do something even trickier by relying on the fact - * that a new line is not necessarily aligned on a lane boundary, so, - * by making adj_dsi_htotal non aligned on a dsi_lanes we can improve a - * bit the precision. With this, the step would be - * - * pll_ref_hz / (2 * opdiv * ipdiv * nlanes) - * - * instead of - * - * pll_ref_hz / (2 * opdiv * ipdiv) - * - * The drawback of this approach is that we would need to make sure the - * number or lines is a multiple of the realignment periodicity which is - * a function of the number of lanes and the original misalignment. For - * example, for NLANES = 4 and HTOTAL % NLANES = 3, it takes 4 lines - * to realign on a lane: - * LINE 0: expected number of bytes, starts emitting first byte of - * LINE 1 on LANE 3 - * LINE 1: expected number of bytes, starts emitting first 2 bytes of - * LINE 2 on LANES 2 and 3 - * LINE 2: expected number of bytes, starts emitting first 3 bytes of - * of LINE 3 on LANES 1, 2 and 3 - * LINE 3: one byte less, now things are realigned on LANE 0 for LINE 4 - * - * I figured this extra complexity was not worth the benefit, but if - * someone really has unfixable mismatch, that would be something to - * investigate. - */ - for (; fbdiv <= fbdiv_max; fbdiv++) { - u32 rem; - - adj_dsi_htotal = (u64)fbdiv * pll_ref_hz * dsi_nlanes * - dpi_htotal; - - /* - * Do the division in 2 steps to avoid an overflow on the - * divider. - */ - rem = do_div(adj_dsi_htotal, dpi_hz); - if (rem) - continue; - - rem = do_div(adj_dsi_htotal, - cfg->pll_opdiv * cfg->pll_ipdiv * 2 * 8); - if (rem) - continue; - - cfg->pll_fbdiv = fbdiv; - *dsi_hfp_ext = adj_dsi_htotal - dsi_htotal; - break; - } - - /* No match, let's just reject the display mode. */ - if (!cfg->pll_fbdiv) - return -EINVAL; - - dlane_bps = DIV_ROUND_DOWN_ULL((u64)dpi_hz * adj_dsi_htotal * 8, - dsi_nlanes * dpi_htotal); - cfg->lane_bps = dlane_bps; - - return 0; -} - -static int cdns_dphy_setup_psm(struct cdns_dphy *dphy) -{ - unsigned long psm_clk_hz = clk_get_rate(dphy->psm_clk); - unsigned long psm_div; - - if (!psm_clk_hz || psm_clk_hz > 100000000) - return -EINVAL; - - psm_div = DIV_ROUND_CLOSEST(psm_clk_hz, 1000000); - if (dphy->ops->set_psm_div) - dphy->ops->set_psm_div(dphy, psm_div); - - return 0; -} - -static void cdns_dphy_set_clk_lane_cfg(struct cdns_dphy *dphy, - enum cdns_dphy_clk_lane_cfg cfg) -{ - if (dphy->ops->set_clk_lane_cfg) - dphy->ops->set_clk_lane_cfg(dphy, cfg); -} - -static void cdns_dphy_set_pll_cfg(struct cdns_dphy *dphy, - const struct cdns_dphy_cfg *cfg) +static unsigned int mode_to_dpi_hfp(const struct drm_display_mode *mode, + bool mode_valid_check) { - if (dphy->ops->set_pll_cfg) - dphy->ops->set_pll_cfg(dphy, cfg); -} + if (mode_valid_check) + return mode->hsync_start - mode->hdisplay; -static unsigned long cdns_dphy_get_wakeup_time_ns(struct cdns_dphy *dphy) -{ - return dphy->ops->get_wakeup_time_ns(dphy); + return mode->crtc_hsync_start - mode->crtc_hdisplay; } static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing, @@ -733,14 +507,12 @@ static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing, static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, const struct drm_display_mode *mode, struct cdns_dsi_cfg *dsi_cfg, - struct cdns_dphy_cfg *dphy_cfg, bool mode_valid_check) { - unsigned long dsi_htotal = 0, dsi_hss_hsa_hse_hbp = 0; struct cdns_dsi_output *output = &dsi->output; - unsigned int dsi_hfp_ext = 0, dpi_hfp, tmp; + unsigned int tmp; bool sync_pulse = false; - int bpp, nlanes, ret; + int bpp, nlanes; memset(dsi_cfg, 0, sizeof(*dsi_cfg)); @@ -759,8 +531,6 @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, mode->crtc_hsync_end : mode->crtc_hsync_start); dsi_cfg->hbp = dpi_to_dsi_timing(tmp, bpp, DSI_HBP_FRAME_OVERHEAD); - dsi_htotal += dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD; - dsi_hss_hsa_hse_hbp += dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD; if (sync_pulse) { if (mode_valid_check) @@ -770,49 +540,104 @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, dsi_cfg->hsa = dpi_to_dsi_timing(tmp, bpp, DSI_HSA_FRAME_OVERHEAD); - dsi_htotal += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD; - dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD; } dsi_cfg->hact = dpi_to_dsi_timing(mode_valid_check ? mode->hdisplay : mode->crtc_hdisplay, bpp, 0); - dsi_htotal += dsi_cfg->hact; + dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check), + bpp, DSI_HFP_FRAME_OVERHEAD); - if (mode_valid_check) - dpi_hfp = mode->hsync_start - mode->hdisplay; - else - dpi_hfp = mode->crtc_hsync_start - mode->crtc_hdisplay; + return 0; +} + +static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi, + struct cdns_dsi_cfg *dsi_cfg, + struct phy_configure_opts_mipi_dphy *phy_cfg, + const struct drm_display_mode *mode, + bool mode_valid_check) +{ + struct cdns_dsi_output *output = &dsi->output; + unsigned long long dlane_bps; + unsigned long adj_dsi_htotal; + unsigned long dsi_htotal; + unsigned long dpi_htotal; + unsigned long dpi_hz; + unsigned int dsi_hfp_ext; + unsigned int lanes = output->dev->lanes; + + dsi_htotal = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD; + if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + dsi_htotal += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD; - dsi_cfg->hfp = dpi_to_dsi_timing(dpi_hfp, bpp, DSI_HFP_FRAME_OVERHEAD); + dsi_htotal += dsi_cfg->hact; dsi_htotal += dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD; - if (mode_valid_check) - ret = cdns_dsi_get_dphy_pll_cfg(dsi->dphy, dphy_cfg, - mode->htotal, bpp, - mode->clock * 1000, - dsi_htotal, nlanes, - &dsi_hfp_ext); - else - ret = cdns_dsi_get_dphy_pll_cfg(dsi->dphy, dphy_cfg, - mode->crtc_htotal, bpp, - mode->crtc_clock * 1000, - dsi_htotal, nlanes, - &dsi_hfp_ext); + /* + * Make sure DSI htotal is aligned on a lane boundary when calculating + * the expected data rate. This is done by extending HFP in case of + * misalignment. + */ + adj_dsi_htotal = dsi_htotal; + if (dsi_htotal % lanes) + adj_dsi_htotal += lanes - (dsi_htotal % lanes); + + dpi_hz = (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000; + dlane_bps = (unsigned long long)d |