diff options
| -rw-r--r-- | arch/powerpc/include/asm/nohash/32/pte-8xx.h | 3 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/nohash/pgtable.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 5 |
3 files changed, 3 insertions, 7 deletions
diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h b/arch/powerpc/include/asm/nohash/32/pte-8xx.h index 6dc0180fd5c7..19a5ecaef265 100644 --- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h +++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h @@ -41,8 +41,7 @@ #define _PAGE_GUARDED 0x0010 /* Copied to L1 G entry in DTLB */ #define _PAGE_USER 0x0020 /* Copied to L1 APG lsb */ #define _PAGE_EXEC 0x0040 /* Copied to L1 APG */ -#define _PAGE_WRITETHRU 0x0080 /* software: caching is write through */ -#define _PAGE_ACCESSED 0x0800 /* software: page referenced */ +#define _PAGE_ACCESSED 0x0080 /* software: page referenced */ #define _PAGE_RO 0x0600 /* Supervisor RO, User no access */ diff --git a/arch/powerpc/include/asm/nohash/pgtable.h b/arch/powerpc/include/asm/nohash/pgtable.h index fc4376c8d444..e0864e683cf9 100644 --- a/arch/powerpc/include/asm/nohash/pgtable.h +++ b/arch/powerpc/include/asm/nohash/pgtable.h @@ -235,8 +235,10 @@ extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addre #define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ _PAGE_COHERENT)) +#if _PAGE_WRITETHRU != 0 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ _PAGE_COHERENT | _PAGE_WRITETHRU)) +#endif #define pgprot_cached_noncoherent(prot) \ (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL)) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 641c9a9d4db2..6399dcadf51d 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -486,10 +486,6 @@ _ENTRY(DTLBMiss_jmp) * above. */ rlwimi r11, r10, 0, 26, 27 - /* Insert the WriteThru flag into the TWC from the Linux PTE. - * It is bit 25 in the Linux PTE and bit 30 in the TWC - */ - rlwimi r11, r10, 32-5, 30, 30 mtspr SPRN_MD_TWC, r11 /* In 4k pages mode, SPS (bit 28) in RPN must match PS[1] (bit 29) @@ -523,7 +519,6 @@ _ENTRY(DTLBMiss_jmp) #else rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ #endif - rlwimi r10, r11, 0, 20, 20 /* clear 20 */ mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ /* Restore registers */ |