Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.4 kernel cycle:

  Core changes:

   - Fix errors in example code in the documentation.

  New drivers:

   - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
     Ingenic driver.

   - Support Cirrus Logic Madera CS47L92 and CS47L15.

   - Support Allwinner Sunxi V3S.

   - Support Aspeed 2600 BMC.

   - Support Qualcomm SC7180.

   - Support Marvell MVEBU CS115.

  Driver improvements:

   - Clean up a few drivers to use the devm_platform_ioremap_resource()
     helper.

   - Pass the irqchip when registering the gpio_chip in some pin
     controllers that are also GPIO controllers.

   - Support suspend/resume in the Tegra driver.

   - Support pull-up on the Broadcom BCM2711.

   - The Intel driver can now request locked pads.

   - Fix the UFS reset pin in the Qualcomm SDM845 driver"

* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
  pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
  pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
  pinctrl: bcm: remove redundant assignment to pointer log
  pinctrl: iproc: Add 'get_direction' support
  pinctrl: iproc-gpio: Handle interrupts for multiple instances
  pinctrl: iproc-gpio: Fix incorrect pinconf configurations
  pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
  pinctrl: qcom: sdm845: Fix UFS_RESET pin
  pinctrl: mvebu: add additional variant for standalone CP115
  pinctrl: mvebu: Add CP110 missing pin functionality
  dt-bindings: cp110: document the new CP115 pinctrl compatible
  pinctrl: bcm2835: Pass irqchip when adding gpiochip
  pinctrl: meson: meson: Add of_node_put() before return
  pinctrl/gpio: Take MUX usage into account
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
  pinctrl: amd: disable spurious-firing GPIO IRQs
  pinctrl: rza2: Include the appropriate headers
  pinctrl: rza2: Drop driver use of consumer flags
  ...

81 files changed, 7597 insertions, 2295 deletions

diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig
index 4cf54172f8fb..de8b185c4fee 100644
--- a/drivers/pinctrl/aspeed/Kconfig
+++ b/drivers/pinctrl/aspeed/Kconfig
@@ -23,3 +23,11 @@ config PINCTRL_ASPEED_G5
 	help
 	  Say Y here to enable pin controller support for Aspeed's 5th
 	  generation SoCs. GPIO is provided by a separate GPIO driver.
+
+config PINCTRL_ASPEED_G6
+	bool "Aspeed G6 SoC pin control"
+	depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF
+	select PINCTRL_ASPEED
+	help
+	  Say Y here to enable pin controller support for Aspeed's 6th
+	  generation SoCs. GPIO is provided by a separate GPIO driver.
diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile
index ea8962645e49..489ea1778353 100644
--- a/drivers/pinctrl/aspeed/Makefile
+++ b/drivers/pinctrl/aspeed/Makefile
@@ -5,3 +5,4 @@ ccflags-y += $(call cc-option,-Woverride-init)
 obj-$(CONFIG_PINCTRL_ASPEED)	+= pinctrl-aspeed.o pinmux-aspeed.o
 obj-$(CONFIG_PINCTRL_ASPEED_G4)	+= pinctrl-aspeed-g4.o
 obj-$(CONFIG_PINCTRL_ASPEED_G5)	+= pinctrl-aspeed-g5.o
+obj-$(CONFIG_PINCTRL_ASPEED_G6)	+= pinctrl-aspeed-g6.o
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index 22256576b69a..95ea593fa29d 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -21,6 +21,13 @@
 #include "pinmux-aspeed.h"
 #include "pinctrl-aspeed.h"
 
+/* Wrap some of the common macros for clarity */
+#define SIG_EXPR_DECL_SINGLE(sig, func, ...) \
+	SIG_EXPR_DECL(sig, func, func, __VA_ARGS__)
+
+#define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG
+#define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG
+
 /*
  * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
  * references registers by the device/offset mnemonic. The register macros
@@ -80,16 +87,16 @@ SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
 #define I2C9_DESC	SIG_DESC_SET(SCU90, 22)
 
 #define C5 4
-SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4));
-MS_PIN_DECL(C5, GPIOA4, SCL9, TIMER5);
+SIG_EXPR_LIST_DECL_SINGLE(C5, SCL9, I2C9, I2C9_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(C5, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4));
+PIN_DECL_2(C5, GPIOA4, SCL9, TIMER5);
 
 FUNC_GROUP_DECL(TIMER5, C5);
 
 #define B4 5
-SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5));
-MS_PIN_DECL(B4, GPIOA5, SDA9, TIMER6);
+SIG_EXPR_LIST_DECL_SINGLE(B4, SDA9, I2C9, I2C9_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(B4, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5));
+PIN_DECL_2(B4, GPIOA5, SDA9, TIMER6);
 
 FUNC_GROUP_DECL(TIMER6, B4);
 FUNC_GROUP_DECL(I2C9, C5, B4);
@@ -97,16 +104,16 @@ FUNC_GROUP_DECL(I2C9, C5, B4);
 #define MDIO2_DESC	SIG_DESC_SET(SCU90, 2)
 
 #define A3 6
-SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6));
-MS_PIN_DECL(A3, GPIOA6, MDC2, TIMER7);
+SIG_EXPR_LIST_DECL_SINGLE(A3, MDC2, MDIO2, MDIO2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(A3, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6));
+PIN_DECL_2(A3, GPIOA6, MDC2, TIMER7);
 
 FUNC_GROUP_DECL(TIMER7, A3);
 
 #define D5 7
-SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7));
-MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8);
+SIG_EXPR_LIST_DECL_SINGLE(D5, MDIO2, MDIO2, MDIO2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(D5, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7));
+PIN_DECL_2(D5, GPIOA7, MDIO2, TIMER8);
 
 FUNC_GROUP_DECL(TIMER8, D5);
 FUNC_GROUP_DECL(MDIO2, A3, D5);
@@ -124,18 +131,18 @@ SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10));
 SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11));
 
 #define E19 12
-SIG_EXPR_DECL(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12));
-SIG_EXPR_DECL(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14));
-SIG_EXPR_LIST_DECL_DUAL(LPCRST, LPCRST, LPCRSTS);
-SS_PIN_DECL(E19, GPIOB4, LPCRST);
+SIG_EXPR_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12));
+SIG_EXPR_DECL_SINGLE(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14));
+SIG_EXPR_LIST_DECL_DUAL(E19, LPCRST, LPCRST, LPCRSTS);
+PIN_DECL_1(E19, GPIOB4, LPCRST);
 
 FUNC_GROUP_DECL(LPCRST, E19);
 
 #define H19 13
 #define H19_DESC        SIG_DESC_SET(SCU80, 13)
-SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC);
-MS_PIN_DECL(H19, GPIOB5, LPCPD, LPCSMI);
+SIG_EXPR_LIST_DECL_SINGLE(H19, LPCPD, LPCPD, H19_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(H19, LPCSMI, LPCSMI, H19_DESC);
+PIN_DECL_2(H19, GPIOB5, LPCPD, LPCSMI);
 
 FUNC_GROUP_DECL(LPCPD, H19);
 FUNC_GROUP_DECL(LPCSMI, H19);
@@ -144,14 +151,14 @@ FUNC_GROUP_DECL(LPCSMI, H19);
 SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
 
 #define E18 15
-SIG_EXPR_LIST_DECL_SINGLE(EXTRST, EXTRST,
+SIG_EXPR_LIST_DECL_SINGLE(E18, EXTRST, EXTRST,
 		SIG_DESC_SET(SCU80, 15),
 		SIG_DESC_BIT(SCU90, 31, 0),
 		SIG_DESC_SET(SCU3C, 3));
-SIG_EXPR_LIST_DECL_SINGLE(SPICS1, SPICS1,
+SIG_EXPR_LIST_DECL_SINGLE(E18, SPICS1, SPICS1,
 		SIG_DESC_SET(SCU80, 15),
 		SIG_DESC_SET(SCU90, 31));
-MS_PIN_DECL(E18, GPIOB7, EXTRST, SPICS1);
+PIN_DECL_2(E18, GPIOB7, EXTRST, SPICS1);
 
 FUNC_GROUP_DECL(EXTRST, E18);
 FUNC_GROUP_DECL(SPICS1, E18);
@@ -160,56 +167,56 @@ FUNC_GROUP_DECL(SPICS1, E18);
 #define I2C10_DESC	SIG_DESC_SET(SCU90, 23)
 
 #define C4 16
-SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC);
-MS_PIN_DECL(C4, GPIOC0, SD1CLK, SCL10);
+SIG_EXPR_LIST_DECL_SINGLE(C4, SD1CLK, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(C4, SCL10, I2C10, I2C10_DESC);
+PIN_DECL_2(C4, GPIOC0, SD1CLK, SCL10);
 
 #define B3 17
-SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC);
-MS_PIN_DECL(B3, GPIOC1, SD1CMD, SDA10);
+SIG_EXPR_LIST_DECL_SINGLE(B3, SD1CMD, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(B3, SDA10, I2C10, I2C10_DESC);
+PIN_DECL_2(B3, GPIOC1, SD1CMD, SDA10);
 
 FUNC_GROUP_DECL(I2C10, C4, B3);
 
 #define I2C11_DESC	SIG_DESC_SET(SCU90, 24)
 
 #define A2 18
-SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC);
-MS_PIN_DECL(A2, GPIOC2, SD1DAT0, SCL11);
+SIG_EXPR_LIST_DECL_SINGLE(A2, SD1DAT0, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(A2, SCL11, I2C11, I2C11_DESC);
+PIN_DECL_2(A2, GPIOC2, SD1DAT0, SCL11);
 
 #define E5 19
-SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC);
-MS_PIN_DECL(E5, GPIOC3, SD1DAT1, SDA11);
+SIG_EXPR_LIST_DECL_SINGLE(E5, SD1DAT1, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(E5, SDA11, I2C11, I2C11_DESC);
+PIN_DECL_2(E5, GPIOC3, SD1DAT1, SDA11);
 
 FUNC_GROUP_DECL(I2C11, A2, E5);
 
 #define I2C12_DESC	SIG_DESC_SET(SCU90, 25)
 
 #define D4 20
-SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC);
-MS_PIN_DECL(D4, GPIOC4, SD1DAT2, SCL12);
+SIG_EXPR_LIST_DECL_SINGLE(D4, SD1DAT2, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(D4, SCL12, I2C12, I2C12_DESC);
+PIN_DECL_2(D4, GPIOC4, SD1DAT2, SCL12);
 
 #define C3 21
-SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC);
-MS_PIN_DECL(C3, GPIOC5, SD1DAT3, SDA12);
+SIG_EXPR_LIST_DECL_SINGLE(C3, SD1DAT3, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(C3, SDA12, I2C12, I2C12_DESC);
+PIN_DECL_2(C3, GPIOC5, SD1DAT3, SDA12);
 
 FUNC_GROUP_DECL(I2C12, D4, C3);
 
 #define I2C13_DESC	SIG_DESC_SET(SCU90, 26)
 
 #define B2 22
-SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC);
-MS_PIN_DECL(B2, GPIOC6, SD1CD, SCL13);
+SIG_EXPR_LIST_DECL_SINGLE(B2, SD1CD, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(B2, SCL13, I2C13, I2C13_DESC);
+PIN_DECL_2(B2, GPIOC6, SD1CD, SCL13);
 
 #define A1 23
-SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC);
-SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC);
-MS_PIN_DECL(A1, GPIOC7, SD1WP, SDA13);
+SIG_EXPR_LIST_DECL_SINGLE(A1, SD1WP, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(A1, SDA13, I2C13, I2C13_DESC);
+PIN_DECL_2(A1, GPIOC7, SD1WP, SDA13);
 
 FUNC_GROUP_DECL(I2C13, B2, A1);
 FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1);
@@ -219,72 +226,72 @@ FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1);
 #define GPID0_DESC	SIG_DESC_SET(SCU8C, 8)
 
 #define A18 24
-SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC);
-SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID);
-MS_PIN_DECL(A18, GPIOD0, SD2CLK, GPID0IN);
+SIG_EXPR_LIST_DECL_SINGLE(A18, SD2CLK, SD2, SD2_DESC);
+SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC);
+SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(A18, GPID0IN, GPID0, GPID);
+PIN_DECL_2(A18, GPIOD0, SD2CLK, GPID0IN);
 
 #define D16 25
-SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC);
-SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID);
-MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT);
+SIG_EXPR_LIST_DECL_SINGLE(D16, SD2CMD, SD2, SD2_DESC);
+SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC);
+SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(D16, GPID0OUT, GPID0, GPID);
+PIN_DECL_2(D16, GPIOD1, SD2CMD, GPID0OUT);
 
 FUNC_GROUP_DECL(GPID0, A18, D16);
 
 #define GPID2_DESC	SIG_DESC_SET(SCU8C, 9)
 
 #define B17 26
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
-SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
-MS_PIN_DECL(B17, GPIOD2, SD2DAT0, GPID2IN);
+SIG_EXPR_LIST_DECL_SINGLE(B17, SD2DAT0, SD2, SD2_DESC);
+SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC);
+SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(B17, GPID2IN, GPID2, GPID);
+PIN_DECL_2(B17, GPIOD2, SD2DAT0, GPID2IN);
 
 #define A17 27
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
-SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
-MS_PIN_DECL(A17, GPIOD3, SD2DAT1, GPID2OUT);
+SIG_EXPR_LIST_DECL_SINGLE(A17, SD2DAT1, SD2, SD2_DESC);
+SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC);
+SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(A17, GPID2OUT, GPID2, GPID);
+PIN_DECL_2(A17, GPIOD3, SD2DAT1, GPID2OUT);
 
 FUNC_GROUP_DECL(GPID2, B17, A17);
 
 #define GPID4_DESC	SIG_DESC_SET(SCU8C, 10)
 
 #define C16 28
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC);
-SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID);
-MS_PIN_DECL(C16, GPIOD4, SD2DAT2, GPID4IN);
+SIG_EXPR_LIST_DECL_SINGLE(C16, SD2DAT2, SD2, SD2_DESC);
+SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC);
+SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(C16, GPID4IN, GPID4, GPID);
+PIN_DECL_2(C16, GPIOD4, SD2DAT2, GPID4IN);
 
 #define B16 29
-SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC);
-SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID);
-MS_PIN_DECL(B16, GPIOD5, SD2DAT3, GPID4OUT);
+SIG_EXPR_LIST_DECL_SINGLE(B16, SD2DAT3, SD2, SD2_DESC);
+SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC);
+SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(B16, GPID4OUT, GPID4, GPID);
+PIN_DECL_2(B16, GPIOD5, SD2DAT3, GPID4OUT);
 
 FUNC_GROUP_DECL(GPID4, C16, B16);
 
 #define GPID6_DESC	SIG_DESC_SET(SCU8C, 11)
 
 #define A16 30
-SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC);
-SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC);
-SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC);
-SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID);
-MS_PIN_DECL(A16, GPIOD6, SD2CD, GPID6IN);
+SIG_EXPR_LIST_DECL_SINGLE(A16, SD2CD, SD2, SD2_DESC);
+SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC);
+SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(A16, GPID6IN, GPID6, GPID);
+PIN_DECL_2(A16, GPIOD6, SD2CD, GPID6IN);
 
 #define E15