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| author | Jyri Sarha <jsarha@ti.com> | 2020-01-08 10:30:08 +0200 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2020-04-24 14:50:23 +0530 |
| commit | 7ae14cf581f2cdd2ebae29ca5b3d42bdfebca597 (patch) | |
| tree | 781db0ef1b9053d1b8360af3642e30dda48c4cf2 /drivers/phy/qualcomm/phy-qcom-qmp.c | |
| parent | 8f3d9f354286745c751374f5f1fcafee6b3f3136 (diff) | |
phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver
For DisplayPort use we need to set WIZ_CONFIG_LANECTL register's
P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the
P_ENABLE bits of the same register are set to P_ENABLE instead of
P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable
the lane as needed. The DisplayPort mode is selected according to
"cdns,phy-type"-properties found in link subnodes under the managed
serdes (see "ti,sierra-phy-t0" and "ti,j721e-serdes-10g" devicetree
bindings for details). All other values of "cdns,phy-type"-property
but PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits
to force enable.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp.c')
0 files changed, 0 insertions, 0 deletions