diff options
author | Kishon Vijay Abraham I <kishon@ti.com> | 2017-02-15 18:48:14 +0530 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-02-21 15:00:26 -0600 |
commit | 442ec4c04d1235f8c664a74004dae54a7a574d18 (patch) | |
tree | 66e1b54e8cabd635a378b48307175dac998fa47b /drivers/pci/dwc/pcie-qcom.c | |
parent | 40f67fb2c384fe12741aa35010d62bfe8c98286c (diff) |
PCI: dwc: all: Split struct pcie_port into host-only and core structures
Keep only the host-specific members in struct pcie_port and move the common
members (i.e common to both host and endpoint) to struct dw_pcie. This is
in preparation for adding endpoint mode support to designware driver.
While at that also fix checkpatch warnings.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Richard Zhu <hongxing.zhu@nxp.com>
CC: Lucas Stach <l.stach@pengutronix.de>
CC: Murali Karicheri <m-karicheri2@ti.com>
CC: Minghuan Lian <minghuan.Lian@freescale.com>
CC: Mingkai Hu <mingkai.hu@freescale.com>
CC: Roy Zang <tie-fei.zang@freescale.com>
CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
CC: Niklas Cassel <niklas.cassel@axis.com>
CC: Jesper Nilsson <jesper.nilsson@axis.com>
CC: Joao Pinto <Joao.Pinto@synopsys.com>
CC: Zhou Wang <wangzhou1@hisilicon.com>
CC: Gabriele Paoloni <gabriele.paoloni@huawei.com>
CC: Stanimir Varbanov <svarbanov@mm-sol.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>
Diffstat (limited to 'drivers/pci/dwc/pcie-qcom.c')
-rw-r--r-- | drivers/pci/dwc/pcie-qcom.c | 70 |
1 files changed, 45 insertions, 25 deletions
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c index ac27b67d303e..e36abe0d9d6f 100644 --- a/drivers/pci/dwc/pcie-qcom.c +++ b/drivers/pci/dwc/pcie-qcom.c @@ -103,7 +103,7 @@ struct qcom_pcie_ops { }; struct qcom_pcie { - struct pcie_port pp; /* pp.dbi_base is DT dbi */ + struct dw_pcie *pci; void __iomem *parf; /* DT parf */ void __iomem *elbi; /* DT elbi */ union qcom_pcie_resources res; @@ -112,7 +112,7 @@ struct qcom_pcie { struct qcom_pcie_ops *ops; }; -#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp) +#define to_qcom_pcie(x) dev_get_drvdata((x)->dev) static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { @@ -155,21 +155,23 @@ static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie) static int qcom_pcie_establish_link(struct qcom_pcie *pcie) { + struct dw_pcie *pci = pcie->pci; - if (dw_pcie_link_up(&pcie->pp)) + if (dw_pcie_link_up(pci)) return 0; /* Enable Link Training state machine */ if (pcie->ops->ltssm_enable) pcie->ops->ltssm_enable(pcie); - return dw_pcie_wait_for_link(&pcie->pp); + return dw_pcie_wait_for_link(pci); } static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_v0 *res = &pcie->res.v0; - struct device *dev = pcie->pp.dev; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; res->vdda = devm_regulator_get(dev, "vdda"); if (IS_ERR(res->vdda)) @@ -218,7 +220,8 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie) static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie) { struct qcom_pcie_resources_v1 *res = &pcie->res.v1; - struct device *dev = pcie->pp.dev; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; res->vdda = devm_regulator_get(dev, "vdda"); if (IS_ERR(res->vdda)) @@ -264,7 +267,8 @@ static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie) static int qcom_pcie_init_v0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_v0 *res = &pcie->res.v0; - struct device *dev = pcie->pp.dev; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; u32 val; int ret; @@ -386,7 +390,8 @@ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie) static int qcom_pcie_init_v1(struct qcom_pcie *pcie) { struct qcom_pcie_resources_v1 *res = &pcie->res.v1; - struct device *dev = pcie->pp.dev; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; int ret; ret = reset_control_deassert(res->core); @@ -453,7 +458,8 @@ err_res: static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_v2 *res = &pcie->res.v2; - struct device *dev = pcie->pp.dev; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; res->aux_clk = devm_clk_get(dev, "aux"); if (IS_ERR(res->aux_clk)) @@ -478,7 +484,8 @@ static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie) static int qcom_pcie_init_v2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_v2 *res = &pcie->res.v2; - struct device *dev = pcie->pp.dev; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; u32 val; int ret; @@ -542,7 +549,8 @@ err_cfg_clk: static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_v2 *res = &pcie->res.v2; - struct device *dev = pcie->pp.dev; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; int ret; ret = clk_prepare_enable(res->pipe_clk); @@ -554,10 +562,9 @@ static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie) return 0; } -static int qcom_pcie_link_up(struct pcie_port *pp) +static int qcom_pcie_link_up(struct dw_pcie *pci) { - struct qcom_pcie *pcie = to_qcom_pcie(pp); - u16 val = readw(pcie->pp.dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA); + u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA); return !!(val & PCI_EXP_LNKSTA_DLLLA); } @@ -575,7 +582,8 @@ static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie) static void qcom_pcie_host_init(struct pcie_port *pp) { - struct qcom_pcie *pcie = to_qcom_pcie(pp); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie = to_qcom_pcie(pci); int ret; qcom_ep_reset_assert(pcie); @@ -613,19 +621,20 @@ err_deinit: static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val) { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + /* the device class is not reported correctly from the register */ if (where == PCI_CLASS_REVISION && size == 4) { - *val = readl(pp->dbi_base + PCI_CLASS_REVISION); + *val = readl(pci->dbi_base + PCI_CLASS_REVISION); *val &= 0xff; /* keep revision id */ *val |= PCI_CLASS_BRIDGE_PCI << 16; return PCIBIOS_SUCCESSFUL; } - return dw_pcie_read(pp->dbi_base + where, size, val); + return dw_pcie_read(pci->dbi_base + where, size, val); } -static struct pcie_host_ops qcom_pcie_dw_ops = { - .link_up = qcom_pcie_link_up, +static struct dw_pcie_host_ops qcom_pcie_dw_ops = { .host_init = qcom_pcie_host_init, .rd_own_conf = qcom_pcie_rd_own_conf, }; @@ -652,19 +661,31 @@ static const struct qcom_pcie_ops ops_v2 = { .ltssm_enable = qcom_pcie_v2_ltssm_enable, }; +static const struct dw_pcie_ops dw_pcie_ops = { + .link_up = qcom_pcie_link_up, +}; + static int qcom_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *res; - struct qcom_pcie *pcie; struct pcie_port *pp; + struct dw_pcie *pci; + struct qcom_pcie *pcie; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; - pp = &pcie->pp; + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pci->dev = dev; + pci->ops = &dw_pcie_ops; + pp = &pci->pp; + pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev); pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW); @@ -677,9 +698,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) return PTR_ERR(pcie->parf); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); - pp->dbi_base = devm_ioremap_resource(dev, res); - if (IS_ERR(pp->dbi_base)) - return PTR_ERR(pp->dbi_base); + pci->dbi_base = devm_ioremap_resource(dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); pcie->elbi = devm_ioremap_resource(dev, res); @@ -690,7 +711,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) if (IS_ERR(pcie->phy)) return PTR_ERR(pcie->phy); - pp->dev = dev; ret = pcie->ops->get_resources(pcie); if (ret) return ret; |