diff options
author | Eilon Greenstein <eilong@broadcom.com> | 2008-06-23 20:29:02 -0700 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-06-23 20:29:02 -0700 |
commit | ad8d394804b355bc623decc50748cd01dbc0783b (patch) | |
tree | be2d1c7fc15fc6e1bd17a7d87c697254407fa865 /drivers/net/bnx2x_init_values.h | |
parent | c18487ee24381b40df3b8b4f54dd13ee9367a1ce (diff) |
bnx2x: New init infrastructure
This new initialization code supports the 57711 HW. It also supports
the emulation and FPGA for the 57711 and 57710 initializations values
(very small amount of code which is very helpful in the lab - less
than 30 lines).
The initialization is done via DMAE after the DMAE block is ready -
before it is ready, some of the initialization is done via PCI
configuration transactions (referred to as indirect write). A mutex
to protect the DMAE from being overlapped was added. There are few
new registers which needs to be initialized by SW - the full comment
for those registers is added to the register file. A place holder for
the 57711 (referred to as E1H) microcode was added- the microcode
itself is too big and it is split over the following 4 patches
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_init_values.h')
-rw-r--r-- | drivers/net/bnx2x_init_values.h | 2149 |
1 files changed, 1633 insertions, 516 deletions
diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h index bef0a9b19d68..41adbec37bdf 100644 --- a/drivers/net/bnx2x_init_values.h +++ b/drivers/net/bnx2x_init_values.h @@ -57,6 +57,7 @@ static const struct raw_op init_ops[] = { {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0}, {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0}, {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0}, + {OP_WR_E1H, PRS_REG_FCOE_TYPE, 0x8906}, {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff}, {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff}, {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff}, @@ -74,23 +75,27 @@ static const struct raw_op init_ops[] = { {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f}, {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f}, {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f}, -#define PRS_COMMON_END 46 -#define PRS_PORT0_START 46 - {OP_WR, PRS_REG_CID_PORT_0, 0x0}, -#define PRS_PORT0_END 47 -#define PRS_PORT1_START 47 - {OP_WR, PRS_REG_CID_PORT_1, 0x800000}, -#define PRS_PORT1_END 48 +#define PRS_COMMON_END 47 +#define SRCH_COMMON_START 47 + {OP_WR_E1H, SRC_REG_E1HMF_ENABLE, 0x1}, +#define SRCH_COMMON_END 48 #define TSDM_COMMON_START 48 - {OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x411}, - {OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400}, - {OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x404}, - {OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419}, + {OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411}, + {OP_WR_E1H, TSDM_REG_CFC_RSP_START_ADDR, 0x211}, + {OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400}, + {OP_WR_E1H, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200}, + {OP_WR_E1, TSDM_REG_Q_COUNTER_START_ADDR, 0x404}, + {OP_WR_E1H, TSDM_REG_Q_COUNTER_START_ADDR, 0x204}, + {OP_WR_E1, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419}, + {OP_WR_E1H, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219}, {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff}, {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff}, {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff}, {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff}, - {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x80}, + {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x2}, + {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34}, + {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35}, + {OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x7c}, {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff}, {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f}, {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff}, @@ -109,9 +114,12 @@ static const struct raw_op init_ops[] = { {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, - {OP_WR, TSDM_REG_TIMER_TICK, 0x3e8}, -#define TSDM_COMMON_END 76 -#define TCM_COMMON_START 76 + {OP_WR_E1, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1}, + {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8}, + {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1}, + {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa}, +#define TSDM_COMMON_END 86 +#define TCM_COMMON_START 86 {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20}, {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32}, {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020}, @@ -143,9 +151,14 @@ static const struct raw_op init_ops[] = { {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8}, {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4}, {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6}, - {OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd}, - {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d}, - {OP_ZR, TCM_REG_PHYS_QNUM1_0, 0x6}, + {OP_WR_E1, TCM_REG_PHYS_QNUM0_0, 0xd}, + {OP_WR_E1, TCM_REG_PHYS_QNUM0_1, 0x2d}, + {OP_WR_E1, TCM_REG_PHYS_QNUM1_0, 0x7}, + {OP_WR_E1, TCM_REG_PHYS_QNUM1_1, 0x27}, + {OP_WR_E1, TCM_REG_PHYS_QNUM2_0, 0x7}, + {OP_WR_E1, TCM_REG_PHYS_QNUM2_1, 0x27}, + {OP_WR_E1, TCM_REG_PHYS_QNUM3_0, 0x7}, + {OP_WR_E1, TCM_REG_PHYS_QNUM3_1, 0x27}, {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1}, {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1}, {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1}, @@ -162,23 +175,75 @@ static const struct raw_op init_ops[] = { {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1}, {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1}, {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1}, -#define TCM_COMMON_END 126 -#define BRB1_COMMON_START 126 +#define TCM_COMMON_END 141 +#define TCM_FUNC0_START 141 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0xd}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x7}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x7}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x7}, +#define TCM_FUNC0_END 145 +#define TCM_FUNC1_START 145 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x2d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x27}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x27}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x27}, +#define TCM_FUNC1_END 149 +#define TCM_FUNC2_START 149 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x1d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x17}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x17}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x17}, +#define TCM_FUNC2_END 153 +#define TCM_FUNC3_START 153 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x3d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x37}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x37}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x37}, +#define TCM_FUNC3_END 157 +#define TCM_FUNC4_START 157 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x4d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x47}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x47}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x47}, +#define TCM_FUNC4_END 161 +#define TCM_FUNC5_START 161 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x6d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x67}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x67}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x67}, +#define TCM_FUNC5_END 165 +#define TCM_FUNC6_START 165 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x5d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x57}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x57}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x57}, +#define TCM_FUNC6_END 169 +#define TCM_FUNC7_START 169 + {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x7d}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x77}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x77}, + {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x77}, +#define TCM_FUNC7_END 173 +#define BRB1_COMMON_START 173 {OP_SW, BRB1_REG_LL_RAM, 0x2000020}, {OP_WR, BRB1_REG_SOFT_RESET, 0x1}, - {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0}, - {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0}, - {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_2, 0x0}, - {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_3, 0x0}, - {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0}, - {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0}, - {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_2, 0x0}, - {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_3, 0x0}, {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0}, {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220}, {OP_WR, BRB1_REG_SOFT_RESET, 0x0}, -#define BRB1_COMMON_END 139 -#define TSEM_COMMON_START 139 +#define BRB1_COMMON_END 178 +#define BRB1_PORT0_START 178 + {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8}, + {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114}, + {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0}, + {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0}, +#define BRB1_PORT0_END 182 +#define BRB1_PORT1_START 182 + {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8}, + {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114}, + {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0}, + {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0}, +#define BRB1_PORT1_END 186 +#define TSEM_COMMON_START 186 {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0}, {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0}, {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0}, @@ -222,106 +287,243 @@ static const struct raw_op init_ops[] = { {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18}, {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc}, {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20}, - {OP_WR, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, + {OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, + {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138}, + {OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388}, {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0x1b3}, - {OP_SW, TSEM_REG_FAST_MEMORY + 0x2000 + 0x6cc, 0x10223}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x2}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x810, 0x4}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1fa0, 0x4}, - {OP_SW, TSEM_REG_FAST_MEMORY + 0x4cf0, 0x80224}, - {OP_ZP, TSEM_REG_INT_TABLE, 0x8c022c}, - {OP_ZP, TSEM_REG_PRAM, 0x3395024f}, - {OP_ZP, TSEM_REG_PRAM + 0x8000, 0x2c760f35}, - {OP_ZP, TSEM_REG_PRAM + 0x10000, 0x5e1a53}, - {OP_ZP, TSEM_REG_PRAM + 0x18000, 0x5e1a6b}, - {OP_ZP, TSEM_REG_PRAM + 0x20000, 0x5e1a83}, - {OP_ZP, TSEM_REG_PRAM + 0x28000, 0x5e1a9b}, - {OP_ZP, TSEM_REG_PRAM + 0x30000, 0x5e1ab3}, - {OP_ZP, TSEM_REG_PRAM + 0x38000, 0x5e1acb}, -#define TSEM_COMMON_END 202 -#define TSEM_PORT0_START 202 - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x16c}, - {OP_SW, TSEM_REG_FAST_MEMORY + 0x4000 + 0x5b0, 0x21ae3}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1370, 0xa}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x13c0, 0x6}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1418, 0xc}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1478, 0x12}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1508, 0x90}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x820, 0x10}, - {OP_SW, TSEM_REG_FAST_MEMORY + 0x820 + 0x40, 0x21ae5}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2908, 0xa}, -#define TSEM_PORT0_END 213 -#define TSEM_PORT1_START 213 - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x45b8, 0x16c}, - {OP_SW, TSEM_REG_FAST_MEMORY + 0x45b8 + 0x5b0, 0x21ae7}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1398, 0xa}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x13d8, 0x6}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1448, 0xc}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x14c0, 0x12}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1748, 0x90}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x868, 0x10}, - {OP_SW, TSEM_REG_FAST_MEMORY + 0x868 + 0x40, 0x21ae9}, - {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2930, 0xa}, -#define TSEM_PORT1_END 224 -#define MISC_COMMON_START 224 - {OP_WR, MISC_REG_GRC_TIMEOUT_EN, 0x1}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2000, 0xb2}, + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x1}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x23c8, 0xc1}, + {OP_WR_EMUL_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x0}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x23c8 + 0x304, 0x10223}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x1000, 0x2b3}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x1000 + 0xacc, 0x10223}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1000, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c18, 0x4}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa000, 0x2}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad0, 0x0}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3b28, 0x6}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x810, 0x4}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x40224}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5008, 0x4}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x80228}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5018, 0x4}, + {OP_ZP_E1, TSEM_REG_INT_TABLE, 0x940000}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4}, + {OP_WR_64_E1, TSEM_REG_INT_TABLE + 0x360, 0x140230}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5038, 0x4}, + {OP_ZP_E1, TSEM_REG_PRAM, 0x6ab70000}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5048, 0x4}, + {OP_WR_64_E1, TSEM_REG_PRAM + 0x117f0, 0x5d020232}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5058, 0x4}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5068, 0x4}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5078, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x6140, 0x200224}, + {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x960000}, + {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x360, 0x140244}, + {OP_ZP_E1H, TSEM_REG_PRAM, 0x6d080000}, + {OP_WR_64_E1H, TSEM_REG_PRAM + 0x11c70, 0x5c720246}, +#define TSEM_COMMON_END 272 +#define TSEM_PORT0_START 272 + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x2000, 0x16c}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0xfc}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb000, 0x28}, + {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b60, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb140, 0xc}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1400, 0xa}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32c0, 0x12}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1450, 0x6}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0xfa}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8108, 0x2}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1570, 0x12}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0xbe}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x820, 0xe}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20234}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2908, 0x2}, +#define TSEM_PORT0_END 290 +#define TSEM_PORT1_START 290 + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2348, 0x20}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x25b0, 0x16c}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x43f0, 0xfc}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28}, + {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b64, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb170, 0xc}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1428, 0xa}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3308, 0x12}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1468, 0x6}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3738, 0xfa}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8110, 0x2}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x15b8, 0x12}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xcb8, 0xbe}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x858, 0xe}, + {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20236}, + {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2910, 0x2}, +#define TSEM_PORT1_END 308 +#define TSEM_FUNC0_START 308 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b60, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31c0, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5080, 0x12}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, +#define TSEM_FUNC0_END 314 +#define TSEM_FUNC1_START 314 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b64, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31e0, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5010, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, +#define TSEM_FUNC1_END 320 +#define TSEM_FUNC2_START 320 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b68, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3200, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5020, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5110, 0x12}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20248}, +#define TSEM_FUNC2_END 326 +#define TSEM_FUNC3_START 326 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b6c, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3220, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5030, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5158, 0x12}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2024a}, +#define TSEM_FUNC3_END 332 +#define TSEM_FUNC4_START 332 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b70, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3240, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5040, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x2024c}, +#define TSEM_FUNC4_END 338 +#define TSEM_FUNC5_START 338 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b74, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3260, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5050, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2024e}, +#define TSEM_FUNC5_END 344 +#define TSEM_FUNC6_START 344 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b78, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3280, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5060, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5230, 0x12}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20250}, +#define TSEM_FUNC6_END 350 +#define TSEM_FUNC7_START 350 + {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b7c, 0x0}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0xe}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5070, 0x2}, + {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5278, 0x12}, + {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x20252}, +#define TSEM_FUNC7_END 356 +#define MISC_COMMON_START 356 + {OP_WR_E1, MISC_REG_GRC_TIMEOUT_EN, 0x1}, {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911}, {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0}, {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424}, {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0}, {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209}, -#define MISC_COMMON_END 230 -#define NIG_COMMON_START 230 + {OP_WR_E1, MISC_REG_SPIO, 0xff000000}, +#define MISC_COMMON_END 363 +#define MISC_FUNC0_START 363 + {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, +#define MISC_FUNC0_END 364 +#define MISC_FUNC1_START 364 + {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, +#define MISC_FUNC1_END 365 +#define MISC_FUNC2_START 365 + {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, +#define MISC_FUNC2_END 366 +#define MISC_FUNC3_START 366 + {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, +#define MISC_FUNC3_END 367 +#define MISC_FUNC4_START 367 + {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, +#define MISC_FUNC4_END 368 +#define MISC_FUNC5_START 368 + {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, +#define MISC_FUNC5_END 369 +#define MISC_FUNC6_START 369 + {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, +#define MISC_FUNC6_END 370 +#define MISC_FUNC7_START 370 + {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, +#define MISC_FUNC7_END 371 +#define NIG_COMMON_START 371 {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1}, {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1}, {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1}, {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1}, {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1}, -#define NIG_COMMON_END 235 -#define NIG_PORT0_START 235 +#define NIG_COMMON_END 376 +#define NIG_PORT0_START 376 {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000}, - {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x26}, + {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28}, {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0}, {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4}, {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1}, {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0}, + {OP_WR_E1H, NIG_REG_LLH0_CLS_TYPE, 0x1}, {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30}, {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1}, {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1}, {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1}, {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1}, -#define NIG_PORT0_END 246 -#define NIG_PORT1_START 246 +#define NIG_PORT0_END 388 +#define NIG_PORT1_START 388 {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000}, - {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x26}, + {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28}, {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0}, {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4}, {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1}, {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0}, + {OP_WR_E1H, NIG_REG_LLH1_CLS_TYPE, 0x1}, {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30}, {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1}, {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1}, {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1}, {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1}, -#define NIG_PORT1_END 257 -#define UPB_COMMON_START 257 +#define NIG_PORT1_END 400 +#define UPB_COMMON_START 400 {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20}, -#define UPB_COMMON_END 258 -#define CSDM_COMMON_START 258 - {OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0xa11}, - {OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, - {OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04}, +#define UPB_COMMON_END 401 +#define CSDM_COMMON_START 401 + {OP_WR_E1, CSDM_REG_CFC_RSP_START_ADDR, 0xa11}, + {OP_WR_E1H, CSDM_REG_CFC_RSP_START_ADDR, 0x211}, + {OP_WR_E1, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, + {OP_WR_E1H, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200}, + {OP_WR_E1, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04}, + {OP_WR_E1H, CSDM_REG_Q_COUNTER_START_ADDR, 0x204}, {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff}, {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff}, {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff}, {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff}, - {OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x80}, + {OP_WR, CSDM_REG_AGG_INT_EVENT_0, 0xc6}, + {OP_WR, CSDM_REG_AGG_INT_EVENT_1, 0x0}, + {OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34}, + {OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35}, + {OP_ZR, CSDM_REG_AGG_INT_EVENT_4, 0x1c}, + {OP_WR, CSDM_REG_AGG_INT_T_0, 0x1}, + {OP_ZR, CSDM_REG_AGG_INT_T_1, 0x5f}, {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff}, {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f}, {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff}, @@ -340,19 +542,29 @@ static const struct raw_op init_ops[] = { {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, - {OP_WR, CSDM_REG_TIMER_TICK, 0x3e8}, -#define CSDM_COMMON_END 285 -#define USDM_COMMON_START 285 - {OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0xa11}, - {OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, - {OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0xa04}, - {OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21}, + {OP_WR_E1, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1}, + {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8}, + {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1}, + {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa}, +#define CSDM_COMMON_END 440 +#define USDM_COMMON_START 440 + {OP_WR_E1, USDM_REG_CFC_RSP_START_ADDR, 0xa11}, + {OP_WR_E1H, USDM_REG_CFC_RSP_START_ADDR, 0x411}, + {OP_WR_E1, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, + {OP_WR_E1H, USDM_REG_CMP_COUNTER_START_ADDR, 0x400}, + {OP_WR_E1, USDM_REG_Q_COUNTER_START_ADDR, 0xa04}, + {OP_WR_E1H, USDM_REG_Q_COUNTER_START_ADDR, 0x404}, + {OP_WR_E1, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21}, + {OP_WR_E1H, USDM_REG_PCK_END_MSG_START_ADDR, 0x421}, {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff}, {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff}, {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff}, {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff}, {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46}, - {OP_ZR, USDM_REG_AGG_INT_EVENT_1, 0x5f}, + {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5}, + {OP_WR, USDM_REG_AGG_INT_EVENT_2, 0x34}, + {OP_WR, USDM_REG_AGG_INT_EVENT_3, 0x35}, + {OP_ZR, USDM_REG_AGG_INT_EVENT_4, 0x5c}, {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1}, {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f}, {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff}, @@ -374,9 +586,12 @@ static const struct raw_op init_ops[] = { {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0}, {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, - {OP_WR, USDM_REG_TIMER_TICK, 0x3e8}, -#define USDM_COMMON_END 317 -#define CCM_COMMON_START 317 + {OP_WR_E1, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1}, + {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8}, + {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1}, + {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa}, +#define USDM_COMMON_END 482 +#define CCM_COMMON_START 482 {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32}, {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020}, {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020}, @@ -401,23 +616,28 @@ static const struct raw_op init_ops[] = { {OP_WR, CCM_REG_XX_INIT_CRD, 0x3}, {OP_WR, CCM_REG_XX_MSG_NUM, 0x18}, {OP_ZR, CCM_REG_XX_TABLE, 0x12}, - {OP_SW, CCM_REG_XX_DESCR_TABLE, 0x241aeb}, + {OP_SW_E1, CCM_REG_XX_DESCR_TABLE, 0x240238}, + {OP_SW_E1H, CCM_REG_XX_DESCR_TABLE, 0x240254}, {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1}, {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2}, {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8}, {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8}, {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4}, {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4}, - {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9}, - {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29}, - {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa}, - {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a}, - {OP_ZR, CCM_REG_QOS_PHYS_QNUM2_0, 0x4}, - {OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc}, - {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c}, - {OP_WR, CCM_REG_PHYS_QNUM2_0, 0xb}, - {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2b}, - {OP_ZR, CCM_REG_PHYS_QNUM3_0, 0x2}, + {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_0, 0x9}, + {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_1, 0x29}, + {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_0, 0xa}, + {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a}, + {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_0, 0x7}, + {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_1, 0x27}, + {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_0, 0x7}, + {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_1, 0x27}, + {OP_WR_E1, CCM_REG_PHYS_QNUM1_0, 0xc}, + {OP_WR_E1, CCM_REG_PHYS_QNUM1_1, 0x2c}, + {OP_WR_E1, CCM_REG_PHYS_QNUM2_0, 0xc}, + {OP_WR_E1, CCM_REG_PHYS_QNUM2_1, 0x2c}, + {OP_WR_E1, CCM_REG_PHYS_QNUM3_0, 0xc}, + {OP_WR_E1, CCM_REG_PHYS_QNUM3_1, 0x2c}, {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1}, {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1}, {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1}, @@ -433,8 +653,80 @@ static const struct raw_op init_ops[] = { {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1}, {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1}, {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1}, -#define CCM_COMMON_END 373 -#define UCM_COMMON_START 373 +#define CCM_COMMON_END 543 +#define CCM_FUNC0_START 543 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x9}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0xa}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x7}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x7}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0xc}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0xb}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x7}, +#define CCM_FUNC0_END 550 +#define CCM_FUNC1_START 550 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x29}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x27}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x27}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x2c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x2b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x27}, +#define CCM_FUNC1_END 557 +#define CCM_FUNC2_START 557 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x19}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x17}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x17}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x1c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x1b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x17}, +#define CCM_FUNC2_END 564 +#define CCM_FUNC3_START 564 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x39}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x37}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x37}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x3c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x3b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x37}, +#define CCM_FUNC3_END 571 +#define CCM_FUNC4_START 571 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x49}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x47}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x47}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x4c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x4b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x47}, +#define CCM_FUNC4_END 578 +#define CCM_FUNC5_START 578 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x69}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x67}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x67}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x6c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x6b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x67}, +#define CCM_FUNC5_END 585 +#define CCM_FUNC6_START 585 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x59}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x57}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x57}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x5c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x5b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x57}, +#define CCM_FUNC6_END 592 +#define CCM_FUNC7_START 592 + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x79}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x77}, + {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x77}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x7c}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x7b}, + {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x77}, +#define CCM_FUNC7_END 599 +#define UCM_COMMON_START 599 {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32}, {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020}, {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020}, @@ -457,20 +749,23 @@ static const struct raw_op init_ops[] = { {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40}, {OP_WR, UCM_REG_TM_INIT_CRD, 0x4}, {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20}, - {OP_WR, UCM_REG_XX_INIT_CRD, 0xc}, - {OP_WR, UCM_REG_XX_MSG_NUM, 0x20}, + {OP_WR, UCM_REG_XX_INIT_CRD, 0xe}, + {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b}, {OP_ZR, UCM_REG_XX_TABLE, 0x12}, - {OP_SW, UCM_REG_XX_DESCR_TABLE, 0x201b0f}, - {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xa}, + {OP_SW_E1, UCM_REG_XX_DESCR_TABLE, 0x1b025c}, + {OP_SW_E1H, UCM_REG_XX_DESCR_TABLE, 0x1b0278}, + {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0x10}, {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7}, {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf}, {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10}, - {OP_ZR, UCM_REG_N_SM_CTX_LD_4, 0x4}, + {OP_ZR_E1, UCM_REG_N_SM_CTX_LD_4, 0x4}, + {OP_WR_E1H, UCM_REG_N_SM_CTX_LD_4, 0xd}, + {OP_ZR_E1H, UCM_REG_N_SM_CTX_LD_5, 0x3}, {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3}, - {OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf}, - {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f}, - {OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe}, - {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e}, + {OP_WR_E1, UCM_REG_PHYS_QNUM0_0, 0xf}, + {OP_WR_E1, UCM_REG_PHYS_QNUM0_1, 0x2f}, + {OP_WR_E1, UCM_REG_PHYS_QNUM1_0, 0xe}, + {OP_WR_E1, UCM_REG_PHYS_QNUM1_1, 0x2e}, {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1}, {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1}, {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1}, @@ -488,8 +783,56 @@ static const struct raw_op init_ops[] = { {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1}, {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1}, {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1}, -#define UCM_COMMON_END 426 -#define USEM_COMMON_START 426 +#define UCM_COMMON_END 655 +#define UCM_FUNC0_START 655 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0xf}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0xe}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, +#define UCM_FUNC0_END 659 +#define UCM_FUNC1_START 659 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x2f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x2e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, +#define UCM_FUNC1_END 663 +#define UCM_FUNC2_START 663 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x1f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x1e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, +#define UCM_FUNC2_END 667 +#define UCM_FUNC3_START 667 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x3f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x3e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, +#define UCM_FUNC3_END 671 +#define UCM_FUNC4_START 671 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x4f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x4e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, +#define UCM_FUNC4_END 675 +#define UCM_FUNC5_START 675 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x6f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x6e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, +#define UCM_FUNC5_END 679 +#define UCM_FUNC6_START 679 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x5f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x5e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, +#define UCM_FUNC6_END 683 +#define UCM_FUNC7_START 683 + {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x7f}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x7e}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, + {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, +#define UCM_FUNC7_END 687 +#define USEM_COMMON_START 687 {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0}, {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0}, {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0}, @@ -533,87 +876,191 @@ static const struct raw_op init_ops[] = { {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e}, {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10}, {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20}, - {OP_WR, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, + {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, + {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138}, + {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388}, {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, - {OP_WR, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x102}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1020, 0xc8}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x2}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1e20, 0x40}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3000, 0x400}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x2400, 0x2}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x2408, 0x2}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x2410, 0x6}, - {OP_SW, USEM_REG_FAST_MEMORY + 0x2410 + 0x18, 0x21b2f}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b68, 0x2}, - {OP_SW, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x21b31}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b10, 0x2}, - {OP_SW, USEM_REG_FAST_MEMORY + 0x2c30, 0x21b33}, + {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, + {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4}, + {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5000, 0x102}, + {OP_WR_EMUL_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x0}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1020, 0xc8}, + {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x1}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1000, 0x2}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2000, 0x102}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57e8, 0x4}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8020, 0xc8}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57d0, 0x5}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8000, 0x2}, + {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x57d0 + 0x14, 0x10277}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x400}, + {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c00, 0x2}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42}, + {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2c00 + 0x8, 0x20278}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2}, + {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x2027a}, + {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2}, + {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027c}, + {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296}, + {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2}, + {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298}, {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, - {OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x101b35}, + {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027e}, + {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a}, {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0}, - {OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x101b45}, - {OP_ZP, USEM_REG_INT_TABLE, 0xb41b55}, - {OP_ZP, USEM_REG_PRAM, 0x32d01b82}, - {OP_ZP, USEM_REG_PRAM + 0x8000, 0x32172836}, - {OP_ZP, USEM_REG_PRAM + 0x10000, 0x1a7a34bc}, - {OP_ZP, USEM_REG_PRAM + 0x18000, 0x5f3b5b}, - {OP_ZP, USEM_REG_PRAM + 0x20000, 0x5f3b73}, - {OP_ZP, USEM_REG_PRAM + 0x28000, 0x5f3b8b}, - {OP_ZP, USEM_REG_PRAM + 0x30000, 0x5f3ba3}, - {OP_ZP, USEM_REG_PRAM + 0x38000, 0x5f3bbb}, -#define USEM_COMMON_END 498 -#define USEM_PORT0_START 498 - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1400, 0xa0}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1900, 0xa}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1950, 0x2e}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1d00, 0x24}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3000, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3100, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3200, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3300, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3400, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3500, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3600, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3700, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3800, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3900, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3a00, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3b00, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3c00, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d00, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3e00, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3f00, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x2400, 0x2}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, -#define USEM_PORT0_END 521 -#define USEM_PORT1_START 521 - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1680, 0xa0}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1928, 0xa}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1a08, 0x2e}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x1d90, 0x24}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3080, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3180, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3280, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3380, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3480, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3580, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3680, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3780, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3880, 0x20}, - {OP_ZR, USEM_REG_FAST_MEMORY + 0x3980, 0x2 |