diff options
author | Eilon Greenstein <eilong@broadcom.com> | 2008-06-23 20:31:40 -0700 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-06-23 20:31:40 -0700 |
commit | 74bc8ebcfd56a1ea01d855d9eebc2533cef66f19 (patch) | |
tree | dbbdac823a1ec2dd99f040809a84a1eb9db02dee /drivers/net/bnx2x_init_values.h | |
parent | 523cb50b265360e87152382ea0984b624e4f7d29 (diff) |
bnx2x: New microcode part 1/3
The new Microcode BLOB - broken into a separate patch to make it small
enough for the mailing list
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_init_values.h')
-rw-r--r-- | drivers/net/bnx2x_init_values.h | 4604 |
1 files changed, 4354 insertions, 250 deletions
diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h index ec3bd85962ea..590b076cce30 100644 --- a/drivers/net/bnx2x_init_values.h +++ b/drivers/net/bnx2x_init_values.h @@ -317,21 +317,25 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4}, {OP_WR_64_E1, TSEM_REG_INT_TABLE + 0x360, 0x140230}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5038, 0x4}, - {OP_ZP_E1, TSEM_REG_PRAM, 0x6ab70000}, + {OP_ZP_E1, TSEM_REG_PRAM, 0x30b10000}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5048, 0x4}, - {OP_WR_64_E1, TSEM_REG_PRAM + 0x117f0, 0x5d020232}, + {OP_ZP_E1, TSEM_REG_PRAM + 0x8000, 0x33c50c2d}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5058, 0x4}, + {OP_ZP_E1, TSEM_REG_PRAM + 0x10000, 0xbc6191f}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5068, 0x4}, + {OP_WR_64_E1, TSEM_REG_PRAM + 0x117f0, 0x5d020232}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5078, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x6140, 0x200224}, {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x960000}, {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x360, 0x140244}, - {OP_ZP_E1H, TSEM_REG_PRAM, 0x6d080000}, + {OP_ZP_E1H, TSEM_REG_PRAM, 0x30cc0000}, + {OP_ZP_E1H, TSEM_REG_PRAM + 0x8000, 0x33df0c33}, + {OP_ZP_E1H, TSEM_REG_PRAM + 0x10000, 0xdce192b}, {OP_WR_64_E1H, TSEM_REG_PRAM + 0x11c70, 0x5c720246}, -#define TSEM_COMMON_END 272 -#define TSEM_PORT0_START 272 +#define TSEM_COMMON_END 276 +#define TSEM_PORT0_START 276 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x2000, 0x16c}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0xfc}, @@ -350,8 +354,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x820, 0xe}, {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20234}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2908, 0x2}, -#define TSEM_PORT0_END 290 -#define TSEM_PORT1_START 290 +#define TSEM_PORT0_END 294 +#define TSEM_PORT1_START 294 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2348, 0x20}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x25b0, 0x16c}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x43f0, 0xfc}, @@ -370,72 +374,72 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x858, 0xe}, {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20236}, {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2910, 0x2}, -#define TSEM_PORT1_END 308 -#define TSEM_FUNC0_START 308 +#define TSEM_PORT1_END 312 +#define TSEM_FUNC0_START 312 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b60, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0xe}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31c0, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5080, 0x12}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2}, -#define TSEM_FUNC0_END 314 -#define TSEM_FUNC1_START 314 +#define TSEM_FUNC0_END 318 +#define TSEM_FUNC1_START 318 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b64, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0xe}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31e0, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5010, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2}, -#define TSEM_FUNC1_END 320 -#define TSEM_FUNC2_START 320 +#define TSEM_FUNC1_END 324 +#define TSEM_FUNC2_START 324 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b68, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0xe}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3200, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5020, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5110, 0x12}, {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20248}, -#define TSEM_FUNC2_END 326 -#define TSEM_FUNC3_START 326 +#define TSEM_FUNC2_END 330 +#define TSEM_FUNC3_START 330 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b6c, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0xe}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3220, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5030, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5158, 0x12}, {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2024a}, -#define TSEM_FUNC3_END 332 -#define TSEM_FUNC4_START 332 +#define TSEM_FUNC3_END 336 +#define TSEM_FUNC4_START 336 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b70, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0xe}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3240, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5040, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12}, {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x2024c}, -#define TSEM_FUNC4_END 338 -#define TSEM_FUNC5_START 338 +#define TSEM_FUNC4_END 342 +#define TSEM_FUNC5_START 342 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b74, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0xe}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3260, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5050, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12}, {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2024e}, -#define TSEM_FUNC5_END 344 -#define TSEM_FUNC6_START 344 +#define TSEM_FUNC5_END 348 +#define TSEM_FUNC6_START 348 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b78, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0xe}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3280, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5060, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5230, 0x12}, {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20250}, -#define TSEM_FUNC6_END 350 -#define TSEM_FUNC7_START 350 +#define TSEM_FUNC6_END 354 +#define TSEM_FUNC7_START 354 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b7c, 0x0}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0xe}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5070, 0x2}, {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5278, 0x12}, {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x20252}, -#define TSEM_FUNC7_END 356 -#define MISC_COMMON_START 356 +#define TSEM_FUNC7_END 360 +#define MISC_COMMON_START 360 {OP_WR_E1, MISC_REG_GRC_TIMEOUT_EN, 0x1}, {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911}, {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0}, @@ -443,39 +447,39 @@ static const struct raw_op init_ops[] = { {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0}, {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209}, {OP_WR_E1, MISC_REG_SPIO, 0xff000000}, -#define MISC_COMMON_END 363 -#define MISC_FUNC0_START 363 +#define MISC_COMMON_END 367 +#define MISC_FUNC0_START 367 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, -#define MISC_FUNC0_END 364 -#define MISC_FUNC1_START 364 +#define MISC_FUNC0_END 368 +#define MISC_FUNC1_START 368 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, -#define MISC_FUNC1_END 365 -#define MISC_FUNC2_START 365 +#define MISC_FUNC1_END 369 +#define MISC_FUNC2_START 369 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, -#define MISC_FUNC2_END 366 -#define MISC_FUNC3_START 366 +#define MISC_FUNC2_END 370 +#define MISC_FUNC3_START 370 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, -#define MISC_FUNC3_END 367 -#define MISC_FUNC4_START 367 +#define MISC_FUNC3_END 371 +#define MISC_FUNC4_START 371 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, -#define MISC_FUNC4_END 368 -#define MISC_FUNC5_START 368 +#define MISC_FUNC4_END 372 +#define MISC_FUNC5_START 372 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, -#define MISC_FUNC5_END 369 -#define MISC_FUNC6_START 369 +#define MISC_FUNC5_END 373 +#define MISC_FUNC6_START 373 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0}, -#define MISC_FUNC6_END 370 -#define MISC_FUNC7_START 370 +#define MISC_FUNC6_END 374 +#define MISC_FUNC7_START 374 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0}, -#define MISC_FUNC7_END 371 -#define NIG_COMMON_START 371 +#define MISC_FUNC7_END 375 +#define NIG_COMMON_START 375 {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1}, {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1}, {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1}, {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1}, {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1}, -#define NIG_COMMON_END 376 -#define NIG_PORT0_START 376 +#define NIG_COMMON_END 380 +#define NIG_PORT0_START 380 {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000}, {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28}, {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0}, @@ -488,8 +492,8 @@ static const struct raw_op init_ops[] = { {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1}, {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1}, {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1}, -#define NIG_PORT0_END 388 -#define NIG_PORT1_START 388 +#define NIG_PORT0_END 392 +#define NIG_PORT1_START 392 {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000}, {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28}, {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0}, @@ -502,11 +506,11 @@ static const struct raw_op init_ops[] = { {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1}, {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1}, {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1}, -#define NIG_PORT1_END 400 -#define UPB_COMMON_START 400 +#define NIG_PORT1_END 404 +#define UPB_COMMON_START 404 {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20}, -#define UPB_COMMON_END 401 -#define CSDM_COMMON_START 401 +#define UPB_COMMON_END 405 +#define CSDM_COMMON_START 405 {OP_WR_E1, CSDM_REG_CFC_RSP_START_ADDR, 0xa11}, {OP_WR_E1H, CSDM_REG_CFC_RSP_START_ADDR, 0x211}, {OP_WR_E1, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, @@ -546,8 +550,8 @@ static const struct raw_op init_ops[] = { {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8}, {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1}, {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa}, -#define CSDM_COMMON_END 440 -#define USDM_COMMON_START 440 +#define CSDM_COMMON_END 444 +#define USDM_COMMON_START 444 {OP_WR_E1, USDM_REG_CFC_RSP_START_ADDR, 0xa11}, {OP_WR_E1H, USDM_REG_CFC_RSP_START_ADDR, 0x411}, {OP_WR_E1, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, @@ -590,8 +594,8 @@ static const struct raw_op init_ops[] = { {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8}, {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1}, {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa}, -#define USDM_COMMON_END 482 -#define CCM_COMMON_START 482 +#define USDM_COMMON_END 486 +#define CCM_COMMON_START 486 {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32}, {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020}, {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020}, @@ -653,8 +657,8 @@ static const struct raw_op init_ops[] = { {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1}, {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1}, {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1}, -#define CCM_COMMON_END 543 -#define CCM_FUNC0_START 543 +#define CCM_COMMON_END 547 +#define CCM_FUNC0_START 547 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x9}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0xa}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x7}, @@ -662,8 +666,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0xc}, {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0xb}, {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x7}, -#define CCM_FUNC0_END 550 -#define CCM_FUNC1_START 550 +#define CCM_FUNC0_END 554 +#define CCM_FUNC1_START 554 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x29}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x27}, @@ -671,8 +675,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x2c}, {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x2b}, {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x27}, -#define CCM_FUNC1_END 557 -#define CCM_FUNC2_START 557 +#define CCM_FUNC1_END 561 +#define CCM_FUNC2_START 561 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x19}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x17}, @@ -680,8 +684,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x1c}, {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x1b}, {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x17}, -#define CCM_FUNC2_END 564 -#define CCM_FUNC3_START 564 +#define CCM_FUNC2_END 568 +#define CCM_FUNC3_START 568 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x39}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x37}, @@ -689,8 +693,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x3c}, {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x3b}, {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x37}, -#define CCM_FUNC3_END 571 -#define CCM_FUNC4_START 571 +#define CCM_FUNC3_END 575 +#define CCM_FUNC4_START 575 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x49}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x47}, @@ -698,8 +702,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x4c}, {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x4b}, {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x47}, -#define CCM_FUNC4_END 578 -#define CCM_FUNC5_START 578 +#define CCM_FUNC4_END 582 +#define CCM_FUNC5_START 582 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x69}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x67}, @@ -707,8 +711,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x6c}, {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x6b}, {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x67}, -#define CCM_FUNC5_END 585 -#define CCM_FUNC6_START 585 +#define CCM_FUNC5_END 589 +#define CCM_FUNC6_START 589 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x59}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x57}, @@ -716,8 +720,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x5c}, {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x5b}, {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x57}, -#define CCM_FUNC6_END 592 -#define CCM_FUNC7_START 592 +#define CCM_FUNC6_END 596 +#define CCM_FUNC7_START 596 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x79}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a}, {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x77}, @@ -725,8 +729,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x7c}, {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x7b}, {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x77}, -#define CCM_FUNC7_END 599 -#define UCM_COMMON_START 599 +#define CCM_FUNC7_END 603 +#define UCM_COMMON_START 603 {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32}, {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020}, {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020}, @@ -783,56 +787,56 @@ static const struct raw_op init_ops[] = { {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1}, {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1}, {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1}, -#define UCM_COMMON_END 655 -#define UCM_FUNC0_START 655 +#define UCM_COMMON_END 659 +#define UCM_FUNC0_START 659 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0xf}, {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0xe}, {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, -#define UCM_FUNC0_END 659 -#define UCM_FUNC1_START 659 +#define UCM_FUNC0_END 663 +#define UCM_FUNC1_START 663 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x2f}, {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x2e}, {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, -#define UCM_FUNC1_END 663 -#define UCM_FUNC2_START 663 +#define UCM_FUNC1_END 667 +#define UCM_FUNC2_START 667 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x1f}, {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x1e}, {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, -#define UCM_FUNC2_END 667 -#define UCM_FUNC3_START 667 +#define UCM_FUNC2_END 671 +#define UCM_FUNC3_START 671 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x3f}, {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x3e}, {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, -#define UCM_FUNC3_END 671 -#define UCM_FUNC4_START 671 +#define UCM_FUNC3_END 675 +#define UCM_FUNC4_START 675 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x4f}, {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x4e}, {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, -#define UCM_FUNC4_END 675 -#define UCM_FUNC5_START 675 +#define UCM_FUNC4_END 679 +#define UCM_FUNC5_START 679 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x6f}, {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x6e}, {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, -#define UCM_FUNC5_END 679 -#define UCM_FUNC6_START 679 +#define UCM_FUNC5_END 683 +#define UCM_FUNC6_START 683 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x5f}, {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x5e}, {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0}, {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0}, -#define UCM_FUNC6_END 683 -#define UCM_FUNC7_START 683 +#define UCM_FUNC6_END 687 +#define UCM_FUNC7_START 687 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x7f}, {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x7e}, {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0}, {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0}, -#define UCM_FUNC7_END 687 -#define USEM_COMMON_START 687 +#define UCM_FUNC7_END 691 +#define USEM_COMMON_START 691 {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0}, {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0}, {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0}, @@ -923,12 +927,17 @@ static const struct raw_op init_ops[] = { {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000}, {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029e}, {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba}, - {OP_ZP_E1, USEM_REG_PRAM, 0x975a0000}, - {OP_ZP_E1H, USEM_REG_PRAM, 0x985c0000}, - {OP_WR_64_E1, USEM_REG_PRAM + 0x17f90, 0x500e02a0}, - {OP_WR_64_E1H, USEM_REG_PRAM + 0x18200, 0x4fc002bc}, -#define USEM_COMMON_END 781 -#define USEM_PORT0_START 781 + {OP_ZP_E1, USEM_REG_PRAM, 0x311c0000}, + {OP_ZP_E1H, USEM_REG_PRAM, 0x31070000}, + {OP_ZP_E1, USEM_REG_PRAM + 0x8000, 0x33450c47}, + {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x330e0c42}, + {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x38561919}, + {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x389b1906}, + {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x500402a0}, + {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x132272d}, + {OP_WR_64_E1H, USEM_REG_PRAM + 0x18250, 0x4fb602bc}, +#define USEM_COMMON_END 790 +#define USEM_PORT0_START 790 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa}, @@ -977,8 +986,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, -#define USEM_PORT0_END 829 -#define USEM_PORT1_START 829 +#define USEM_PORT0_END 838 +#define USEM_PORT1_START 838 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa}, @@ -1027,40 +1036,40 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc}, -#define USEM_PORT1_END 877 -#define USEM_FUNC0_START 877 +#define USEM_PORT1_END 886 +#define USEM_FUNC0_START 886 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2}, -#define USEM_FUNC0_END 879 -#define USEM_FUNC1_START 879 +#define USEM_FUNC0_END 888 +#define USEM_FUNC1_START 888 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2}, -#define USEM_FUNC1_END 881 -#define USEM_FUNC2_START 881 +#define USEM_FUNC1_END 890 +#define USEM_FUNC2_START 890 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2}, -#define USEM_FUNC2_END 883 -#define USEM_FUNC3_START 883 +#define USEM_FUNC2_END 892 +#define USEM_FUNC3_START 892 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2}, -#define USEM_FUNC3_END 885 -#define USEM_FUNC4_START 885 +#define USEM_FUNC3_END 894 +#define USEM_FUNC4_START 894 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2}, -#define USEM_FUNC4_END 887 -#define USEM_FUNC5_START 887 +#define USEM_FUNC4_END 896 +#define USEM_FUNC5_START 896 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2}, -#define USEM_FUNC5_END 889 -#define USEM_FUNC6_START 889 +#define USEM_FUNC5_END 898 +#define USEM_FUNC6_START 898 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2}, -#define USEM_FUNC6_END 891 -#define USEM_FUNC7_START 891 +#define USEM_FUNC6_END 900 +#define USEM_FUNC7_START 900 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2}, -#define USEM_FUNC7_END 893 -#define CSEM_COMMON_START 893 +#define USEM_FUNC7_END 902 +#define CSEM_COMMON_START 902 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0}, {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0}, {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0}, @@ -1134,12 +1143,14 @@ static const struct raw_op init_ops[] = { {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000}, {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002ca}, {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe}, - {OP_ZP_E1, CSEM_REG_PRAM, 0x48bc0000}, - {OP_ZP_E1H, CSEM_REG_PRAM, 0x493d0000}, + {OP_ZP_E1, CSEM_REG_PRAM, 0x32580000}, + {OP_ZP_E1H, CSEM_REG_PRAM, 0x31fa0000}, + {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x18270c96}, + {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x19040c7f}, {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402cc}, {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300}, -#define CSEM_COMMON_END 970 -#define CSEM_PORT0_START 970 +#define CSEM_COMMON_END 981 +#define CSEM_PORT0_START 981 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10}, @@ -1152,8 +1163,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30}, -#define CSEM_PORT0_END 982 -#define CSEM_PORT1_START 982 +#define CSEM_PORT0_END 993 +#define CSEM_PORT1_START 993 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10}, @@ -1166,43 +1177,43 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30}, -#define CSEM_PORT1_END 994 -#define CSEM_FUNC0_START 994 +#define CSEM_PORT1_END 1005 +#define CSEM_FUNC0_START 1005 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2}, -#define CSEM_FUNC0_END 996 -#define CSEM_FUNC1_START 996 +#define CSEM_FUNC0_END 1007 +#define CSEM_FUNC1_START 1007 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2}, -#define CSEM_FUNC1_END 998 -#define CSEM_FUNC2_START 998 +#define CSEM_FUNC1_END 1009 +#define CSEM_FUNC2_START 1009 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2}, -#define CSEM_FUNC2_END 1000 -#define CSEM_FUNC3_START 1000 +#define CSEM_FUNC2_END 1011 +#define CSEM_FUNC3_START 1011 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2}, -#define CSEM_FUNC3_END 1002 -#define CSEM_FUNC4_START 1002 +#define CSEM_FUNC3_END 1013 +#define CSEM_FUNC4_START 1013 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2}, -#define CSEM_FUNC4_END 1004 -#define CSEM_FUNC5_START 1004 +#define CSEM_FUNC4_END 1015 +#define CSEM_FUNC5_START 1015 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2}, -#define CSEM_FUNC5_END 1006 -#define CSEM_FUNC6_START 1006 +#define CSEM_FUNC5_END 1017 +#define CSEM_FUNC6_START 1017 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2}, -#define CSEM_FUNC6_END 1008 -#define CSEM_FUNC7_START 1008 +#define CSEM_FUNC6_END 1019 +#define CSEM_FUNC7_START 1019 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2}, -#define CSEM_FUNC7_END 1010 -#define XPB_COMMON_START 1010 +#define CSEM_FUNC7_END 1021 +#define XPB_COMMON_START 1021 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20}, -#define XPB_COMMON_END 1011 -#define DQ_COMMON_START 1011 +#define XPB_COMMON_END 1022 +#define DQ_COMMON_START 1022 {OP_WR, DORQ_REG_MODE_ACT, 0x2}, {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3}, {OP_WR, DORQ_REG_OUTST_REQ, 0x4}, @@ -1221,8 +1232,8 @@ static const struct raw_op init_ops[] = { {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c}, {OP_WR, DORQ_REG_REGN, 0x7c1004}, {OP_WR, DORQ_REG_IF_EN, 0xf}, -#define DQ_COMMON_END 1029 -#define TIMERS_COMMON_START 1029 +#define DQ_COMMON_END 1040 +#define TIMERS_COMMON_START 1040 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2}, {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c}, {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1}, @@ -1245,14 +1256,14 @@ static const struct raw_op init_ops[] = { {OP_WR, TM_REG_EN_CL0_INPUT, 0x1}, {OP_WR, TM_REG_EN_CL1_INPUT, 0x1}, {OP_WR, TM_REG_EN_CL2_INPUT, 0x1}, -#define TIMERS_COMMON_END 1051 -#define TIMERS_PORT0_START 1051 +#define TIMERS_COMMON_END 1062 +#define TIMERS_PORT0_START 1062 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2}, -#define TIMERS_PORT0_END 1052 -#define TIMERS_PORT1_START 1052 +#define TIMERS_PORT0_END 1063 +#define TIMERS_PORT1_START 1063 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2}, -#define TIMERS_PORT1_END 1053 -#define XSDM_COMMON_START 1053 +#define TIMERS_PORT1_END 1064 +#define XSDM_COMMON_START 1064 {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614}, {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424}, {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600}, @@ -1300,8 +1311,8 @@ static const struct raw_op init_ops[] = { {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8}, {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1}, {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa}, -#define XSDM_COMMON_END 1100 -#define QM_COMMON_START 1100 +#define XSDM_COMMON_END 1111 +#define QM_COMMON_START 1111 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6}, {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5}, {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa}, @@ -1602,8 +1613,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5}, {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7}, {OP_WR, QM_REG_CMINTEN, 0xff}, -#define QM_COMMON_END 1400 -#define PBF_COMMON_START 1400 +#define QM_COMMON_END 1411 +#define PBF_COMMON_START 1411 {OP_WR, PBF_REG_INIT, 0x1}, {OP_WR, PBF_REG_INIT_P4, 0x1}, {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1}, @@ -1611,20 +1622,20 @@ static const struct raw_op init_ops[] = { {OP_WR, PBF_REG_INIT_P4, 0x0}, {OP_WR, PBF_REG_INIT, 0x0}, {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0}, -#define PBF_COMMON_END 1407 -#define PBF_PORT0_START 1407 +#define PBF_COMMON_END 1418 +#define PBF_PORT0_START 1418 {OP_WR, PBF_REG_INIT_P0, 0x1}, {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1}, {OP_WR, PBF_REG_INIT_P0, 0x0}, {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0}, -#define PBF_PORT0_END 1411 -#define PBF_PORT1_START 1411 +#define PBF_PORT0_END 1422 +#define PBF_PORT1_START 1422 {OP_WR, PBF_REG_INIT_P1, 0x1}, {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1}, {OP_WR, PBF_REG_INIT_P1, 0x0}, {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0}, -#define PBF_PORT1_END 1415 -#define XCM_COMMON_START 1415 +#define PBF_PORT1_END 1426 +#define XCM_COMMON_START 1426 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32}, {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020}, {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020}, @@ -1689,8 +1700,8 @@ static const struct raw_op init_ops[] = { {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1}, {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1}, {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1}, -#define XCM_COMMON_END 1479 -#define XCM_PORT0_START 1479 +#define XCM_COMMON_END 1490 +#define XCM_PORT0_START 1490 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1699,8 +1710,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2}, {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, -#define XCM_PORT0_END 1487 -#define XCM_PORT1_START 1487 +#define XCM_PORT0_END 1498 +#define XCM_PORT1_START 1498 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1709,8 +1720,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2}, {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, -#define XCM_PORT1_END 1495 -#define XCM_FUNC0_START 1495 +#define XCM_PORT1_END 1506 +#define XCM_FUNC0_START 1506 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1720,8 +1731,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, -#define XCM_FUNC0_END 1504 -#define XCM_FUNC1_START 1504 +#define XCM_FUNC0_END 1515 +#define XCM_FUNC1_START 1515 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1731,8 +1742,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, -#define XCM_FUNC1_END 1513 -#define XCM_FUNC2_START 1513 +#define XCM_FUNC1_END 1524 +#define XCM_FUNC2_START 1524 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1742,8 +1753,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, -#define XCM_FUNC2_END 1522 -#define XCM_FUNC3_START 1522 +#define XCM_FUNC2_END 1533 +#define XCM_FUNC3_START 1533 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1753,8 +1764,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, -#define XCM_FUNC3_END 1531 -#define XCM_FUNC4_START 1531 +#define XCM_FUNC3_END 1542 +#define XCM_FUNC4_START 1542 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1764,8 +1775,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, -#define XCM_FUNC4_END 1540 -#define XCM_FUNC5_START 1540 +#define XCM_FUNC4_END 1551 +#define XCM_FUNC5_START 1551 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1775,8 +1786,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, -#define XCM_FUNC5_END 1549 -#define XCM_FUNC6_START 1549 +#define XCM_FUNC5_END 1560 +#define XCM_FUNC6_START 1560 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1786,8 +1797,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, -#define XCM_FUNC6_END 1558 -#define XCM_FUNC7_START 1558 +#define XCM_FUNC6_END 1569 +#define XCM_FUNC7_START 1569 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1797,8 +1808,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, -#define XCM_FUNC7_END 1567 -#define XSEM_COMMON_START 1567 +#define XCM_FUNC7_END 1578 +#define XSEM_COMMON_START 1578 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0}, {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0}, {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0}, @@ -1895,16 +1906,22 @@ static const struct raw_op init_ops[] = { {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000}, {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030f}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351}, - {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xab0000}, + {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xa90000}, {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000}, {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130317}, {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359}, - {OP_ZP_E1, XSEM_REG_PRAM, 0xc09e0000}, - {OP_ZP_E1H, XSEM_REG_PRAM, 0xc3b20000}, - {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0c0, 0x47e80319}, - {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8c0, 0x46e8035b}, -#define XSEM_COMMON_END 1671 -#define XSEM_PORT0_START 1671 + {OP_ZP_E1, XSEM_REG_PRAM, 0x344e0000}, + {OP_ZP_E1H, XSEM_REG_PRAM, 0x34620000}, + {OP_ZP_E1, XSEM_REG_PRAM + 0x8000, 0x38840d14}, + {OP_ZP_E1H, XSEM_REG_PRAM + 0x8000, 0x38240d19}, + {OP_ZP_E1, XSEM_REG_PRAM + 0x10000, 0x3e711b35}, + {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3e971b22}, + {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x1dd02ad2}, + {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x21542ac8}, + {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60319}, + {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8d0, 0x46e6035b}, +#define XSEM_COMMON_END 1688 +#define XSEM_PORT0_START 1688 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c}, @@ -1937,8 +1954,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4}, -#define XSEM_PORT0_END 1703 -#define XSEM_PORT1_START 1703 +#define XSEM_PORT0_END 1720 +#define XSEM_PORT1_START 1720 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c}, @@ -1971,48 +1988,48 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4}, -#define XSEM_PORT1_END 1735 -#define XSEM_FUNC0_START 1735 +#define XSEM_PORT1_END 1752 +#define XSEM_FUNC0_START 1752 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe}, -#define XSEM_FUNC0_END 1738 -#define XSEM_FUNC1_START 1738 +#define XSEM_FUNC0_END 1755 +#define XSEM_FUNC1_START 1755 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe}, -#define XSEM_FUNC1_END 1741 -#define XSEM_FUNC2_START 1741 +#define XSEM_FUNC1_END 1758 +#define XSEM_FUNC2_START 1758 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe}, -#define XSEM_FUNC2_END 1744 -#define XSEM_FUNC3_START 1744 +#define XSEM_FUNC2_END 1761 +#define XSEM_FUNC3_START 1761 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe}, -#define XSEM_FUNC3_END 1747 -#define XSEM_FUNC4_START 1747 +#define XSEM_FUNC3_END 1764 +#define XSEM_FUNC4_START |